Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.96	98.21	96.58	99.62	96.00	96.32	100.00	99.02

Total test records in report: 1070

T1004	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.2086081642	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:01 AM UTC 24	40695388 ps
T165	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3590488456	Sep 24 06:49:58 AM UTC 24	Sep 24 06:50:02 AM UTC 24	207392871 ps
T1005	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3464487931	Sep 24 06:49:58 AM UTC 24	Sep 24 06:50:02 AM UTC 24	140950632 ps
T1006	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.3357347994	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:02 AM UTC 24	47784283 ps
T1007	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3325960095	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:02 AM UTC 24	46199596 ps
T1008	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.1580743311	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:02 AM UTC 24	17486347 ps
T1009	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.2394757375	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:02 AM UTC 24	59956145 ps
T1010	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1756709711	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:02 AM UTC 24	195222837 ps
T119	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3460369543	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:02 AM UTC 24	24276292 ps
T1011	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.423251412	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:02 AM UTC 24	29396792 ps
T1012	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1819680644	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:02 AM UTC 24	33244666 ps
T1013	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.3090799007	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:02 AM UTC 24	55367375 ps
T1014	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2059659999	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:02 AM UTC 24	145838702 ps
T1015	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3744191430	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:02 AM UTC 24	74516342 ps
T71	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3918718776	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:02 AM UTC 24	458085727 ps
T1016	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.3447020207	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:03 AM UTC 24	345921748 ps
T1017	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.1149563604	Sep 24 06:50:00 AM UTC 24	Sep 24 06:50:03 AM UTC 24	474039691 ps
T1018	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.896449944	Sep 24 06:50:01 AM UTC 24	Sep 24 06:50:03 AM UTC 24	53427967 ps
T1019	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3490934586	Sep 24 06:50:01 AM UTC 24	Sep 24 06:50:03 AM UTC 24	87658301 ps
T1020	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.580553640	Sep 24 06:50:02 AM UTC 24	Sep 24 06:50:03 AM UTC 24	23443128 ps
T1021	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.529927363	Sep 24 06:50:01 AM UTC 24	Sep 24 06:50:03 AM UTC 24	18970481 ps
T1022	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.2468950503	Sep 24 06:50:02 AM UTC 24	Sep 24 06:50:04 AM UTC 24	24175453 ps
T1023	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2953154210	Sep 24 06:50:01 AM UTC 24	Sep 24 06:50:04 AM UTC 24	75213257 ps
T1024	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3007782875	Sep 24 06:50:02 AM UTC 24	Sep 24 06:50:04 AM UTC 24	50628974 ps
T1025	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3590518567	Sep 24 06:50:02 AM UTC 24	Sep 24 06:50:04 AM UTC 24	38144083 ps
T1026	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2675778859	Sep 24 06:50:01 AM UTC 24	Sep 24 06:50:04 AM UTC 24	331165277 ps
T1027	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.835712859	Sep 24 06:50:01 AM UTC 24	Sep 24 06:50:04 AM UTC 24	51710974 ps
T1028	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.194555333	Sep 24 06:50:02 AM UTC 24	Sep 24 06:50:04 AM UTC 24	111158725 ps
T1029	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.3164332286	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	33676953 ps
T1030	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.1390543848	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	31266326 ps
T1031	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.383957906	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	34042417 ps
T1032	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1584731361	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	42130701 ps
T1033	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3811851787	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	29660809 ps
T1034	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.887690832	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	33731741 ps
T1035	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.215448954	Sep 24 06:50:02 AM UTC 24	Sep 24 06:50:05 AM UTC 24	125971364 ps
T1036	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.1853139741	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	81961363 ps
T1037	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.3984313579	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	121139623 ps
T1038	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.68538065	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	16975683 ps
T1039	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.1030282048	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	55390575 ps
T1040	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.4054127443	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	25337704 ps
T1041	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.3515477775	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	24536295 ps
T1042	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.2226880729	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	107848749 ps
T1043	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.340853663	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	69659735 ps
T1044	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.4068522401	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	140880429 ps
T1045	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2426799180	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:05 AM UTC 24	358390655 ps
T1046	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.2675318139	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:06 AM UTC 24	31181913 ps
T1047	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.3981358492	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:06 AM UTC 24	18942300 ps
T1048	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.3216742702	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:06 AM UTC 24	23463566 ps
T1049	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.549412929	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:06 AM UTC 24	56711260 ps
T1050	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.2645114735	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:06 AM UTC 24	40094460 ps
T1051	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.2363904588	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:06 AM UTC 24	45911097 ps
T1052	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.876197544	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:06 AM UTC 24	51227681 ps
T1053	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.495338634	Sep 24 06:50:03 AM UTC 24	Sep 24 06:50:06 AM UTC 24	800994124 ps
T1054	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.1016089156	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:06 AM UTC 24	61570038 ps
T1055	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.3498782892	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:07 AM UTC 24	23020513 ps
T1056	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.3408284358	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:07 AM UTC 24	36004726 ps
T1057	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.2776224033	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:07 AM UTC 24	35879075 ps
T1058	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.3722192512	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:07 AM UTC 24	29450034 ps
T1059	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.3455939545	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:07 AM UTC 24	42498085 ps
T1060	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.753514668	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:07 AM UTC 24	33968463 ps
T1061	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.1633789824	Sep 24 06:50:05 AM UTC 24	Sep 24 06:50:07 AM UTC 24	19534376 ps
T1062	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.684646713	Sep 24 06:50:06 AM UTC 24	Sep 24 06:50:08 AM UTC 24	58551367 ps
T1063	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.3151244962	Sep 24 06:50:06 AM UTC 24	Sep 24 06:50:08 AM UTC 24	45771338 ps
T1064	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.4049551536	Sep 24 06:50:06 AM UTC 24	Sep 24 06:50:08 AM UTC 24	20823520 ps
T1065	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.474884099	Sep 24 06:50:06 AM UTC 24	Sep 24 06:50:08 AM UTC 24	21244172 ps
T1066	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.823887424	Sep 24 06:50:06 AM UTC 24	Sep 24 06:50:08 AM UTC 24	28542976 ps
T1067	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.1274655524	Sep 24 06:50:06 AM UTC 24	Sep 24 06:50:08 AM UTC 24	29615044 ps
T1068	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.3865193070	Sep 24 06:50:06 AM UTC 24	Sep 24 06:50:08 AM UTC 24	22452994 ps
T1069	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.1332002288	Sep 24 06:50:06 AM UTC 24	Sep 24 06:50:08 AM UTC 24	16928791 ps
T1070	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.595240567	Sep 24 06:50:06 AM UTC 24	Sep 24 06:50:08 AM UTC 24	19451089 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.1497865383
Short name	T4
Test name
Test status
Simulation time	311508985 ps
CPU time	1.46 seconds
Started	Sep 24 08:42:06 AM UTC 24
Finished	Sep 24 08:42:09 AM UTC 24
Peak memory	209856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497865383 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wakeup_race.1497865383
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4078235510
Short name	T14
Test name
Test status
Simulation time	997562069 ps
CPU time	3.09 seconds
Started	Sep 24 08:42:08 AM UTC 24
Finished	Sep 24 08:42:12 AM UTC 24
Peak memory	211444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078235510 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.4078235510
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.1710463727
Short name	T28
Test name
Test status
Simulation time	113633378 ps
CPU time	1.44 seconds
Started	Sep 24 08:42:09 AM UTC 24
Finished	Sep 24 08:42:12 AM UTC 24
Peak memory	220304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710463727 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.1710463727
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.1962226018
Short name	T22
Test name
Test status
Simulation time	411940059 ps
CPU time	1.78 seconds
Started	Sep 24 08:42:14 AM UTC 24
Finished	Sep 24 08:42:17 AM UTC 24
Peak memory	237576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962226018 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.1962226018
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.1034912423
Short name	T42
Test name
Test status
Simulation time	2772936689 ps
CPU time	3.11 seconds
Started	Sep 24 08:42:14 AM UTC 24
Finished	Sep 24 08:42:18 AM UTC 24
Peak memory	211692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034912423 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.1034912423
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.3907296907
Short name	T48
Test name
Test status
Simulation time	2120723370 ps
CPU time	9.54 seconds
Started	Sep 24 08:42:41 AM UTC 24
Finished	Sep 24 08:42:52 AM UTC 24
Peak memory	211620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3907296907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr _stress_all_with_rand_reset.3907296907
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2066078902
Short name	T45
Test name
Test status
Simulation time	193038582 ps
CPU time	2.52 seconds
Started	Sep 24 06:49:43 AM UTC 24
Finished	Sep 24 06:49:46 AM UTC 24
Peak memory	211108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066078902 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.2066078902
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.4232595943
Short name	T23
Test name
Test status
Simulation time	42712972 ps
CPU time	0.98 seconds
Started	Sep 24 08:42:23 AM UTC 24
Finished	Sep 24 08:42:25 AM UTC 24
Peak memory	210168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232595943 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invalid.4232595943
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_lowpower_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.2204485987
Short name	T65
Test name
Test status
Simulation time	24344051 ps
CPU time	0.95 seconds
Started	Sep 24 06:49:47 AM UTC 24
Finished	Sep 24 06:49:49 AM UTC 24
Peak memory	206960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204485987 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.2204485987
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.147074353
Short name	T58
Test name
Test status
Simulation time	19682901 ps
CPU time	1.03 seconds
Started	Sep 24 06:49:45 AM UTC 24
Finished	Sep 24 06:49:47 AM UTC 24
Peak memory	209660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147074353 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.147074353
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.657454130
Short name	T9
Test name
Test status
Simulation time	386990452 ps
CPU time	0.99 seconds
Started	Sep 24 08:42:08 AM UTC 24
Finished	Sep 24 08:42:10 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657454130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.657454130
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.2149175960
Short name	T55
Test name
Test status
Simulation time	299778317 ps
CPU time	1.89 seconds
Started	Sep 24 08:42:13 AM UTC 24
Finished	Sep 24 08:42:16 AM UTC 24
Peak memory	209740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149175960 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_ctrl_config_regwen.2149175960
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.3888677507
Short name	T26
Test name
Test status
Simulation time	4252156429 ps
CPU time	16.14 seconds
Started	Sep 24 08:42:20 AM UTC 24
Finished	Sep 24 08:42:37 AM UTC 24
Peak memory	211812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3888677507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr _stress_all_with_rand_reset.3888677507
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.1050060588
Short name	T52
Test name
Test status
Simulation time	226656151 ps
CPU time	1.91 seconds
Started	Sep 24 06:49:46 AM UTC 24
Finished	Sep 24 06:49:49 AM UTC 24
Peak memory	211184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050060588 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.1050060588
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.2664598226
Short name	T181
Test name
Test status
Simulation time	73212222 ps
CPU time	0.92 seconds
Started	Sep 24 08:42:56 AM UTC 24
Finished	Sep 24 08:42:58 AM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664598226 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disable_rom_integrity_check.2664598226
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.942200063
Short name	T16
Test name
Test status
Simulation time	2532572466 ps
CPU time	5.38 seconds
Started	Sep 24 08:42:10 AM UTC 24
Finished	Sep 24 08:42:16 AM UTC 24
Peak memory	211736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942200063 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.942200063
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.107354446
Short name	T1003
Test name
Test status
Simulation time	21223240 ps
CPU time	0.76 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:01 AM UTC 24
Peak memory	207016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107354446 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.107354446
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3590488456
Short name	T165
Test name
Test status
Simulation time	207392871 ps
CPU time	1.97 seconds
Started	Sep 24 06:49:58 AM UTC 24
Finished	Sep 24 06:50:02 AM UTC 24
Peak memory	211188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590488456 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_err.3590488456
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_disable_rom_integrity_check.4194876020
Short name	T184
Test name
Test status
Simulation time	54871984 ps
CPU time	0.8 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:49 AM UTC 24
Peak memory	209124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194876020 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disable_rom_integrity_check.4194876020
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1124062539
Short name	T70
Test name
Test status
Simulation time	203723507 ps
CPU time	1.71 seconds
Started	Sep 24 06:49:57 AM UTC 24
Finished	Sep 24 06:49:59 AM UTC 24
Peak memory	211120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124062539 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err.1124062539
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.578723557
Short name	T10
Test name
Test status
Simulation time	99643812 ps
CPU time	1.1 seconds
Started	Sep 24 08:42:08 AM UTC 24
Finished	Sep 24 08:42:10 AM UTC 24
Peak memory	209308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578723557 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_ctrl_config_regwen.578723557
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3464487931
Short name	T1005
Test name
Test status
Simulation time	140950632 ps
CPU time	2.38 seconds
Started	Sep 24 06:49:58 AM UTC 24
Finished	Sep 24 06:50:02 AM UTC 24
Peak memory	211172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464487931 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.3464487931
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.3547744628
Short name	T17
Test name
Test status
Simulation time	38698601 ps
CPU time	0.91 seconds
Started	Sep 24 08:42:09 AM UTC 24
Finished	Sep 24 08:42:11 AM UTC 24
Peak memory	208676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547744628 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.3547744628
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2180805228
Short name	T177
Test name
Test status
Simulation time	52452594 ps
CPU time	0.99 seconds
Started	Sep 24 06:49:45 AM UTC 24
Finished	Sep 24 06:49:47 AM UTC 24
Peak memory	209244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180805228 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.2180805228
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1604201474
Short name	T180
Test name
Test status
Simulation time	171929260 ps
CPU time	2.33 seconds
Started	Sep 24 06:49:45 AM UTC 24
Finished	Sep 24 06:49:48 AM UTC 24
Peak memory	210916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604201474 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.1604201474
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1870281876
Short name	T51
Test name
Test status
Simulation time	224124190 ps
CPU time	1 seconds
Started	Sep 24 06:49:45 AM UTC 24
Finished	Sep 24 06:49:47 AM UTC 24
Peak memory	208596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870281876 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.1870281876
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1165974938
Short name	T57
Test name
Test status
Simulation time	50061278 ps
CPU time	0.92 seconds
Started	Sep 24 06:49:46 AM UTC 24
Finished	Sep 24 06:49:48 AM UTC 24
Peak memory	211168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1165974938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_w ith_rand_reset.1165974938
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.1345946408
Short name	T50
Test name
Test status
Simulation time	43312102 ps
CPU time	0.93 seconds
Started	Sep 24 06:49:44 AM UTC 24
Finished	Sep 24 06:49:46 AM UTC 24
Peak memory	208252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345946408 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.1345946408
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.4215523048
Short name	T121
Test name
Test status
Simulation time	215506475 ps
CPU time	0.91 seconds
Started	Sep 24 06:49:46 AM UTC 24
Finished	Sep 24 06:49:48 AM UTC 24
Peak memory	210128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215523048 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_same_csr_outstanding.4215523048
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.1325557578
Short name	T46
Test name
Test status
Simulation time	473542226 ps
CPU time	3.32 seconds
Started	Sep 24 06:49:43 AM UTC 24
Finished	Sep 24 06:49:47 AM UTC 24
Peak memory	211128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325557578 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.1325557578
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.71125213
Short name	T960
Test name
Test status
Simulation time	60314980 ps
CPU time	0.84 seconds
Started	Sep 24 06:49:48 AM UTC 24
Finished	Sep 24 06:49:49 AM UTC 24
Peak memory	210072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71125213 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.71125213
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.170226711
Short name	T179
Test name
Test status
Simulation time	122180077 ps
CPU time	2.15 seconds
Started	Sep 24 06:49:48 AM UTC 24
Finished	Sep 24 06:49:51 AM UTC 24
Peak memory	211300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170226711 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.170226711
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3948523622
Short name	T959
Test name
Test status
Simulation time	42836942 ps
CPU time	1 seconds
Started	Sep 24 06:49:47 AM UTC 24
Finished	Sep 24 06:49:49 AM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948523622 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.3948523622
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.478906218
Short name	T962
Test name
Test status
Simulation time	82787752 ps
CPU time	1.16 seconds
Started	Sep 24 06:49:49 AM UTC 24
Finished	Sep 24 06:49:51 AM UTC 24
Peak memory	211228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=478906218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_wi th_rand_reset.478906218
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.3874215152
Short name	T178
Test name
Test status
Simulation time	23209333 ps
CPU time	0.79 seconds
Started	Sep 24 06:49:47 AM UTC 24
Finished	Sep 24 06:49:49 AM UTC 24
Peak memory	208180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874215152 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.3874215152
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3043550442
Short name	T122
Test name
Test status
Simulation time	98251621 ps
CPU time	0.98 seconds
Started	Sep 24 06:49:48 AM UTC 24
Finished	Sep 24 06:49:50 AM UTC 24
Peak memory	210128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043550442 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_same_csr_outstanding.3043550442
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3274684894
Short name	T47
Test name
Test status
Simulation time	591996485 ps
CPU time	1.81 seconds
Started	Sep 24 06:49:46 AM UTC 24
Finished	Sep 24 06:49:49 AM UTC 24
Peak memory	211120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274684894 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err.3274684894
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2492391881
Short name	T992
Test name
Test status
Simulation time	40523815 ps
CPU time	0.94 seconds
Started	Sep 24 06:49:57 AM UTC 24
Finished	Sep 24 06:49:59 AM UTC 24
Peak memory	211232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2492391881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_ with_rand_reset.2492391881
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.3030724358
Short name	T116
Test name
Test status
Simulation time	19632430 ps
CPU time	0.87 seconds
Started	Sep 24 06:49:57 AM UTC 24
Finished	Sep 24 06:49:59 AM UTC 24
Peak memory	209284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030724358 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.3030724358
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.3589536470
Short name	T988
Test name
Test status
Simulation time	31153193 ps
CPU time	0.72 seconds
Started	Sep 24 06:49:57 AM UTC 24
Finished	Sep 24 06:49:58 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589536470 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.3589536470
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1761275928
Short name	T979
Test name
Test status
Simulation time	71272481 ps
CPU time	0.97 seconds
Started	Sep 24 06:49:57 AM UTC 24
Finished	Sep 24 06:49:59 AM UTC 24
Peak memory	210124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761275928 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_same_csr_outstanding.1761275928
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.3747466034
Short name	T54
Test name
Test status
Simulation time	67918764 ps
CPU time	1.27 seconds
Started	Sep 24 06:49:57 AM UTC 24
Finished	Sep 24 06:49:59 AM UTC 24
Peak memory	211128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747466034 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.3747466034
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.3794161470
Short name	T997
Test name
Test status
Simulation time	63366953 ps
CPU time	0.92 seconds
Started	Sep 24 06:49:58 AM UTC 24
Finished	Sep 24 06:50:00 AM UTC 24
Peak memory	211232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3794161470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_ with_rand_reset.3794161470
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.1986918434
Short name	T117
Test name
Test status
Simulation time	51083035 ps
CPU time	0.81 seconds
Started	Sep 24 06:49:58 AM UTC 24
Finished	Sep 24 06:50:00 AM UTC 24
Peak memory	206956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986918434 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.1986918434
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.1437557114
Short name	T993
Test name
Test status
Simulation time	44139913 ps
CPU time	0.65 seconds
Started	Sep 24 06:49:58 AM UTC 24
Finished	Sep 24 06:50:00 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437557114 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1437557114
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3026138273
Short name	T995
Test name
Test status
Simulation time	32712320 ps
CPU time	0.9 seconds
Started	Sep 24 06:49:58 AM UTC 24
Finished	Sep 24 06:50:00 AM UTC 24
Peak memory	209620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026138273 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_same_csr_outstanding.3026138273
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.1259111192
Short name	T69
Test name
Test status
Simulation time	86668904 ps
CPU time	1.41 seconds
Started	Sep 24 06:49:57 AM UTC 24
Finished	Sep 24 06:49:59 AM UTC 24
Peak memory	211116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259111192 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.1259111192
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.999190807
Short name	T994
Test name
Test status
Simulation time	199076686 ps
CPU time	1.74 seconds
Started	Sep 24 06:49:57 AM UTC 24
Finished	Sep 24 06:50:00 AM UTC 24
Peak memory	211152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999190807 -assert nopostproc +UVM_TESTNA ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_err.999190807
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3630415163
Short name	T999
Test name
Test status
Simulation time	56529576 ps
CPU time	1.01 seconds
Started	Sep 24 06:49:58 AM UTC 24
Finished	Sep 24 06:50:00 AM UTC 24
Peak memory	211232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3630415163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_ with_rand_reset.3630415163
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.621812116
Short name	T118
Test name
Test status
Simulation time	22792763 ps
CPU time	0.82 seconds
Started	Sep 24 06:49:58 AM UTC 24
Finished	Sep 24 06:50:00 AM UTC 24
Peak memory	208768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621812116 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.621812116
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.2396367978
Short name	T996
Test name
Test status
Simulation time	17253919 ps
CPU time	0.84 seconds
Started	Sep 24 06:49:58 AM UTC 24
Finished	Sep 24 06:50:00 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396367978 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.2396367978
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.1142259982
Short name	T998
Test name
Test status
Simulation time	146945614 ps
CPU time	0.96 seconds
Started	Sep 24 06:49:58 AM UTC 24
Finished	Sep 24 06:50:00 AM UTC 24
Peak memory	209092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142259982 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_same_csr_outstanding.1142259982
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.944942927
Short name	T1000
Test name
Test status
Simulation time	412529097 ps
CPU time	1.71 seconds
Started	Sep 24 06:49:58 AM UTC 24
Finished	Sep 24 06:50:01 AM UTC 24
Peak memory	211184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944942927 -assert nopostproc +UVM_TESTNA ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err.944942927
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1756709711
Short name	T1010
Test name
Test status
Simulation time	195222837 ps
CPU time	1.07 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:02 AM UTC 24
Peak memory	209828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1756709711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_ with_rand_reset.1756709711
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.2086081642
Short name	T1004
Test name
Test status
Simulation time	40695388 ps
CPU time	0.78 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:01 AM UTC 24
Peak memory	206956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086081642 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.2086081642
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3325960095
Short name	T1007
Test name
Test status
Simulation time	46199596 ps
CPU time	0.99 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:02 AM UTC 24
Peak memory	211168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325960095 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_same_csr_outstanding.3325960095
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.2159273777
Short name	T1001
Test name
Test status
Simulation time	116228127 ps
CPU time	1.64 seconds
Started	Sep 24 06:49:58 AM UTC 24
Finished	Sep 24 06:50:01 AM UTC 24
Peak memory	211124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159273777 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.2159273777
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.3090799007
Short name	T1013
Test name
Test status
Simulation time	55367375 ps
CPU time	0.97 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:02 AM UTC 24
Peak memory	209888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3090799007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_ with_rand_reset.3090799007
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.3357347994
Short name	T1006
Test name
Test status
Simulation time	47784283 ps
CPU time	0.83 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:02 AM UTC 24
Peak memory	206956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357347994 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.3357347994
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.1580743311
Short name	T1008
Test name
Test status
Simulation time	17486347 ps
CPU time	0.87 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:02 AM UTC 24
Peak memory	207068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580743311 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.1580743311
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.423251412
Short name	T1011
Test name
Test status
Simulation time	29396792 ps
CPU time	0.96 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:02 AM UTC 24
Peak memory	209656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423251412 -assert nopostproc +U VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_same_csr_outstanding.423251412
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.3447020207
Short name	T1016
Test name
Test status
Simulation time	345921748 ps
CPU time	1.96 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:03 AM UTC 24
Peak memory	211116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447020207 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.3447020207
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3918718776
Short name	T71
Test name
Test status
Simulation time	458085727 ps
CPU time	1.57 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:02 AM UTC 24
Peak memory	211180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918718776 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err.3918718776
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3744191430
Short name	T1015
Test name
Test status
Simulation time	74516342 ps
CPU time	1.21 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:02 AM UTC 24
Peak memory	211160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3744191430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_ with_rand_reset.3744191430
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3460369543
Short name	T119
Test name
Test status
Simulation time	24276292 ps
CPU time	0.65 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:02 AM UTC 24
Peak memory	206956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460369543 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.3460369543
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.2394757375
Short name	T1009
Test name
Test status
Simulation time	59956145 ps
CPU time	0.63 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:02 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394757375 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.2394757375
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1819680644
Short name	T1012
Test name
Test status
Simulation time	33244666 ps
CPU time	0.71 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:02 AM UTC 24
Peak memory	208504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819680644 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_same_csr_outstanding.1819680644
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.1149563604
Short name	T1017
Test name
Test status
Simulation time	474039691 ps
CPU time	2.04 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:03 AM UTC 24
Peak memory	211144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149563604 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.1149563604
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2059659999
Short name	T1014
Test name
Test status
Simulation time	145838702 ps
CPU time	1.33 seconds
Started	Sep 24 06:50:00 AM UTC 24
Finished	Sep 24 06:50:02 AM UTC 24
Peak memory	211180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059659999 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_err.2059659999
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2953154210
Short name	T1023
Test name
Test status
Simulation time	75213257 ps
CPU time	1.19 seconds
Started	Sep 24 06:50:01 AM UTC 24
Finished	Sep 24 06:50:04 AM UTC 24
Peak memory	211232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2953154210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_ with_rand_reset.2953154210
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.529927363
Short name	T1021
Test name
Test status
Simulation time	18970481 ps
CPU time	1 seconds
Started	Sep 24 06:50:01 AM UTC 24
Finished	Sep 24 06:50:03 AM UTC 24
Peak memory	208440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529927363 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.529927363
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.896449944
Short name	T1018
Test name
Test status
Simulation time	53427967 ps
CPU time	0.74 seconds
Started	Sep 24 06:50:01 AM UTC 24
Finished	Sep 24 06:50:03 AM UTC 24
Peak memory	207016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896449944 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.896449944
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3490934586
Short name	T1019
Test name
Test status
Simulation time	87658301 ps
CPU time	0.85 seconds
Started	Sep 24 06:50:01 AM UTC 24
Finished	Sep 24 06:50:03 AM UTC 24
Peak memory	209944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490934586 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_same_csr_outstanding.3490934586
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.835712859
Short name	T1027
Test name
Test status
Simulation time	51710974 ps
CPU time	1.44 seconds
Started	Sep 24 06:50:01 AM UTC 24
Finished	Sep 24 06:50:04 AM UTC 24
Peak memory	211148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835712859 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.835712859
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2675778859
Short name	T1026
Test name
Test status
Simulation time	331165277 ps
CPU time	1.43 seconds
Started	Sep 24 06:50:01 AM UTC 24
Finished	Sep 24 06:50:04 AM UTC 24
Peak memory	211180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675778859 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err.2675778859
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3590518567
Short name	T1025
Test name
Test status
Simulation time	38144083 ps
CPU time	0.97 seconds
Started	Sep 24 06:50:02 AM UTC 24
Finished	Sep 24 06:50:04 AM UTC 24
Peak memory	211232 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3590518567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_ with_rand_reset.3590518567
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.2468950503
Short name	T1022
Test name
Test status
Simulation time	24175453 ps
CPU time	0.81 seconds
Started	Sep 24 06:50:02 AM UTC 24
Finished	Sep 24 06:50:04 AM UTC 24
Peak memory	208180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468950503 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.2468950503
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.580553640
Short name	T1020
Test name
Test status
Simulation time	23443128 ps
CPU time	0.69 seconds
Started	Sep 24 06:50:02 AM UTC 24
Finished	Sep 24 06:50:03 AM UTC 24
Peak memory	207016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580553640 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.580553640
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3007782875
Short name	T1024
Test name
Test status
Simulation time	50628974 ps
CPU time	1.01 seconds
Started	Sep 24 06:50:02 AM UTC 24
Finished	Sep 24 06:50:04 AM UTC 24
Peak memory	211108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007782875 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_same_csr_outstanding.3007782875
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.215448954
Short name	T1035
Test name
Test status
Simulation time	125971364 ps
CPU time	2.45 seconds
Started	Sep 24 06:50:02 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	211216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215448954 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.215448954
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.194555333
Short name	T1028
Test name
Test status
Simulation time	111158725 ps
CPU time	1.28 seconds
Started	Sep 24 06:50:02 AM UTC 24
Finished	Sep 24 06:50:04 AM UTC 24
Peak memory	211176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194555333 -assert nopostproc +UVM_TESTNA ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err.194555333
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1584731361
Short name	T1032
Test name
Test status
Simulation time	42130701 ps
CPU time	0.94 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	209828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1584731361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_ with_rand_reset.1584731361
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.3164332286
Short name	T1029
Test name
Test status
Simulation time	33676953 ps
CPU time	0.74 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	209788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164332286 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.3164332286
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.1390543848
Short name	T1030
Test name
Test status
Simulation time	31266326 ps
CPU time	0.71 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390543848 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.1390543848
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.3984313579
Short name	T1037
Test name
Test status
Simulation time	121139623 ps
CPU time	1.13 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	211168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984313579 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_same_csr_outstanding.3984313579
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.495338634
Short name	T1053
Test name
Test status
Simulation time	800994124 ps
CPU time	2.55 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:06 AM UTC 24
Peak memory	211116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495338634 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.495338634
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.4068522401
Short name	T1044
Test name
Test status
Simulation time	140880429 ps
CPU time	1.43 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	211180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068522401 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err.4068522401
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.340853663
Short name	T1043
Test name
Test status
Simulation time	69659735 ps
CPU time	1.06 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	211108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=340853663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_w ith_rand_reset.340853663
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.887690832
Short name	T1034
Test name
Test status
Simulation time	33731741 ps
CPU time	0.82 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	208180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887690832 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.887690832
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.383957906
Short name	T1031
Test name
Test status
Simulation time	34042417 ps
CPU time	0.71 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	207016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383957906 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.383957906
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3811851787
Short name	T1033
Test name
Test status
Simulation time	29660809 ps
CPU time	0.76 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	210340 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811851787 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_same_csr_outstanding.3811851787
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.2226880729
Short name	T1042
Test name
Test status
Simulation time	107848749 ps
CPU time	1.21 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	211164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226880729 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.2226880729
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2426799180
Short name	T1045
Test name
Test status
Simulation time	358390655 ps
CPU time	1.3 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	211156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426799180 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err.2426799180
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2595678358
Short name	T114
Test name
Test status
Simulation time	51616870 ps
CPU time	1.07 seconds
Started	Sep 24 06:49:49 AM UTC 24
Finished	Sep 24 06:49:51 AM UTC 24
Peak memory	210120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595678358 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.2595678358
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2384324597
Short name	T966
Test name
Test status
Simulation time	221156007 ps
CPU time	3.29 seconds
Started	Sep 24 06:49:49 AM UTC 24
Finished	Sep 24 06:49:53 AM UTC 24
Peak memory	211144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384324597 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.2384324597
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.582947703
Short name	T961
Test name
Test status
Simulation time	25269643 ps
CPU time	0.9 seconds
Started	Sep 24 06:49:49 AM UTC 24
Finished	Sep 24 06:49:51 AM UTC 24
Peak memory	208776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582947703 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.582947703
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3504061167
Short name	T60
Test name
Test status
Simulation time	116267232 ps
CPU time	1.26 seconds
Started	Sep 24 06:49:50 AM UTC 24
Finished	Sep 24 06:49:53 AM UTC 24
Peak memory	210944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3504061167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_w ith_rand_reset.3504061167
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.748580289
Short name	T113
Test name
Test status
Simulation time	68869297 ps
CPU time	0.74 seconds
Started	Sep 24 06:49:49 AM UTC 24
Finished	Sep 24 06:49:51 AM UTC 24
Peak memory	206948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748580289 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.748580289
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.2395720516
Short name	T170
Test name
Test status
Simulation time	39641217 ps
CPU time	0.75 seconds
Started	Sep 24 06:49:49 AM UTC 24
Finished	Sep 24 06:49:51 AM UTC 24
Peak memory	206960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395720516 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.2395720516
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2244263524
Short name	T123
Test name
Test status
Simulation time	123297914 ps
CPU time	1.26 seconds
Started	Sep 24 06:49:50 AM UTC 24
Finished	Sep 24 06:49:53 AM UTC 24
Peak memory	210128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244263524 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_same_csr_outstanding.2244263524
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.1603976977
Short name	T63
Test name
Test status
Simulation time	45415205 ps
CPU time	1.55 seconds
Started	Sep 24 06:49:49 AM UTC 24
Finished	Sep 24 06:49:51 AM UTC 24
Peak memory	211200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603976977 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.1603976977
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1130403006
Short name	T53
Test name
Test status
Simulation time	851928086 ps
CPU time	1.74 seconds
Started	Sep 24 06:49:49 AM UTC 24
Finished	Sep 24 06:49:52 AM UTC 24
Peak memory	211112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130403006 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.1130403006
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.1853139741
Short name	T1036
Test name
Test status
Simulation time	81961363 ps
CPU time	0.77 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853139741 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.1853139741
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.68538065
Short name	T1038
Test name
Test status
Simulation time	16975683 ps
CPU time	0.78 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68538065 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pw rmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.68538065
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.1030282048
Short name	T1039
Test name
Test status
Simulation time	55390575 ps
CPU time	0.71 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030282048 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.1030282048
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.4054127443
Short name	T1040
Test name
Test status
Simulation time	25337704 ps
CPU time	0.66 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054127443 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.4054127443
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.3515477775
Short name	T1041
Test name
Test status
Simulation time	24536295 ps
CPU time	0.88 seconds
Started	Sep 24 06:50:03 AM UTC 24
Finished	Sep 24 06:50:05 AM UTC 24
Peak memory	207068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515477775 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.3515477775
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.3981358492
Short name	T1047
Test name
Test status
Simulation time	18942300 ps
CPU time	0.66 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:06 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981358492 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.3981358492
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.2363904588
Short name	T1051
Test name
Test status
Simulation time	45911097 ps
CPU time	0.72 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:06 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363904588 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.2363904588
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.2675318139
Short name	T1046
Test name
Test status
Simulation time	31181913 ps
CPU time	0.55 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:06 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675318139 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.2675318139
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.3216742702
Short name	T1048
Test name
Test status
Simulation time	23463566 ps
CPU time	0.61 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:06 AM UTC 24
Peak memory	206448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216742702 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.3216742702
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.549412929
Short name	T1049
Test name
Test status
Simulation time	56711260 ps
CPU time	0.63 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:06 AM UTC 24
Peak memory	207016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549412929 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.549412929
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.479151344
Short name	T965
Test name
Test status
Simulation time	129657190 ps
CPU time	1.22 seconds
Started	Sep 24 06:49:51 AM UTC 24
Finished	Sep 24 06:49:53 AM UTC 24
Peak memory	209820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479151344 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.479151344
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2261992864
Short name	T968
Test name
Test status
Simulation time	900278804 ps
CPU time	2.17 seconds
Started	Sep 24 06:49:51 AM UTC 24
Finished	Sep 24 06:49:54 AM UTC 24
Peak memory	211372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261992864 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.2261992864
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3506863521
Short name	T963
Test name
Test status
Simulation time	276659279 ps
CPU time	0.88 seconds
Started	Sep 24 06:49:50 AM UTC 24
Finished	Sep 24 06:49:52 AM UTC 24
Peak memory	208380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506863521 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.3506863521
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.321766992
Short name	T964
Test name
Test status
Simulation time	138885812 ps
CPU time	0.84 seconds
Started	Sep 24 06:49:51 AM UTC 24
Finished	Sep 24 06:49:53 AM UTC 24
Peak memory	211228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=321766992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_wi th_rand_reset.321766992
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.513041513
Short name	T120
Test name
Test status
Simulation time	20855465 ps
CPU time	0.79 seconds
Started	Sep 24 06:49:50 AM UTC 24
Finished	Sep 24 06:49:52 AM UTC 24
Peak memory	209516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513041513 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.513041513
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.1990384357
Short name	T171
Test name
Test status
Simulation time	19960879 ps
CPU time	0.91 seconds
Started	Sep 24 06:49:50 AM UTC 24
Finished	Sep 24 06:49:52 AM UTC 24
Peak memory	206960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990384357 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.1990384357
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1417326557
Short name	T124
Test name
Test status
Simulation time	131102065 ps
CPU time	1.08 seconds
Started	Sep 24 06:49:51 AM UTC 24
Finished	Sep 24 06:49:53 AM UTC 24
Peak memory	209888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417326557 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_same_csr_outstanding.1417326557
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.1452367436
Short name	T68
Test name
Test status
Simulation time	41205551 ps
CPU time	1.39 seconds
Started	Sep 24 06:49:50 AM UTC 24
Finished	Sep 24 06:49:53 AM UTC 24
Peak memory	209828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452367436 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.1452367436
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3087637464
Short name	T66
Test name
Test status
Simulation time	492117944 ps
CPU time	1.31 seconds
Started	Sep 24 06:49:50 AM UTC 24
Finished	Sep 24 06:49:53 AM UTC 24
Peak memory	211120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087637464 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err.3087637464
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.876197544
Short name	T1052
Test name
Test status
Simulation time	51227681 ps
CPU time	0.73 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:06 AM UTC 24
Peak memory	207016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876197544 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.876197544
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.1016089156
Short name	T1054
Test name
Test status
Simulation time	61570038 ps
CPU time	0.65 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:06 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016089156 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.1016089156
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.2645114735
Short name	T1050
Test name
Test status
Simulation time	40094460 ps
CPU time	0.62 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:06 AM UTC 24
Peak memory	207068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645114735 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.2645114735
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.3498782892
Short name	T1055
Test name
Test status
Simulation time	23020513 ps
CPU time	0.74 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:07 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498782892 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.3498782892
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.3722192512
Short name	T1058
Test name
Test status
Simulation time	29450034 ps
CPU time	0.72 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:07 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722192512 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.3722192512
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.2776224033
Short name	T1057
Test name
Test status
Simulation time	35879075 ps
CPU time	0.73 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:07 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776224033 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.2776224033
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.3455939545
Short name	T1059
Test name
Test status
Simulation time	42498085 ps
CPU time	0.69 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:07 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455939545 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3455939545
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.3408284358
Short name	T1056
Test name
Test status
Simulation time	36004726 ps
CPU time	0.65 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:07 AM UTC 24
Peak memory	207068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408284358 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.3408284358
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.753514668
Short name	T1060
Test name
Test status
Simulation time	33968463 ps
CPU time	0.65 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:07 AM UTC 24
Peak memory	207016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753514668 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.753514668
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.1633789824
Short name	T1061
Test name
Test status
Simulation time	19534376 ps
CPU time	0.72 seconds
Started	Sep 24 06:50:05 AM UTC 24
Finished	Sep 24 06:50:07 AM UTC 24
Peak memory	207068 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633789824 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.1633789824
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2848342799
Short name	T970
Test name
Test status
Simulation time	51030523 ps
CPU time	0.91 seconds
Started	Sep 24 06:49:52 AM UTC 24
Finished	Sep 24 06:49:54 AM UTC 24
Peak memory	210012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848342799 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.2848342799
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1066335177
Short name	T974
Test name
Test status
Simulation time	736478950 ps
CPU time	2.22 seconds
Started	Sep 24 06:49:52 AM UTC 24
Finished	Sep 24 06:49:55 AM UTC 24
Peak memory	211404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066335177 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.1066335177
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3410885834
Short name	T969
Test name
Test status
Simulation time	132066127 ps
CPU time	0.94 seconds
Started	Sep 24 06:49:52 AM UTC 24
Finished	Sep 24 06:49:54 AM UTC 24
Peak memory	208440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410885834 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.3410885834
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2883522561
Short name	T971
Test name
Test status
Simulation time	35985165 ps
CPU time	1.05 seconds
Started	Sep 24 06:49:52 AM UTC 24
Finished	Sep 24 06:49:54 AM UTC 24
Peak memory	211168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2883522561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_w ith_rand_reset.2883522561
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.4282915834
Short name	T967
Test name
Test status
Simulation time	24837707 ps
CPU time	0.66 seconds
Started	Sep 24 06:49:52 AM UTC 24
Finished	Sep 24 06:49:54 AM UTC 24
Peak memory	207012 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282915834 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.4282915834
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.1066221481
Short name	T176
Test name
Test status
Simulation time	20881035 ps
CPU time	0.77 seconds
Started	Sep 24 06:49:52 AM UTC 24
Finished	Sep 24 06:49:54 AM UTC 24
Peak memory	206956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066221481 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.1066221481
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1950085286
Short name	T125
Test name
Test status
Simulation time	111626251 ps
CPU time	1.29 seconds
Started	Sep 24 06:49:52 AM UTC 24
Finished	Sep 24 06:49:54 AM UTC 24
Peak memory	210412 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950085286 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_same_csr_outstanding.1950085286
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.1451347121
Short name	T973
Test name
Test status
Simulation time	627796935 ps
CPU time	3.33 seconds
Started	Sep 24 06:49:51 AM UTC 24
Finished	Sep 24 06:49:55 AM UTC 24
Peak memory	211216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451347121 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.1451347121
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.3966745771
Short name	T166
Test name
Test status
Simulation time	155901602 ps
CPU time	1.31 seconds
Started	Sep 24 06:49:51 AM UTC 24
Finished	Sep 24 06:49:53 AM UTC 24
Peak memory	211160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966745771 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.3966745771
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.3151244962
Short name	T1063
Test name
Test status
Simulation time	45771338 ps
CPU time	0.63 seconds
Started	Sep 24 06:50:06 AM UTC 24
Finished	Sep 24 06:50:08 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151244962 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.3151244962
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.684646713
Short name	T1062
Test name
Test status
Simulation time	58551367 ps
CPU time	0.57 seconds
Started	Sep 24 06:50:06 AM UTC 24
Finished	Sep 24 06:50:08 AM UTC 24
Peak memory	207016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684646713 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.684646713
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.4049551536
Short name	T1064
Test name
Test status
Simulation time	20823520 ps
CPU time	0.68 seconds
Started	Sep 24 06:50:06 AM UTC 24
Finished	Sep 24 06:50:08 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049551536 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.4049551536
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.474884099
Short name	T1065
Test name
Test status
Simulation time	21244172 ps
CPU time	0.64 seconds
Started	Sep 24 06:50:06 AM UTC 24
Finished	Sep 24 06:50:08 AM UTC 24
Peak memory	207016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474884099 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.474884099
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.3287364384
Short name	T1002
Test name
Test status
Simulation time	49974558 ps
CPU time	0.68 seconds
Started	Sep 24 06:50:06 AM UTC 24
Finished	Sep 24 06:50:08 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287364384 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.3287364384
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.823887424
Short name	T1066
Test name
Test status
Simulation time	28542976 ps
CPU time	0.71 seconds
Started	Sep 24 06:50:06 AM UTC 24
Finished	Sep 24 06:50:08 AM UTC 24
Peak memory	207016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823887424 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.823887424
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.1274655524
Short name	T1067
Test name
Test status
Simulation time	29615044 ps
CPU time	0.71 seconds
Started	Sep 24 06:50:06 AM UTC 24
Finished	Sep 24 06:50:08 AM UTC 24
Peak memory	206912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274655524 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.1274655524
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.3865193070
Short name	T1068
Test name
Test status
Simulation time	22452994 ps
CPU time	0.7 seconds
Started	Sep 24 06:50:06 AM UTC 24
Finished	Sep 24 06:50:08 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865193070 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.3865193070
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.595240567
Short name	T1070
Test name
Test status
Simulation time	19451089 ps
CPU time	0.71 seconds
Started	Sep 24 06:50:06 AM UTC 24
Finished	Sep 24 06:50:08 AM UTC 24
Peak memory	206916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595240567 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.595240567
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.1332002288
Short name	T1069
Test name
Test status
Simulation time	16928791 ps
CPU time	0.64 seconds
Started	Sep 24 06:50:06 AM UTC 24
Finished	Sep 24 06:50:08 AM UTC 24
Peak memory	206952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332002288 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.1332002288
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.2127874997
Short name	T975
Test name
Test status
Simulation time	42784018 ps
CPU time	0.89 seconds
Started	Sep 24 06:49:53 AM UTC 24
Finished	Sep 24 06:49:55 AM UTC 24
Peak memory	211168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2127874997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_w ith_rand_reset.2127874997
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.2726440360
Short name	T972
Test name
Test status
Simulation time	21057362 ps
CPU time	0.78 seconds
Started	Sep 24 06:49:53 AM UTC 24
Finished	Sep 24 06:49:55 AM UTC 24
Peak memory	208384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726440360 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.2726440360
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.2146964634
Short name	T174
Test name
Test status
Simulation time	17038634 ps
CPU time	0.77 seconds
Started	Sep 24 06:49:52 AM UTC 24
Finished	Sep 24 06:49:54 AM UTC 24
Peak memory	206960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146964634 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.2146964634
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1287399237
Short name	T126
Test name
Test status
Simulation time	80867604 ps
CPU time	1.01 seconds
Started	Sep 24 06:49:53 AM UTC 24
Finished	Sep 24 06:49:56 AM UTC 24
Peak memory	209352 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287399237 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_same_csr_outstanding.1287399237
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.1804452201
Short name	T61
Test name
Test status
Simulation time	475056472 ps
CPU time	2.43 seconds
Started	Sep 24 06:49:52 AM UTC 24
Finished	Sep 24 06:49:56 AM UTC 24
Peak memory	211184 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804452201 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.1804452201
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.389505583
Short name	T64
Test name
Test status
Simulation time	158154705 ps
CPU time	1.32 seconds
Started	Sep 24 06:49:52 AM UTC 24
Finished	Sep 24 06:49:55 AM UTC 24
Peak memory	210708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389505583 -assert nopostproc +UVM_TESTNA ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err.389505583
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1056939976
Short name	T62
Test name
Test status
Simulation time	51577602 ps
CPU time	1.52 seconds
Started	Sep 24 06:49:54 AM UTC 24
Finished	Sep 24 06:49:56 AM UTC 24
Peak memory	211128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1056939976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_w ith_rand_reset.1056939976
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.767325933
Short name	T978
Test name
Test status
Simulation time	58645670 ps
CPU time	0.99 seconds
Started	Sep 24 06:49:54 AM UTC 24
Finished	Sep 24 06:49:56 AM UTC 24
Peak memory	208532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767325933 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.767325933
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.366754439
Short name	T175
Test name
Test status
Simulation time	18969007 ps
CPU time	0.9 seconds
Started	Sep 24 06:49:54 AM UTC 24
Finished	Sep 24 06:49:56 AM UTC 24
Peak memory	206796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366754439 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.366754439
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2195408732
Short name	T127
Test name
Test status
Simulation time	580827423 ps
CPU time	1.12 seconds
Started	Sep 24 06:49:54 AM UTC 24
Finished	Sep 24 06:49:56 AM UTC 24
Peak memory	209888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195408732 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_same_csr_outstanding.2195408732
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.2859765842
Short name	T980
Test name
Test status
Simulation time	76362962 ps
CPU time	2.16 seconds
Started	Sep 24 06:49:54 AM UTC 24
Finished	Sep 24 06:49:57 AM UTC 24
Peak memory	211456 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859765842 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.2859765842
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1996235232
Short name	T167
Test name
Test status
Simulation time	355450912 ps
CPU time	1.6 seconds
Started	Sep 24 06:49:54 AM UTC 24
Finished	Sep 24 06:49:56 AM UTC 24
Peak memory	209876 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996235232 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err.1996235232
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.267254628
Short name	T982
Test name
Test status
Simulation time	52232730 ps
CPU time	1.05 seconds
Started	Sep 24 06:49:55 AM UTC 24
Finished	Sep 24 06:49:57 AM UTC 24
Peak memory	209824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=267254628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_wi th_rand_reset.267254628
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.751429809
Short name	T976
Test name
Test status
Simulation time	19631701 ps
CPU time	0.67 seconds
Started	Sep 24 06:49:54 AM UTC 24
Finished	Sep 24 06:49:56 AM UTC 24
Peak memory	208496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751429809 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.751429809
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.4105444103
Short name	T977
Test name
Test status
Simulation time	97353493 ps
CPU time	0.74 seconds
Started	Sep 24 06:49:54 AM UTC 24
Finished	Sep 24 06:49:56 AM UTC 24
Peak memory	206960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105444103 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.4105444103
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1840447812
Short name	T981
Test name
Test status
Simulation time	28852459 ps
CPU time	0.97 seconds
Started	Sep 24 06:49:55 AM UTC 24
Finished	Sep 24 06:49:57 AM UTC 24
Peak memory	210380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840447812 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_same_csr_outstanding.1840447812
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.3012442526
Short name	T986
Test name
Test status
Simulation time	271365630 ps
CPU time	2.89 seconds
Started	Sep 24 06:49:54 AM UTC 24
Finished	Sep 24 06:49:58 AM UTC 24
Peak memory	211376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012442526 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.3012442526
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2417026789
Short name	T168
Test name
Test status
Simulation time	280249165 ps
CPU time	1.64 seconds
Started	Sep 24 06:49:54 AM UTC 24
Finished	Sep 24 06:49:56 AM UTC 24
Peak memory	211120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417026789 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.2417026789
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.4283544386
Short name	T984
Test name
Test status
Simulation time	120183649 ps
CPU time	1.03 seconds
Started	Sep 24 06:49:55 AM UTC 24
Finished	Sep 24 06:49:57 AM UTC 24
Peak memory	211168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4283544386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_w ith_rand_reset.4283544386
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.2536751976
Short name	T983
Test name
Test status
Simulation time	17847833 ps
CPU time	0.87 seconds
Started	Sep 24 06:49:55 AM UTC 24
Finished	Sep 24 06:49:57 AM UTC 24
Peak memory	209128 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536751976 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.2536751976
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.394543835
Short name	T172
Test name
Test status
Simulation time	30373167 ps
CPU time	0.87 seconds
Started	Sep 24 06:49:55 AM UTC 24
Finished	Sep 24 06:49:57 AM UTC 24
Peak memory	207016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394543835 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.394543835
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2901546314
Short name	T985
Test name
Test status
Simulation time	75660481 ps
CPU time	1.16 seconds
Started	Sep 24 06:49:55 AM UTC 24
Finished	Sep 24 06:49:57 AM UTC 24
Peak memory	209888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901546314 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_same_csr_outstanding.2901546314
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.116333318
Short name	T987
Test name
Test status
Simulation time	42324487 ps
CPU time	2.16 seconds
Started	Sep 24 06:49:55 AM UTC 24
Finished	Sep 24 06:49:58 AM UTC 24
Peak memory	211180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116333318 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.116333318
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.827029778
Short name	T67
Test name
Test status
Simulation time	177727837 ps
CPU time	1.65 seconds
Started	Sep 24 06:49:55 AM UTC 24
Finished	Sep 24 06:49:58 AM UTC 24
Peak memory	211116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827029778 -assert nopostproc +UVM_TESTNA ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.827029778
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.4261409062
Short name	T991
Test name
Test status
Simulation time	112661353 ps
CPU time	0.89 seconds
Started	Sep 24 06:49:57 AM UTC 24
Finished	Sep 24 06:49:59 AM UTC 24
Peak memory	211168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4261409062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_w ith_rand_reset.4261409062
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.749512847
Short name	T115
Test name
Test status
Simulation time	29610000 ps
CPU time	0.84 seconds
Started	Sep 24 06:49:57 AM UTC 24
Finished	Sep 24 06:49:58 AM UTC 24
Peak memory	206948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749512847 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.749512847
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.414384592
Short name	T173
Test name
Test status
Simulation time	119728108 ps
CPU time	0.82 seconds
Started	Sep 24 06:49:56 AM UTC 24
Finished	Sep 24 06:49:58 AM UTC 24
Peak memory	207016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414384592 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.414384592
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.416776958
Short name	T989
Test name
Test status
Simulation time	19106417 ps
CPU time	0.97 seconds
Started	Sep 24 06:49:57 AM UTC 24
Finished	Sep 24 06:49:59 AM UTC 24
Peak memory	210040 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416776958 -assert nopostproc +U VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_same_csr_outstanding.416776958
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.109312025
Short name	T990
Test name
Test status
Simulation time	143060085 ps
CPU time	2.12 seconds
Started	Sep 24 06:49:55 AM UTC 24
Finished	Sep 24 06:49:59 AM UTC 24
Peak memory	211132 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109312025 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.109312025
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.209732658
Short name	T169
Test name
Test status
Simulation time	232757066 ps
CPU time	1.68 seconds
Started	Sep 24 06:49:55 AM UTC 24
Finished	Sep 24 06:49:58 AM UTC 24
Peak memory	211244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209732658 -assert nopostproc +UVM_TESTNA ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.209732658
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.740763945
Short name	T8
Test name
Test status
Simulation time	146928901 ps
CPU time	1.24 seconds
Started	Sep 24 08:42:08 AM UTC 24
Finished	Sep 24 08:42:10 AM UTC 24
Peak memory	210304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740763945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.740763945
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.1560531360
Short name	T12
Test name
Test status
Simulation time	67788124 ps
CPU time	1.25 seconds
Started	Sep 24 08:42:09 AM UTC 24
Finished	Sep 24 08:42:12 AM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560531360 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disable_rom_integrity_check.1560531360
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.990823540
Short name	T6
Test name
Test status
Simulation time	46517851 ps
CPU time	0.77 seconds
Started	Sep 24 08:42:08 AM UTC 24
Finished	Sep 24 08:42:10 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990823540 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_malfunc.990823540
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.1095056009
Short name	T7
Test name
Test status
Simulation time	48561657 ps
CPU time	0.9 seconds
Started	Sep 24 08:42:08 AM UTC 24
Finished	Sep 24 08:42:10 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095056009 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.1095056009
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.3813020338
Short name	T3
Test name
Test status
Simulation time	59765840 ps
CPU time	1.33 seconds
Started	Sep 24 08:42:06 AM UTC 24
Finished	Sep 24 08:42:09 AM UTC 24
Peak memory	210356 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813020338 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.3813020338
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.1821737157
Short name	T20
Test name
Test status
Simulation time	339784653 ps
CPU time	2.28 seconds
Started	Sep 24 08:42:10 AM UTC 24
Finished	Sep 24 08:42:13 AM UTC 24
Peak memory	239316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821737157 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.1821737157
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3293096801
Short name	T37
Test name
Test status
Simulation time	820112486 ps
CPU time	3.58 seconds
Started	Sep 24 08:42:08 AM UTC 24
Finished	Sep 24 08:42:12 AM UTC 24
Peak memory	211640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293096801 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.3293096801
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3225421831
Short name	T13
Test name
Test status
Simulation time	53909716 ps
CPU time	1.42 seconds
Started	Sep 24 08:42:08 AM UTC 24
Finished	Sep 24 08:42:10 AM UTC 24
Peak memory	209476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225421831 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3225421831
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.3626760041
Short name	T1
Test name
Test status
Simulation time	30792867 ps
CPU time	1.05 seconds
Started	Sep 24 08:42:06 AM UTC 24
Finished	Sep 24 08:42:08 AM UTC 24
Peak memory	208848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626760041 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.3626760041
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.2405089529
Short name	T25
Test name
Test status
Simulation time	5115822706 ps
CPU time	19.56 seconds
Started	Sep 24 08:42:10 AM UTC 24
Finished	Sep 24 08:42:31 AM UTC 24
Peak memory	211628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2405089529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr _stress_all_with_rand_reset.2405089529
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.2746572987
Short name	T5
Test name
Test status
Simulation time	281197322 ps
CPU time	1.36 seconds
Started	Sep 24 08:42:07 AM UTC 24
Finished	Sep 24 08:42:09 AM UTC 24
Peak memory	209528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746572987 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.2746572987
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.522208656
Short name	T2
Test name
Test status
Simulation time	103096451 ps
CPU time	1.12 seconds
Started	Sep 24 08:42:07 AM UTC 24
Finished	Sep 24 08:42:09 AM UTC 24
Peak memory	208620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522208656 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.522208656
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.4249290078
Short name	T15
Test name
Test status
Simulation time	70586096 ps
CPU time	1.05 seconds
Started	Sep 24 08:42:11 AM UTC 24
Finished	Sep 24 08:42:13 AM UTC 24
Peak memory	208680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249290078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.4249290078
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.1405935851
Short name	T27
Test name
Test status
Simulation time	66885745 ps
CPU time	1.02 seconds
Started	Sep 24 08:42:13 AM UTC 24
Finished	Sep 24 08:42:15 AM UTC 24
Peak memory	208688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405935851 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disable_rom_integrity_check.1405935851
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.261342606
Short name	T11
Test name
Test status
Simulation time	39682826 ps
CPU time	0.7 seconds
Started	Sep 24 08:42:13 AM UTC 24
Finished	Sep 24 08:42:14 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261342606 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_malfunc.261342606
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.3148147950
Short name	T40
Test name
Test status
Simulation time	115980010 ps
CPU time	1.27 seconds
Started	Sep 24 08:42:13 AM UTC 24
Finished	Sep 24 08:42:15 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148147950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.3148147950
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.2892628349
Short name	T18
Test name
Test status
Simulation time	67060743 ps
CPU time	0.96 seconds
Started	Sep 24 08:42:13 AM UTC 24
Finished	Sep 24 08:42:15 AM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892628349 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.2892628349
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.162505980
Short name	T35
Test name
Test status
Simulation time	97927891 ps
CPU time	0.87 seconds
Started	Sep 24 08:42:13 AM UTC 24
Finished	Sep 24 08:42:15 AM UTC 24
Peak memory	208860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162505980 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.162505980
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.665753455
Short name	T59
Test name
Test status
Simulation time	283157727 ps
CPU time	1.31 seconds
Started	Sep 24 08:42:10 AM UTC 24
Finished	Sep 24 08:42:12 AM UTC 24
Peak memory	209740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665753455 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wakeup_race.665753455
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.3420113263
Short name	T36
Test name
Test status
Simulation time	223784425 ps
CPU time	1.27 seconds
Started	Sep 24 08:42:10 AM UTC 24
Finished	Sep 24 08:42:12 AM UTC 24
Peak memory	208376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420113263 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.3420113263
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.1521002657
Short name	T38
Test name
Test status
Simulation time	218718532 ps
CPU time	1.21 seconds
Started	Sep 24 08:42:13 AM UTC 24
Finished	Sep 24 08:42:15 AM UTC 24
Peak memory	220304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521002657 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.1521002657
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3835763251
Short name	T39
Test name
Test status
Simulation time	1429322945 ps
CPU time	3.29 seconds
Started	Sep 24 08:42:11 AM UTC 24
Finished	Sep 24 08:42:16 AM UTC 24
Peak memory	211576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835763251 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.3835763251
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3133651442
Short name	T73
Test name
Test status
Simulation time	879152153 ps
CPU time	3.42 seconds
Started	Sep 24 08:42:11 AM UTC 24
Finished	Sep 24 08:42:16 AM UTC 24
Peak memory	211500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133651442 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.3133651442
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2097865720
Short name	T32
Test name
Test status
Simulation time	147232357 ps
CPU time	1.08 seconds
Started	Sep 24 08:42:11 AM UTC 24
Finished	Sep 24 08:42:13 AM UTC 24
Peak memory	209476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097865720 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2097865720
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.2531612276
Short name	T41
Test name
Test status
Simulation time	54390852 ps
CPU time	0.92 seconds
Started	Sep 24 08:42:10 AM UTC 24
Finished	Sep 24 08:42:12 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531612276 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.2531612276
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.1323049912
Short name	T24
Test name
Test status
Simulation time	7185412992 ps
CPU time	11.97 seconds
Started	Sep 24 08:42:14 AM UTC 24
Finished	Sep 24 08:42:27 AM UTC 24
Peak memory	211660 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1323049912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr _stress_all_with_rand_reset.1323049912
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.2151816749
Short name	T31
Test name
Test status
Simulation time	281842476 ps
CPU time	1.22 seconds
Started	Sep 24 08:42:11 AM UTC 24
Finished	Sep 24 08:42:13 AM UTC 24
Peak memory	210092 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151816749 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.2151816749
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.3048143073
Short name	T33
Test name
Test status
Simulation time	121105208 ps
CPU time	1.34 seconds
Started	Sep 24 08:42:11 AM UTC 24
Finished	Sep 24 08:42:13 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048143073 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.3048143073
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.3405946722
Short name	T278
Test name
Test status
Simulation time	70969330 ps
CPU time	0.94 seconds
Started	Sep 24 08:42:59 AM UTC 24
Finished	Sep 24 08:43:01 AM UTC 24
Peak memory	208744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405946722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.3405946722
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.2884353158
Short name	T189
Test name
Test status
Simulation time	73595802 ps
CPU time	1.03 seconds
Started	Sep 24 08:43:00 AM UTC 24
Finished	Sep 24 08:43:02 AM UTC 24
Peak memory	208620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884353158 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disable_rom_integrity_check.2884353158
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1695932098
Short name	T280
Test name
Test status
Simulation time	36220174 ps
CPU time	0.82 seconds
Started	Sep 24 08:42:59 AM UTC 24
Finished	Sep 24 08:43:01 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695932098 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_malfunc.1695932098
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.1490814317
Short name	T285
Test name
Test status
Simulation time	394706070 ps
CPU time	1.07 seconds
Started	Sep 24 08:43:00 AM UTC 24
Finished	Sep 24 08:43:02 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490814317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.1490814317
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.2711772430
Short name	T279
Test name
Test status
Simulation time	40061197 ps
CPU time	0.75 seconds
Started	Sep 24 08:43:00 AM UTC 24
Finished	Sep 24 08:43:01 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711772430 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.2711772430
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.1787149264
Short name	T281
Test name
Test status
Simulation time	47925338 ps
CPU time	0.85 seconds
Started	Sep 24 08:43:00 AM UTC 24
Finished	Sep 24 08:43:01 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787149264 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.1787149264
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.3167968986
Short name	T275
Test name
Test status
Simulation time	90314285 ps
CPU time	0.88 seconds
Started	Sep 24 08:42:59 AM UTC 24
Finished	Sep 24 08:43:01 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167968986 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wakeup_race.3167968986
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.3425126439
Short name	T273
Test name
Test status
Simulation time	86269264 ps
CPU time	0.84 seconds
Started	Sep 24 08:42:59 AM UTC 24
Finished	Sep 24 08:43:01 AM UTC 24
Peak memory	208740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425126439 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.3425126439
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.3095672774
Short name	T283
Test name
Test status
Simulation time	134657753 ps
CPU time	0.93 seconds
Started	Sep 24 08:43:00 AM UTC 24
Finished	Sep 24 08:43:02 AM UTC 24
Peak memory	220364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095672774 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.3095672774
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.1799891156
Short name	T282
Test name
Test status
Simulation time	183628153 ps
CPU time	1.04 seconds
Started	Sep 24 08:42:59 AM UTC 24
Finished	Sep 24 08:43:02 AM UTC 24
Peak memory	209736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799891156 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_ctrl_config_regwen.1799891156
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.575020285
Short name	T289
Test name
Test status
Simulation time	844343785 ps
CPU time	3.35 seconds
Started	Sep 24 08:42:59 AM UTC 24
Finished	Sep 24 08:43:04 AM UTC 24
Peak memory	211456 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575020285 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.575020285
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2910786958
Short name	T287
Test name
Test status
Simulation time	1293472944 ps
CPU time	2.79 seconds
Started	Sep 24 08:42:59 AM UTC 24
Finished	Sep 24 08:43:03 AM UTC 24
Peak memory	211720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910786958 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2910786958
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.4281619327
Short name	T284
Test name
Test status
Simulation time	171061218 ps
CPU time	1.22 seconds
Started	Sep 24 08:42:59 AM UTC 24
Finished	Sep 24 08:43:02 AM UTC 24
Peak memory	209148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281619327 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig_mubi.4281619327
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.2197612371
Short name	T271
Test name
Test status
Simulation time	42985028 ps
CPU time	0.74 seconds
Started	Sep 24 08:42:59 AM UTC 24
Finished	Sep 24 08:43:01 AM UTC 24
Peak memory	208680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197612371 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.2197612371
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.455616511
Short name	T290
Test name
Test status
Simulation time	961271527 ps
CPU time	2.32 seconds
Started	Sep 24 08:43:01 AM UTC 24
Finished	Sep 24 08:43:04 AM UTC 24
Peak memory	211384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455616511 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.455616511
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.3118808334
Short name	T94
Test name
Test status
Simulation time	5883937933 ps
CPU time	9.64 seconds
Started	Sep 24 08:43:01 AM UTC 24
Finished	Sep 24 08:43:12 AM UTC 24
Peak memory	211628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3118808334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmg r_stress_all_with_rand_reset.3118808334
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.4258830181
Short name	T276
Test name
Test status
Simulation time	51052963 ps
CPU time	1.01 seconds
Started	Sep 24 08:42:59 AM UTC 24
Finished	Sep 24 08:43:01 AM UTC 24
Peak memory	209036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258830181 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.4258830181
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.847727916
Short name	T286
Test name
Test status
Simulation time	593177092 ps
CPU time	1.56 seconds
Started	Sep 24 08:42:59 AM UTC 24
Finished	Sep 24 08:43:02 AM UTC 24
Peak memory	210408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847727916 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.847727916
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/10.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.1130294970
Short name	T298
Test name
Test status
Simulation time	45858092 ps
CPU time	1.08 seconds
Started	Sep 24 08:43:05 AM UTC 24
Finished	Sep 24 08:43:07 AM UTC 24
Peak memory	210172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130294970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.1130294970
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.2578032144
Short name	T191
Test name
Test status
Simulation time	68034703 ps
CPU time	1.1 seconds
Started	Sep 24 08:43:05 AM UTC 24
Finished	Sep 24 08:43:07 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578032144 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disable_rom_integrity_check.2578032144
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.271659298
Short name	T297
Test name
Test status
Simulation time	34694280 ps
CPU time	0.89 seconds
Started	Sep 24 08:43:05 AM UTC 24
Finished	Sep 24 08:43:07 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271659298 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_malfunc.271659298
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.1229929473
Short name	T301
Test name
Test status
Simulation time	422308915 ps
CPU time	0.84 seconds
Started	Sep 24 08:43:05 AM UTC 24
Finished	Sep 24 08:43:07 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229929473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.1229929473
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.848757558
Short name	T294
Test name
Test status
Simulation time	115041358 ps
CPU time	0.67 seconds
Started	Sep 24 08:43:05 AM UTC 24
Finished	Sep 24 08:43:07 AM UTC 24
Peak memory	208740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848757558 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.848757558
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.2163713935
Short name	T295
Test name
Test status
Simulation time	59978536 ps
CPU time	0.81 seconds
Started	Sep 24 08:43:05 AM UTC 24
Finished	Sep 24 08:43:07 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163713935 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.2163713935
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.2074829982
Short name	T293
Test name
Test status
Simulation time	356499732 ps
CPU time	1.09 seconds
Started	Sep 24 08:43:04 AM UTC 24
Finished	Sep 24 08:43:07 AM UTC 24
Peak memory	210104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074829982 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_wakeup_race.2074829982
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.551207238
Short name	T292
Test name
Test status
Simulation time	67664991 ps
CPU time	0.99 seconds
Started	Sep 24 08:43:04 AM UTC 24
Finished	Sep 24 08:43:07 AM UTC 24
Peak memory	210032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551207238 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.551207238
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.2970026875
Short name	T303
Test name
Test status
Simulation time	104418705 ps
CPU time	1.2 seconds
Started	Sep 24 08:43:05 AM UTC 24
Finished	Sep 24 08:43:08 AM UTC 24
Peak memory	220364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970026875 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.2970026875
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.2541552662
Short name	T300
Test name
Test status
Simulation time	265357815 ps
CPU time	0.96 seconds
Started	Sep 24 08:43:05 AM UTC 24
Finished	Sep 24 08:43:07 AM UTC 24
Peak memory	210120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541552662 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_ctrl_config_regwen.2541552662
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3079842582
Short name	T296
Test name
Test status
Simulation time	842415885 ps
CPU time	3.71 seconds
Started	Sep 24 08:43:05 AM UTC 24
Finished	Sep 24 08:43:10 AM UTC 24
Peak memory	211444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079842582 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3079842582
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1198201224
Short name	T306
Test name
Test status
Simulation time	1153872883 ps
CPU time	2.61 seconds
Started	Sep 24 08:43:05 AM UTC 24
Finished	Sep 24 08:43:09 AM UTC 24
Peak memory	211640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198201224 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1198201224
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.1141969346
Short name	T299
Test name
Test status
Simulation time	276864160 ps
CPU time	1.09 seconds
Started	Sep 24 08:43:05 AM UTC 24
Finished	Sep 24 08:43:07 AM UTC 24
Peak memory	209212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141969346 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_mubi.1141969346
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.492425681
Short name	T288
Test name
Test status
Simulation time	29798130 ps
CPU time	0.73 seconds
Started	Sep 24 08:43:01 AM UTC 24
Finished	Sep 24 08:43:03 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492425681 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.492425681
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.2708338077
Short name	T111
Test name
Test status
Simulation time	1064085629 ps
CPU time	4.8 seconds
Started	Sep 24 08:43:08 AM UTC 24
Finished	Sep 24 08:43:14 AM UTC 24
Peak memory	211488 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708338077 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.2708338077
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.211307230
Short name	T143
Test name
Test status
Simulation time	5965902654 ps
CPU time	6.97 seconds
Started	Sep 24 08:43:05 AM UTC 24
Finished	Sep 24 08:43:14 AM UTC 24
Peak memory	211696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=211307230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr _stress_all_with_rand_reset.211307230
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.1672678279
Short name	T304
Test name
Test status
Simulation time	316392771 ps
CPU time	1.83 seconds
Started	Sep 24 08:43:05 AM UTC 24
Finished	Sep 24 08:43:08 AM UTC 24
Peak memory	210096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672678279 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.1672678279
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.2433901732
Short name	T305
Test name
Test status
Simulation time	334480797 ps
CPU time	2.2 seconds
Started	Sep 24 08:43:05 AM UTC 24
Finished	Sep 24 08:43:08 AM UTC 24
Peak memory	211292 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433901732 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.2433901732
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/11.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.1147696884
Short name	T307
Test name
Test status
Simulation time	56276135 ps
CPU time	1.01 seconds
Started	Sep 24 08:43:08 AM UTC 24
Finished	Sep 24 08:43:10 AM UTC 24
Peak memory	210628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147696884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.1147696884
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.2488503033
Short name	T319
Test name
Test status
Simulation time	61592808 ps
CPU time	1.23 seconds
Started	Sep 24 08:43:12 AM UTC 24
Finished	Sep 24 08:43:14 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488503033 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disable_rom_integrity_check.2488503033
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1760065002
Short name	T311
Test name
Test status
Simulation time	29517347 ps
CPU time	0.91 seconds
Started	Sep 24 08:43:11 AM UTC 24
Finished	Sep 24 08:43:14 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760065002 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst_malfunc.1760065002
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.1545958134
Short name	T314
Test name
Test status
Simulation time	114135553 ps
CPU time	1.08 seconds
Started	Sep 24 08:43:11 AM UTC 24
Finished	Sep 24 08:43:14 AM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545958134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.1545958134
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.3509139138
Short name	T277
Test name
Test status
Simulation time	48904378 ps
CPU time	0.71 seconds
Started	Sep 24 08:43:11 AM UTC 24
Finished	Sep 24 08:43:14 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509139138 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.3509139138
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.3805479469
Short name	T302
Test name
Test status
Simulation time	76358375 ps
CPU time	0.83 seconds
Started	Sep 24 08:43:11 AM UTC 24
Finished	Sep 24 08:43:14 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805479469 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.3805479469
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.2085063742
Short name	T308
Test name
Test status
Simulation time	284714980 ps
CPU time	1.41 seconds
Started	Sep 24 08:43:08 AM UTC 24
Finished	Sep 24 08:43:10 AM UTC 24
Peak memory	209740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085063742 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_wakeup_race.2085063742
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.1382102655
Short name	T85
Test name
Test status
Simulation time	151175658 ps
CPU time	1.01 seconds
Started	Sep 24 08:43:08 AM UTC 24
Finished	Sep 24 08:43:10 AM UTC 24
Peak memory	209664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382102655 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.1382102655
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.1150368984
Short name	T316
Test name
Test status
Simulation time	298742777 ps
CPU time	1.11 seconds
Started	Sep 24 08:43:12 AM UTC 24
Finished	Sep 24 08:43:14 AM UTC 24
Peak memory	220664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150368984 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.1150368984
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.1191931575
Short name	T312
Test name
Test status
Simulation time	87284004 ps
CPU time	0.8 seconds
Started	Sep 24 08:43:11 AM UTC 24
Finished	Sep 24 08:43:14 AM UTC 24
Peak memory	209112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191931575 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_ctrl_config_regwen.1191931575
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2387484484
Short name	T309
Test name
Test status
Simulation time	824622997 ps
CPU time	2.8 seconds
Started	Sep 24 08:43:08 AM UTC 24
Finished	Sep 24 08:43:12 AM UTC 24
Peak memory	211516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387484484 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2387484484
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3819276702
Short name	T325
Test name
Test status
Simulation time	905642582 ps
CPU time	2.87 seconds
Started	Sep 24 08:43:11 AM UTC 24
Finished	Sep 24 08:43:16 AM UTC 24
Peak memory	211432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819276702 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3819276702
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3944640501
Short name	T310
Test name
Test status
Simulation time	146617306 ps
CPU time	0.95 seconds
Started	Sep 24 08:43:11 AM UTC 24
Finished	Sep 24 08:43:13 AM UTC 24
Peak memory	209772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944640501 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3944640501
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.3747824479
Short name	T272
Test name
Test status
Simulation time	59113878 ps
CPU time	0.76 seconds
Started	Sep 24 08:43:08 AM UTC 24
Finished	Sep 24 08:43:10 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747824479 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.3747824479
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all.4027771549
Short name	T323
Test name
Test status
Simulation time	1939660785 ps
CPU time	2.32 seconds
Started	Sep 24 08:43:12 AM UTC 24
Finished	Sep 24 08:43:15 AM UTC 24
Peak memory	211536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027771549 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.4027771549
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all_with_rand_reset.3100888561
Short name	T144
Test name
Test status
Simulation time	5596030382 ps
CPU time	15.79 seconds
Started	Sep 24 08:43:12 AM UTC 24
Finished	Sep 24 08:43:29 AM UTC 24
Peak memory	211684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3100888561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmg r_stress_all_with_rand_reset.3100888561
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.843160333
Short name	T274
Test name
Test status
Simulation time	488831847 ps
CPU time	1.28 seconds
Started	Sep 24 08:43:08 AM UTC 24
Finished	Sep 24 08:43:10 AM UTC 24
Peak memory	209528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843160333 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.843160333
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.202860696
Short name	T269
Test name
Test status
Simulation time	132241759 ps
CPU time	1.16 seconds
Started	Sep 24 08:43:08 AM UTC 24
Finished	Sep 24 08:43:10 AM UTC 24
Peak memory	208380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202860696 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.202860696
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/12.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.2562060551
Short name	T318
Test name
Test status
Simulation time	34424954 ps
CPU time	0.9 seconds
Started	Sep 24 08:43:12 AM UTC 24
Finished	Sep 24 08:43:14 AM UTC 24
Peak memory	208972 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562060551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.2562060551
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_disable_rom_integrity_check.37395475
Short name	T339
Test name
Test status
Simulation time	60569526 ps
CPU time	1.02 seconds
Started	Sep 24 08:43:18 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	209636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37395475 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disable_rom_integrity_check.37395475
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.123847231
Short name	T324
Test name
Test status
Simulation time	30212624 ps
CPU time	0.74 seconds
Started	Sep 24 08:43:14 AM UTC 24
Finished	Sep 24 08:43:15 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123847231 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_malfunc.123847231
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.770606783
Short name	T330
Test name
Test status
Simulation time	115507333 ps
CPU time	1.05 seconds
Started	Sep 24 08:43:14 AM UTC 24
Finished	Sep 24 08:43:16 AM UTC 24
Peak memory	208444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770606783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.770606783
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.2902265168
Short name	T335
Test name
Test status
Simulation time	60812091 ps
CPU time	0.94 seconds
Started	Sep 24 08:43:18 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	208604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902265168 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.2902265168
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_global_esc.3016813324
Short name	T327
Test name
Test status
Simulation time	78681588 ps
CPU time	0.8 seconds
Started	Sep 24 08:43:14 AM UTC 24
Finished	Sep 24 08:43:16 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016813324 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.3016813324
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.1611326219
Short name	T317
Test name
Test status
Simulation time	155698783 ps
CPU time	1.05 seconds
Started	Sep 24 08:43:12 AM UTC 24
Finished	Sep 24 08:43:14 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611326219 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_wakeup_race.1611326219
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.1704430615
Short name	T315
Test name
Test status
Simulation time	51705322 ps
CPU time	1.12 seconds
Started	Sep 24 08:43:12 AM UTC 24
Finished	Sep 24 08:43:14 AM UTC 24
Peak memory	208380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704430615 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.1704430615
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset_invalid.2773078146
Short name	T333
Test name
Test status
Simulation time	161890506 ps
CPU time	0.83 seconds
Started	Sep 24 08:43:18 AM UTC 24
Finished	Sep 24 08:43:20 AM UTC 24
Peak memory	220724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773078146 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.2773078146
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.2250360082
Short name	T329
Test name
Test status
Simulation time	414692473 ps
CPU time	1.07 seconds
Started	Sep 24 08:43:14 AM UTC 24
Finished	Sep 24 08:43:16 AM UTC 24
Peak memory	210000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250360082 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_ctrl_config_regwen.2250360082
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3063924678
Short name	T328
Test name
Test status
Simulation time	1261449708 ps
CPU time	2.42 seconds
Started	Sep 24 08:43:12 AM UTC 24
Finished	Sep 24 08:43:16 AM UTC 24
Peak memory	211428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063924678 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3063924678
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3602286786
Short name	T331
Test name
Test status
Simulation time	958330178 ps
CPU time	2.79 seconds
Started	Sep 24 08:43:12 AM UTC 24
Finished	Sep 24 08:43:16 AM UTC 24
Peak memory	211448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602286786 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3602286786
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.3628385321
Short name	T326
Test name
Test status
Simulation time	171314739 ps
CPU time	0.95 seconds
Started	Sep 24 08:43:14 AM UTC 24
Finished	Sep 24 08:43:16 AM UTC 24
Peak memory	209148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628385321 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_mubi.3628385321
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.408369307
Short name	T266
Test name
Test status
Simulation time	31871883 ps
CPU time	0.91 seconds
Started	Sep 24 08:43:12 AM UTC 24
Finished	Sep 24 08:43:14 AM UTC 24
Peak memory	208316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408369307 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.408369307
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all.879301684
Short name	T355
Test name
Test status
Simulation time	352064571 ps
CPU time	2.01 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:22 AM UTC 24
Peak memory	211360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879301684 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.879301684
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.2655619642
Short name	T360
Test name
Test status
Simulation time	2593591262 ps
CPU time	4.06 seconds
Started	Sep 24 08:43:18 AM UTC 24
Finished	Sep 24 08:43:24 AM UTC 24
Peak memory	211760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2655619642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmg r_stress_all_with_rand_reset.2655619642
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.4072689092
Short name	T321
Test name
Test status
Simulation time	218328939 ps
CPU time	1.57 seconds
Started	Sep 24 08:43:12 AM UTC 24
Finished	Sep 24 08:43:15 AM UTC 24
Peak memory	210152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072689092 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.4072689092
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.1724753537
Short name	T320
Test name
Test status
Simulation time	435561880 ps
CPU time	1.19 seconds
Started	Sep 24 08:43:12 AM UTC 24
Finished	Sep 24 08:43:14 AM UTC 24
Peak memory	210648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724753537 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.1724753537
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/13.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.3856869014
Short name	T349
Test name
Test status
Simulation time	146838998 ps
CPU time	1.24 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	210004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856869014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.3856869014
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.796122190
Short name	T182
Test name
Test status
Simulation time	83053018 ps
CPU time	0.9 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	208648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796122190 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_disable_rom_integrity_check.796122190
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.249722290
Short name	T343
Test name
Test status
Simulation time	37383832 ps
CPU time	0.71 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249722290 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_malfunc.249722290
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_escalation_timeout.3624987629
Short name	T350
Test name
Test status
Simulation time	108635844 ps
CPU time	1.08 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624987629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.3624987629
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.827694178
Short name	T353
Test name
Test status
Simulation time	59428429 ps
CPU time	0.97 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	208620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827694178 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.827694178
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_global_esc.3863837495
Short name	T347
Test name
Test status
Simulation time	58676869 ps
CPU time	0.79 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863837495 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.3863837495
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_wakeup_race.1879466615
Short name	T346
Test name
Test status
Simulation time	102585153 ps
CPU time	1.09 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	208988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879466615 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_wakeup_race.1879466615
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset.805470652
Short name	T340
Test name
Test status
Simulation time	33974685 ps
CPU time	1.02 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	209000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805470652 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.805470652
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.2426499227
Short name	T354
Test name
Test status
Simulation time	114594525 ps
CPU time	1.15 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	220368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426499227 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.2426499227
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.3134540859
Short name	T356
Test name
Test status
Simulation time	229798165 ps
CPU time	1.44 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:22 AM UTC 24
Peak memory	209796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134540859 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_ctrl_config_regwen.3134540859
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1984468286
Short name	T358
Test name
Test status
Simulation time	877528535 ps
CPU time	3.4 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:23 AM UTC 24
Peak memory	211380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984468286 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1984468286
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3387894803
Short name	T359
Test name
Test status
Simulation time	891420526 ps
CPU time	3.34 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:23 AM UTC 24
Peak memory	211404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387894803 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3387894803
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.703462738
Short name	T348
Test name
Test status
Simulation time	53677396 ps
CPU time	0.99 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	208520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703462738 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_mubi.703462738
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_smoke.4064296373
Short name	T332
Test name
Test status
Simulation time	51121426 ps
CPU time	0.73 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:20 AM UTC 24
Peak memory	208680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064296373 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.4064296373
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all.3038949513
Short name	T357
Test name
Test status
Simulation time	813197435 ps
CPU time	1.35 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:22 AM UTC 24
Peak memory	210528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038949513 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.3038949513
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all_with_rand_reset.216063396
Short name	T382
Test name
Test status
Simulation time	7137856158 ps
CPU time	12.03 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:33 AM UTC 24
Peak memory	211752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=216063396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr _stress_all_with_rand_reset.216063396
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup.2194938312
Short name	T342
Test name
Test status
Simulation time	232451079 ps
CPU time	0.97 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	209036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194938312 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.2194938312
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.640479496
Short name	T345
Test name
Test status
Simulation time	739865568 ps
CPU time	1.23 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	210424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640479496 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.640479496
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/14.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_aborted_low_power.1341491452
Short name	T112
Test name
Test status
Simulation time	56656908 ps
CPU time	0.76 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:26 AM UTC 24
Peak memory	208744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341491452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.1341491452
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.2722966552
Short name	T183
Test name
Test status
Simulation time	81904140 ps
CPU time	0.76 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:26 AM UTC 24
Peak memory	208620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722966552 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disable_rom_integrity_check.2722966552
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.3167166805
Short name	T362
Test name
Test status
Simulation time	27472156 ps
CPU time	0.86 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:26 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167166805 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_malfunc.3167166805
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.2175165728
Short name	T372
Test name
Test status
Simulation time	404527810 ps
CPU time	1.18 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:26 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175165728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.2175165728
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.2620410594
Short name	T363
Test name
Test status
Simulation time	52564995 ps
CPU time	0.72 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:26 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620410594 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.2620410594
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_global_esc.332271165
Short name	T364
Test name
Test status
Simulation time	30078458 ps
CPU time	0.82 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:26 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332271165 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.332271165
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_wakeup_race.4292059941
Short name	T361
Test name
Test status
Simulation time	118678593 ps
CPU time	0.75 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:26 AM UTC 24
Peak memory	208988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292059941 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_wakeup_race.4292059941
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset.2818553462
Short name	T368
Test name
Test status
Simulation time	70678142 ps
CPU time	1.49 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:26 AM UTC 24
Peak memory	208764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818553462 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.2818553462
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset_invalid.2493693045
Short name	T373
Test name
Test status
Simulation time	125316934 ps
CPU time	1.19 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:26 AM UTC 24
Peak memory	220724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493693045 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.2493693045
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.637826458
Short name	T367
Test name
Test status
Simulation time	693113124 ps
CPU time	1.01 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:26 AM UTC 24
Peak memory	210064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637826458 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_ctrl_config_regwen.637826458
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1321774497
Short name	T374
Test name
Test status
Simulation time	896139885 ps
CPU time	2.05 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:27 AM UTC 24
Peak memory	211384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321774497 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1321774497
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1790878258
Short name	T337
Test name
Test status
Simulation time	1404111891 ps
CPU time	2.26 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:27 AM UTC 24
Peak memory	211512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790878258 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1790878258
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.4015652700
Short name	T369
Test name
Test status
Simulation time	69022276 ps
CPU time	1.23 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:26 AM UTC 24
Peak memory	209152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015652700 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_mubi.4015652700
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.1669692898
Short name	T351
Test name
Test status
Simulation time	91604677 ps
CPU time	0.71 seconds
Started	Sep 24 08:43:19 AM UTC 24
Finished	Sep 24 08:43:21 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669692898 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.1669692898
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.2490944552
Short name	T338
Test name
Test status
Simulation time	865503159 ps
CPU time	4.08 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:30 AM UTC 24
Peak memory	211708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490944552 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.2490944552
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.2373824557
Short name	T145
Test name
Test status
Simulation time	7183937879 ps
CPU time	11.36 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:37 AM UTC 24
Peak memory	211684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2373824557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmg r_stress_all_with_rand_reset.2373824557
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup.1258046521
Short name	T365
Test name
Test status
Simulation time	97431120 ps
CPU time	1.19 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:26 AM UTC 24
Peak memory	209036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258046521 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.1258046521
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup_reset.3679449078
Short name	T366
Test name
Test status
Simulation time	330523782 ps
CPU time	1.22 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:26 AM UTC 24
Peak memory	210408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679449078 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.3679449078
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/15.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_aborted_low_power.1018824925
Short name	T376
Test name
Test status
Simulation time	63578223 ps
CPU time	1.07 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:32 AM UTC 24
Peak memory	210388 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018824925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.1018824925
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.4265693705
Short name	T190
Test name
Test status
Simulation time	79978801 ps
CPU time	0.95 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:32 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265693705 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disable_rom_integrity_check.4265693705
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.3439651690
Short name	T322
Test name
Test status
Simulation time	40343653 ps
CPU time	0.69 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:32 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439651690 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_malfunc.3439651690
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_escalation_timeout.400221132
Short name	T379
Test name
Test status
Simulation time	203086115 ps
CPU time	1.11 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:32 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400221132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.400221132
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_glitch.2282792753
Short name	T341
Test name
Test status
Simulation time	57731181 ps
CPU time	0.75 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:32 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282792753 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.2282792753
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_global_esc.409507112
Short name	T352
Test name
Test status
Simulation time	66234636 ps
CPU time	0.7 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:32 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409507112 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.409507112
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_wakeup_race.1006219691
Short name	T377
Test name
Test status
Simulation time	249968880 ps
CPU time	1.21 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:32 AM UTC 24
Peak memory	210100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006219691 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_wakeup_race.1006219691
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.3794611767
Short name	T336
Test name
Test status
Simulation time	90166507 ps
CPU time	1.11 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:27 AM UTC 24
Peak memory	208380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794611767 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.3794611767
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset_invalid.3242218897
Short name	T381
Test name
Test status
Simulation time	96911002 ps
CPU time	1.17 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:32 AM UTC 24
Peak memory	220364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242218897 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.3242218897
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.3113638836
Short name	T384
Test name
Test status
Simulation time	198383487 ps
CPU time	1.53 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:33 AM UTC 24
Peak memory	210264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113638836 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_ctrl_config_regwen.3113638836
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3516357737
Short name	T387
Test name
Test status
Simulation time	837915102 ps
CPU time	3.15 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:34 AM UTC 24
Peak memory	211464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516357737 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3516357737
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1442255045
Short name	T389
Test name
Test status
Simulation time	895078518 ps
CPU time	3.81 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:35 AM UTC 24
Peak memory	211576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442255045 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1442255045
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.57934253
Short name	T375
Test name
Test status
Simulation time	65918475 ps
CPU time	0.97 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:32 AM UTC 24
Peak memory	209148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57934253 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_mubi.57934253
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.3557563696
Short name	T371
Test name
Test status
Simulation time	34086311 ps
CPU time	0.83 seconds
Started	Sep 24 08:43:24 AM UTC 24
Finished	Sep 24 08:43:26 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557563696 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.3557563696
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all.363838134
Short name	T390
Test name
Test status
Simulation time	664422482 ps
CPU time	3.92 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:35 AM UTC 24
Peak memory	211672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363838134 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.363838134
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all_with_rand_reset.3949428473
Short name	T404
Test name
Test status
Simulation time	2554787961 ps
CPU time	9.85 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:41 AM UTC 24
Peak memory	211764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3949428473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmg r_stress_all_with_rand_reset.3949428473
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.1512372350
Short name	T313
Test name
Test status
Simulation time	157646630 ps
CPU time	0.97 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:32 AM UTC 24
Peak memory	209032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512372350 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.1512372350
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup_reset.3497332054
Short name	T344
Test name
Test status
Simulation time	409869238 ps
CPU time	1.4 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:32 AM UTC 24
Peak memory	210524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497332054 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.3497332054
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/16.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_aborted_low_power.379363749
Short name	T380
Test name
Test status
Simulation time	18521927 ps
CPU time	0.66 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:32 AM UTC 24
Peak memory	209116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379363749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.379363749
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.1811036462
Short name	T398
Test name
Test status
Simulation time	65421283 ps
CPU time	1.01 seconds
Started	Sep 24 08:43:34 AM UTC 24
Finished	Sep 24 08:43:36 AM UTC 24
Peak memory	210468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811036462 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_disable_rom_integrity_check.1811036462
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.343765086
Short name	T391
Test name
Test status
Simulation time	32446542 ps
CPU time	0.76 seconds
Started	Sep 24 08:43:34 AM UTC 24
Finished	Sep 24 08:43:36 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343765086 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_malfunc.343765086
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_escalation_timeout.598455580
Short name	T397
Test name
Test status
Simulation time	401381420 ps
CPU time	1 seconds
Started	Sep 24 08:43:34 AM UTC 24
Finished	Sep 24 08:43:36 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598455580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.598455580
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_glitch.3886290019
Short name	T393
Test name
Test status
Simulation time	66825313 ps
CPU time	0.69 seconds
Started	Sep 24 08:43:34 AM UTC 24
Finished	Sep 24 08:43:36 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886290019 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.3886290019
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_global_esc.78769581
Short name	T394
Test name
Test status
Simulation time	56522318 ps
CPU time	0.89 seconds
Started	Sep 24 08:43:34 AM UTC 24
Finished	Sep 24 08:43:36 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78769581 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.78769581
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_wakeup_race.1246271089
Short name	T385
Test name
Test status
Simulation time	327801155 ps
CPU time	1.19 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:33 AM UTC 24
Peak memory	209720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246271089 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_wakeup_race.1246271089
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset.3926690365
Short name	T334
Test name
Test status
Simulation time	61111040 ps
CPU time	0.79 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:32 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926690365 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.3926690365
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset_invalid.2929238334
Short name	T401
Test name
Test status
Simulation time	93116823 ps
CPU time	1.12 seconds
Started	Sep 24 08:43:34 AM UTC 24
Finished	Sep 24 08:43:37 AM UTC 24
Peak memory	220336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929238334 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2929238334
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.3270101241
Short name	T399
Test name
Test status
Simulation time	248767683 ps
CPU time	1.31 seconds
Started	Sep 24 08:43:34 AM UTC 24
Finished	Sep 24 08:43:36 AM UTC 24
Peak memory	210000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270101241 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_ctrl_config_regwen.3270101241
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3976383705
Short name	T388
Test name
Test status
Simulation time	989038748 ps
CPU time	2.73 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:34 AM UTC 24
Peak memory	211508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976383705 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3976383705
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3221158493
Short name	T402
Test name
Test status
Simulation time	961599341 ps
CPU time	3.57 seconds
Started	Sep 24 08:43:34 AM UTC 24
Finished	Sep 24 08:43:39 AM UTC 24
Peak memory	211504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221158493 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3221158493
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.3436057749
Short name	T392
Test name
Test status
Simulation time	50334755 ps
CPU time	0.94 seconds
Started	Sep 24 08:43:34 AM UTC 24
Finished	Sep 24 08:43:36 AM UTC 24
Peak memory	209776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436057749 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_mubi.3436057749
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.622768857
Short name	T370
Test name
Test status
Simulation time	34669431 ps
CPU time	0.84 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:32 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622768857 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.622768857
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all.281556072
Short name	T403
Test name
Test status
Simulation time	2357820159 ps
CPU time	5.19 seconds
Started	Sep 24 08:43:34 AM UTC 24
Finished	Sep 24 08:43:41 AM UTC 24
Peak memory	211476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281556072 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.281556072
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all_with_rand_reset.2080610678
Short name	T146
Test name
Test status
Simulation time	1072116162 ps
CPU time	2.33 seconds
Started	Sep 24 08:43:34 AM UTC 24
Finished	Sep 24 08:43:38 AM UTC 24
Peak memory	211688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2080610678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmg r_stress_all_with_rand_reset.2080610678
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup.3812574472
Short name	T386
Test name
Test status
Simulation time	296896738 ps
CPU time	1.69 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:33 AM UTC 24
Peak memory	210772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812574472 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.3812574472
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup_reset.4121292864
Short name	T383
Test name
Test status
Simulation time	109720537 ps
CPU time	0.9 seconds
Started	Sep 24 08:43:30 AM UTC 24
Finished	Sep 24 08:43:33 AM UTC 24
Peak memory	208740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121292864 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.4121292864
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/17.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_aborted_low_power.3349917497
Short name	T407
Test name
Test status
Simulation time	17562989 ps
CPU time	0.79 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:42 AM UTC 24
Peak memory	208324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349917497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.3349917497
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_disable_rom_integrity_check.3549132837
Short name	T415
Test name
Test status
Simulation time	80337542 ps
CPU time	0.79 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:42 AM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549132837 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disable_rom_integrity_check.3549132837
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.2168217717
Short name	T406
Test name
Test status
Simulation time	39979585 ps
CPU time	0.59 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:42 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168217717 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_malfunc.2168217717
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_escalation_timeout.735247718
Short name	T417
Test name
Test status
Simulation time	220043555 ps
CPU time	0.94 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:42 AM UTC 24
Peak memory	208904 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735247718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.735247718
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_glitch.4161102288
Short name	T411
Test name
Test status
Simulation time	45281419 ps
CPU time	0.76 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:42 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161102288 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.4161102288
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_global_esc.1845241034
Short name	T410
Test name
Test status
Simulation time	34904047 ps
CPU time	0.8 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:42 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845241034 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.1845241034
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_wakeup_race.3410865320
Short name	T409
Test name
Test status
Simulation time	330232372 ps
CPU time	0.92 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:42 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410865320 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_wakeup_race.3410865320
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset.3111385538
Short name	T400
Test name
Test status
Simulation time	69736667 ps
CPU time	1.14 seconds
Started	Sep 24 08:43:34 AM UTC 24
Finished	Sep 24 08:43:37 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111385538 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.3111385538
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset_invalid.2069520721
Short name	T418
Test name
Test status
Simulation time	179718252 ps
CPU time	0.88 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:42 AM UTC 24
Peak memory	220724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069520721 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.2069520721
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.1085142648
Short name	T413
Test name
Test status
Simulation time	149858915 ps
CPU time	0.83 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:42 AM UTC 24
Peak memory	209160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085142648 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_ctrl_config_regwen.1085142648
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4015791571
Short name	T432
Test name
Test status
Simulation time	836833104 ps
CPU time	3.76 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:45 AM UTC 24
Peak memory	211508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015791571 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.4015791571
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3522816284
Short name	T429
Test name
Test status
Simulation time	983604209 ps
CPU time	2.48 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:44 AM UTC 24
Peak memory	211572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522816284 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3522816284
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.3330837231
Short name	T422
Test name
Test status
Simulation time	78224176 ps
CPU time	1.34 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:42 AM UTC 24
Peak memory	209832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330837231 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_mubi.3330837231
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_smoke.2283250347
Short name	T396
Test name
Test status
Simulation time	55631214 ps
CPU time	0.73 seconds
Started	Sep 24 08:43:34 AM UTC 24
Finished	Sep 24 08:43:36 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283250347 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.2283250347
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all.1741882610
Short name	T405
Test name
Test status
Simulation time	2000632751 ps
CPU time	7.93 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:50 AM UTC 24
Peak memory	211608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741882610 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.1741882610
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all_with_rand_reset.42926690
Short name	T444
Test name
Test status
Simulation time	3092517900 ps
CPU time	8.05 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:50 AM UTC 24
Peak memory	211472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=42926690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_ stress_all_with_rand_reset.42926690
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup.1883975238
Short name	T408
Test name
Test status
Simulation time	52956876 ps
CPU time	0.89 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:42 AM UTC 24
Peak memory	209036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883975238 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.1883975238
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup_reset.2949053566
Short name	T425
Test name
Test status
Simulation time	313995193 ps
CPU time	1.79 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:43 AM UTC 24
Peak memory	210444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949053566 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.2949053566
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/18.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_aborted_low_power.188541938
Short name	T423
Test name
Test status
Simulation time	143106203 ps
CPU time	0.87 seconds
Started	Sep 24 08:43:41 AM UTC 24
Finished	Sep 24 08:43:43 AM UTC 24
Peak memory	210064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188541938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.188541938
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.1896704312
Short name	T433
Test name
Test status
Simulation time	33003514 ps
CPU time	0.64 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:48 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896704312 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_malfunc.1896704312
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_escalation_timeout.3695297568
Short name	T437
Test name
Test status
Simulation time	391810888 ps
CPU time	1.02 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:49 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695297568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.3695297568
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_glitch.3960121270
Short name	T435
Test name
Test status
Simulation time	32162908 ps
CPU time	0.64 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:49 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960121270 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.3960121270
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_global_esc.360823661
Short name	T434
Test name
Test status
Simulation time	52776741 ps
CPU time	0.7 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:49 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360823661 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.360823661
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_wakeup_race.1221720637
Short name	T424
Test name
Test status
Simulation time	165839692 ps
CPU time	1.15 seconds
Started	Sep 24 08:43:41 AM UTC 24
Finished	Sep 24 08:43:43 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221720637 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_wakeup_race.1221720637
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset.2168567943
Short name	T421
Test name
Test status
Simulation time	23465335 ps
CPU time	0.93 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:42 AM UTC 24
Peak memory	209124 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168567943 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.2168567943
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset_invalid.2792084040
Short name	T438
Test name
Test status
Simulation time	145501473 ps
CPU time	0.97 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:49 AM UTC 24
Peak memory	220364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792084040 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.2792084040
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.1255838486
Short name	T440
Test name
Test status
Simulation time	336966600 ps
CPU time	1.4 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:49 AM UTC 24
Peak memory	210324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255838486 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_ctrl_config_regwen.1255838486
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1809531258
Short name	T430
Test name
Test status
Simulation time	1167966196 ps
CPU time	2.59 seconds
Started	Sep 24 08:43:41 AM UTC 24
Finished	Sep 24 08:43:44 AM UTC 24
Peak memory	211420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809531258 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1809531258
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2802731880
Short name	T431
Test name
Test status
Simulation time	1024247335 ps
CPU time	2.68 seconds
Started	Sep 24 08:43:41 AM UTC 24
Finished	Sep 24 08:43:44 AM UTC 24
Peak memory	211472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802731880 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2802731880
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3966989210
Short name	T427
Test name
Test status
Simulation time	173968694 ps
CPU time	1.05 seconds
Started	Sep 24 08:43:41 AM UTC 24
Finished	Sep 24 08:43:43 AM UTC 24
Peak memory	209508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966989210 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3966989210
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_smoke.3730025425
Short name	T420
Test name
Test status
Simulation time	31953732 ps
CPU time	0.85 seconds
Started	Sep 24 08:43:40 AM UTC 24
Finished	Sep 24 08:43:42 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730025425 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.3730025425
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all.189587399
Short name	T395
Test name
Test status
Simulation time	2410083998 ps
CPU time	3.45 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:52 AM UTC 24
Peak memory	211592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189587399 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.189587399
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all_with_rand_reset.20503611
Short name	T476
Test name
Test status
Simulation time	3165368628 ps
CPU time	12.68 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	211696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=20503611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_ stress_all_with_rand_reset.20503611
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup.2765476451
Short name	T426
Test name
Test status
Simulation time	157908484 ps
CPU time	1.19 seconds
Started	Sep 24 08:43:41 AM UTC 24
Finished	Sep 24 08:43:43 AM UTC 24
Peak memory	210212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765476451 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.2765476451
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup_reset.3972382313
Short name	T428
Test name
Test status
Simulation time	389850892 ps
CPU time	1.41 seconds
Started	Sep 24 08:43:41 AM UTC 24
Finished	Sep 24 08:43:43 AM UTC 24
Peak memory	210396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972382313 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.3972382313
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/19.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.1641229641
Short name	T128
Test name
Test status
Simulation time	20652109 ps
CPU time	0.95 seconds
Started	Sep 24 08:42:16 AM UTC 24
Finished	Sep 24 08:42:18 AM UTC 24
Peak memory	209112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641229641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.1641229641
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.2956329249
Short name	T156
Test name
Test status
Simulation time	89800943 ps
CPU time	1.12 seconds
Started	Sep 24 08:42:18 AM UTC 24
Finished	Sep 24 08:42:20 AM UTC 24
Peak memory	208620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956329249 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disable_rom_integrity_check.2956329249
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.1302430112
Short name	T150
Test name
Test status
Simulation time	39199410 ps
CPU time	0.9 seconds
Started	Sep 24 08:42:17 AM UTC 24
Finished	Sep 24 08:42:18 AM UTC 24
Peak memory	208864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302430112 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_malfunc.1302430112
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.4190873966
Short name	T151
Test name
Test status
Simulation time	623714943 ps
CPU time	1.43 seconds
Started	Sep 24 08:42:18 AM UTC 24
Finished	Sep 24 08:42:21 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190873966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.4190873966
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.3892892524
Short name	T19
Test name
Test status
Simulation time	27925713 ps
CPU time	0.91 seconds
Started	Sep 24 08:42:18 AM UTC 24
Finished	Sep 24 08:42:20 AM UTC 24
Peak memory	208676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892892524 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.3892892524
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.1550256688
Short name	T194
Test name
Test status
Simulation time	40213513 ps
CPU time	0.87 seconds
Started	Sep 24 08:42:18 AM UTC 24
Finished	Sep 24 08:42:20 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550256688 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.1550256688
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.366996572
Short name	T75
Test name
Test status
Simulation time	408073337 ps
CPU time	1.65 seconds
Started	Sep 24 08:42:15 AM UTC 24
Finished	Sep 24 08:42:17 AM UTC 24
Peak memory	209740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366996572 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wakeup_race.366996572
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.2223030038
Short name	T140
Test name
Test status
Simulation time	130343716 ps
CPU time	1.47 seconds
Started	Sep 24 08:42:15 AM UTC 24
Finished	Sep 24 08:42:17 AM UTC 24
Peak memory	210464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223030038 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.2223030038
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.39725699
Short name	T44
Test name
Test status
Simulation time	124712411 ps
CPU time	1.18 seconds
Started	Sep 24 08:42:18 AM UTC 24
Finished	Sep 24 08:42:20 AM UTC 24
Peak memory	220428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39725699 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.39725699
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.1481888465
Short name	T29
Test name
Test status
Simulation time	322425827 ps
CPU time	2.18 seconds
Started	Sep 24 08:42:18 AM UTC 24
Finished	Sep 24 08:42:22 AM UTC 24
Peak memory	239312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481888465 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1481888465
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.3978377967
Short name	T56
Test name
Test status
Simulation time	448175401 ps
CPU time	1.43 seconds
Started	Sep 24 08:42:18 AM UTC 24
Finished	Sep 24 08:42:20 AM UTC 24
Peak memory	210172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978377967 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_ctrl_config_regwen.3978377967
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3322190430
Short name	T163
Test name
Test status
Simulation time	870399101 ps
CPU time	3.5 seconds
Started	Sep 24 08:42:16 AM UTC 24
Finished	Sep 24 08:42:21 AM UTC 24
Peak memory	211512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322190430 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.3322190430
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1529804666
Short name	T157
Test name
Test status
Simulation time	1246264718 ps
CPU time	3.51 seconds
Started	Sep 24 08:42:16 AM UTC 24
Finished	Sep 24 08:42:21 AM UTC 24
Peak memory	211508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529804666 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.1529804666
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1917302258
Short name	T192
Test name
Test status
Simulation time	93931932 ps
CPU time	1.12 seconds
Started	Sep 24 08:42:16 AM UTC 24
Finished	Sep 24 08:42:19 AM UTC 24
Peak memory	209212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917302258 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1917302258
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.3785158707
Short name	T74
Test name
Test status
Simulation time	63352542 ps
CPU time	0.78 seconds
Started	Sep 24 08:42:15 AM UTC 24
Finished	Sep 24 08:42:16 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785158707 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.3785158707
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.3770096002
Short name	T43
Test name
Test status
Simulation time	1460241788 ps
CPU time	6.82 seconds
Started	Sep 24 08:42:20 AM UTC 24
Finished	Sep 24 08:42:28 AM UTC 24
Peak memory	211608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770096002 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.3770096002
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.262183259
Short name	T193
Test name
Test status
Simulation time	136535969 ps
CPU time	1.56 seconds
Started	Sep 24 08:42:16 AM UTC 24
Finished	Sep 24 08:42:19 AM UTC 24
Peak memory	209468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262183259 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.262183259
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.1758604164
Short name	T141
Test name
Test status
Simulation time	82352609 ps
CPU time	1.24 seconds
Started	Sep 24 08:42:16 AM UTC 24
Finished	Sep 24 08:42:18 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758604164 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.1758604164
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/2.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_aborted_low_power.3750656258
Short name	T442
Test name
Test status
Simulation time	52437598 ps
CPU time	0.92 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:49 AM UTC 24
Peak memory	210364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750656258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.3750656258
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.4086460974
Short name	T185
Test name
Test status
Simulation time	63859854 ps
CPU time	0.91 seconds
Started	Sep 24 08:43:48 AM UTC 24
Finished	Sep 24 08:43:53 AM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086460974 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disable_rom_integrity_check.4086460974
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.1817094969
Short name	T414
Test name
Test status
Simulation time	35843502 ps
CPU time	0.66 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:52 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817094969 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst_malfunc.1817094969
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_escalation_timeout.1880821257
Short name	T447
Test name
Test status
Simulation time	387669884 ps
CPU time	0.85 seconds
Started	Sep 24 08:43:48 AM UTC 24
Finished	Sep 24 08:43:52 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880821257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.1880821257
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_glitch.491473655
Short name	T416
Test name
Test status
Simulation time	37739840 ps
CPU time	0.63 seconds
Started	Sep 24 08:43:48 AM UTC 24
Finished	Sep 24 08:43:52 AM UTC 24
Peak memory	208680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491473655 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.491473655
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_global_esc.1139285854
Short name	T445
Test name
Test status
Simulation time	53349272 ps
CPU time	0.67 seconds
Started	Sep 24 08:43:48 AM UTC 24
Finished	Sep 24 08:43:52 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139285854 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.1139285854
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_wakeup_race.3882187623
Short name	T419
Test name
Test status
Simulation time	342572735 ps
CPU time	1.36 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:50 AM UTC 24
Peak memory	210364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882187623 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_wakeup_race.3882187623
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset.2729077311
Short name	T443
Test name
Test status
Simulation time	153592657 ps
CPU time	1.03 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:49 AM UTC 24
Peak memory	210468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729077311 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.2729077311
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset_invalid.3817794970
Short name	T449
Test name
Test status
Simulation time	118008734 ps
CPU time	0.91 seconds
Started	Sep 24 08:43:48 AM UTC 24
Finished	Sep 24 08:43:53 AM UTC 24
Peak memory	220664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817794970 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3817794970
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.2258438290
Short name	T448
Test name
Test status
Simulation time	431158948 ps
CPU time	1.06 seconds
Started	Sep 24 08:43:48 AM UTC 24
Finished	Sep 24 08:43:53 AM UTC 24
Peak memory	209736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258438290 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_ctrl_config_regwen.2258438290
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1891660489
Short name	T436
Test name
Test status
Simulation time	1566704079 ps
CPU time	2.23 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:51 AM UTC 24
Peak memory	211564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891660489 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1891660489
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3865417991
Short name	T450
Test name
Test status
Simulation time	1256043597 ps
CPU time	2.29 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:54 AM UTC 24
Peak memory	211480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865417991 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3865417991
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.2197760945
Short name	T446
Test name
Test status
Simulation time	68593468 ps
CPU time	0.93 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:52 AM UTC 24
Peak memory	209148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197760945 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig_mubi.2197760945
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_smoke.3636908207
Short name	T441
Test name
Test status
Simulation time	36623390 ps
CPU time	0.98 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:49 AM UTC 24
Peak memory	208320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636908207 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.3636908207
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all.2784866438
Short name	T458
Test name
Test status
Simulation time	1168501291 ps
CPU time	2.81 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:43:56 AM UTC 24
Peak memory	211540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784866438 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.2784866438
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all_with_rand_reset.458733781
Short name	T81
Test name
Test status
Simulation time	10531007624 ps
CPU time	16.18 seconds
Started	Sep 24 08:43:52 AM UTC 24
Finished	Sep 24 08:44:10 AM UTC 24
Peak memory	211696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=458733781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr _stress_all_with_rand_reset.458733781
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup.2174774512
Short name	T439
Test name
Test status
Simulation time	201429617 ps
CPU time	0.9 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:49 AM UTC 24
Peak memory	209036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174774512 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.2174774512
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup_reset.1516088934
Short name	T378
Test name
Test status
Simulation time	249925952 ps
CPU time	1.45 seconds
Started	Sep 24 08:43:47 AM UTC 24
Finished	Sep 24 08:43:50 AM UTC 24
Peak memory	210708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516088934 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.1516088934
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/20.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_aborted_low_power.2283647834
Short name	T462
Test name
Test status
Simulation time	97673981 ps
CPU time	0.89 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:43:58 AM UTC 24
Peak memory	209740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283647834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.2283647834
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.3555785421
Short name	T468
Test name
Test status
Simulation time	64514770 ps
CPU time	0.94 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555785421 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disable_rom_integrity_check.3555785421
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2245959688
Short name	T461
Test name
Test status
Simulation time	29930004 ps
CPU time	0.72 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:43:58 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245959688 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_malfunc.2245959688
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_escalation_timeout.2051372103
Short name	T457
Test name
Test status
Simulation time	429760190 ps
CPU time	0.84 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:43:56 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051372103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.2051372103
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_glitch.1586423778
Short name	T456
Test name
Test status
Simulation time	60668056 ps
CPU time	0.67 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:43:56 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586423778 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.1586423778
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_global_esc.3555046936
Short name	T454
Test name
Test status
Simulation time	62361035 ps
CPU time	0.62 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:43:56 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555046936 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.3555046936
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_wakeup_race.2987152676
Short name	T460
Test name
Test status
Simulation time	186283735 ps
CPU time	1.03 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:43:58 AM UTC 24
Peak memory	209596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987152676 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_wakeup_race.2987152676
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset.634458743
Short name	T459
Test name
Test status
Simulation time	132980978 ps
CPU time	0.93 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:43:58 AM UTC 24
Peak memory	210524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634458743 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.634458743
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset_invalid.4146385547
Short name	T475
Test name
Test status
Simulation time	148481954 ps
CPU time	1.23 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	220724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146385547 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.4146385547
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.1395064000
Short name	T455
Test name
Test status
Simulation time	113256508 ps
CPU time	0.72 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:43:56 AM UTC 24
Peak memory	208740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395064000 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_ctrl_config_regwen.1395064000
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.773663317
Short name	T465
Test name
Test status
Simulation time	838385778 ps
CPU time	3.12 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:44:00 AM UTC 24
Peak memory	211384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773663317 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.773663317
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2638681181
Short name	T467
Test name
Test status
Simulation time	764605400 ps
CPU time	3.47 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:44:00 AM UTC 24
Peak memory	211444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638681181 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2638681181
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.153043246
Short name	T463
Test name
Test status
Simulation time	91798016 ps
CPU time	0.89 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:43:58 AM UTC 24
Peak memory	209472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153043246 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig_mubi.153043246
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_smoke.3401904759
Short name	T412
Test name
Test status
Simulation time	30979492 ps
CPU time	0.81 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:43:54 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401904759 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.3401904759
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all.1581516838
Short name	T490
Test name
Test status
Simulation time	3035457509 ps
CPU time	4.26 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:04 AM UTC 24
Peak memory	211656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581516838 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.1581516838
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all_with_rand_reset.2557053836
Short name	T489
Test name
Test status
Simulation time	4594613123 ps
CPU time	4.02 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:04 AM UTC 24
Peak memory	211628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2557053836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmg r_stress_all_with_rand_reset.2557053836
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup.2795601141
Short name	T452
Test name
Test status
Simulation time	198242365 ps
CPU time	1.12 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:43:55 AM UTC 24
Peak memory	209396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795601141 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.2795601141
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup_reset.1934636325
Short name	T464
Test name
Test status
Simulation time	268397461 ps
CPU time	1.06 seconds
Started	Sep 24 08:43:53 AM UTC 24
Finished	Sep 24 08:43:58 AM UTC 24
Peak memory	210600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934636325 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.1934636325
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/21.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_aborted_low_power.2088675670
Short name	T478
Test name
Test status
Simulation time	47500333 ps
CPU time	1.06 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	210044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088675670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.2088675670
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_disable_rom_integrity_check.3918674825
Short name	T483
Test name
Test status
Simulation time	64892488 ps
CPU time	0.85 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	208944 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918674825 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_disable_rom_integrity_check.3918674825
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.2050195744
Short name	T479
Test name
Test status
Simulation time	29955740 ps
CPU time	0.8 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050195744 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst_malfunc.2050195744
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_escalation_timeout.3480692523
Short name	T484
Test name
Test status
Simulation time	114985847 ps
CPU time	1.01 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480692523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.3480692523
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_glitch.2631773254
Short name	T482
Test name
Test status
Simulation time	61892816 ps
CPU time	0.87 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	208628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631773254 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2631773254
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_global_esc.2786304527
Short name	T480
Test name
Test status
Simulation time	39188859 ps
CPU time	0.81 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786304527 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.2786304527
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_wakeup_race.3630994303
Short name	T471
Test name
Test status
Simulation time	90068215 ps
CPU time	0.96 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630994303 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_wakeup_race.3630994303
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset.977540040
Short name	T470
Test name
Test status
Simulation time	132388194 ps
CPU time	0.9 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	210464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977540040 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.977540040
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset_invalid.177667115
Short name	T485
Test name
Test status
Simulation time	110250557 ps
CPU time	0.91 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	220372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177667115 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.177667115
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.1034859285
Short name	T486
Test name
Test status
Simulation time	235130734 ps
CPU time	1.08 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	210060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034859285 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_ctrl_config_regwen.1034859285
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1743837021
Short name	T488
Test name
Test status
Simulation time	879183677 ps
CPU time	2.48 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:03 AM UTC 24
Peak memory	211704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743837021 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1743837021
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1463795594
Short name	T487
Test name
Test status
Simulation time	3534928488 ps
CPU time	2.26 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:02 AM UTC 24
Peak memory	211640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463795594 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1463795594
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3672646551
Short name	T477
Test name
Test status
Simulation time	89381728 ps
CPU time	0.98 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	209208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672646551 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3672646551
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_smoke.2661978664
Short name	T469
Test name
Test status
Simulation time	57279616 ps
CPU time	0.73 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661978664 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.2661978664
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all.22869580
Short name	T514
Test name
Test status
Simulation time	1573522456 ps
CPU time	3.56 seconds
Started	Sep 24 08:44:06 AM UTC 24
Finished	Sep 24 08:44:11 AM UTC 24
Peak memory	211616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22869580 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.22869580
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all_with_rand_reset.69697666
Short name	T80
Test name
Test status
Simulation time	1379253929 ps
CPU time	5.6 seconds
Started	Sep 24 08:44:06 AM UTC 24
Finished	Sep 24 08:44:13 AM UTC 24
Peak memory	211632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=69697666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_ stress_all_with_rand_reset.69697666
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup.4262349581
Short name	T474
Test name
Test status
Simulation time	62836598 ps
CPU time	0.96 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	209036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262349581 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.4262349581
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup_reset.1119623305
Short name	T481
Test name
Test status
Simulation time	465231292 ps
CPU time	1.23 seconds
Started	Sep 24 08:43:59 AM UTC 24
Finished	Sep 24 08:44:01 AM UTC 24
Peak memory	210504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119623305 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.1119623305
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/22.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_aborted_low_power.2869676820
Short name	T494
Test name
Test status
Simulation time	67558200 ps
CPU time	0.79 seconds
Started	Sep 24 08:44:06 AM UTC 24
Finished	Sep 24 08:44:08 AM UTC 24
Peak memory	208744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869676820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.2869676820
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_disable_rom_integrity_check.84474048
Short name	T504
Test name
Test status
Simulation time	73685409 ps
CPU time	0.85 seconds
Started	Sep 24 08:44:07 AM UTC 24
Finished	Sep 24 08:44:09 AM UTC 24
Peak memory	208648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84474048 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_disable_rom_integrity_check.84474048
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.2414983112
Short name	T497
Test name
Test status
Simulation time	29804737 ps
CPU time	0.78 seconds
Started	Sep 24 08:44:07 AM UTC 24
Finished	Sep 24 08:44:08 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414983112 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_malfunc.2414983112
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_escalation_timeout.2490437851
Short name	T508
Test name
Test status
Simulation time	389669793 ps
CPU time	1.03 seconds
Started	Sep 24 08:44:07 AM UTC 24
Finished	Sep 24 08:44:09 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490437851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.2490437851
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_glitch.749865291
Short name	T498
Test name
Test status
Simulation time	24761249 ps
CPU time	0.75 seconds
Started	Sep 24 08:44:07 AM UTC 24
Finished	Sep 24 08:44:08 AM UTC 24
Peak memory	208680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749865291 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.749865291
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_global_esc.342708607
Short name	T496
Test name
Test status
Simulation time	213676134 ps
CPU time	0.66 seconds
Started	Sep 24 08:44:07 AM UTC 24
Finished	Sep 24 08:44:08 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342708607 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.342708607
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_wakeup_race.3222096512
Short name	T502
Test name
Test status
Simulation time	367794865 ps
CPU time	1.21 seconds
Started	Sep 24 08:44:06 AM UTC 24
Finished	Sep 24 08:44:09 AM UTC 24
Peak memory	209664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222096512 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_wakeup_race.3222096512
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset.849261320
Short name	T493
Test name
Test status
Simulation time	78663123 ps
CPU time	0.72 seconds
Started	Sep 24 08:44:06 AM UTC 24
Finished	Sep 24 08:44:08 AM UTC 24
Peak memory	208676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849261320 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.849261320
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset_invalid.3600863052
Short name	T510
Test name
Test status
Simulation time	96111316 ps
CPU time	1.28 seconds
Started	Sep 24 08:44:07 AM UTC 24
Finished	Sep 24 08:44:09 AM UTC 24
Peak memory	220304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600863052 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.3600863052
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.2704569523
Short name	T501
Test name
Test status
Simulation time	134215776 ps
CPU time	0.83 seconds
Started	Sep 24 08:44:07 AM UTC 24
Finished	Sep 24 08:44:08 AM UTC 24
Peak memory	208320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704569523 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_ctrl_config_regwen.2704569523
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2092759563
Short name	T513
Test name
Test status
Simulation time	947741707 ps
CPU time	2.52 seconds
Started	Sep 24 08:44:06 AM UTC 24
Finished	Sep 24 08:44:10 AM UTC 24
Peak memory	211640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092759563 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2092759563
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3755541722
Short name	T491
Test name
Test status
Simulation time	1360343483 ps
CPU time	2.41 seconds
Started	Sep 24 08:44:06 AM UTC 24
Finished	Sep 24 08:44:10 AM UTC 24
Peak memory	211592 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755541722 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3755541722
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3056213300
Short name	T500
Test name
Test status
Simulation time	98614705 ps
CPU time	0.92 seconds
Started	Sep 24 08:44:06 AM UTC 24
Finished	Sep 24 08:44:08 AM UTC 24
Peak memory	209836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056213300 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3056213300
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_smoke.1400314207
Short name	T492
Test name
Test status
Simulation time	64177277 ps
CPU time	0.64 seconds
Started	Sep 24 08:44:06 AM UTC 24
Finished	Sep 24 08:44:08 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400314207 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.1400314207
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all.2940765611
Short name	T472
Test name
Test status
Simulation time	1323043038 ps
CPU time	4.6 seconds
Started	Sep 24 08:44:07 AM UTC 24
Finished	Sep 24 08:44:13 AM UTC 24
Peak memory	211532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940765611 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.2940765611
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all_with_rand_reset.1007101928
Short name	T535
Test name
Test status
Simulation time	17920893598 ps
CPU time	12.28 seconds
Started	Sep 24 08:44:07 AM UTC 24
Finished	Sep 24 08:44:20 AM UTC 24
Peak memory	211692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1007101928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmg r_stress_all_with_rand_reset.1007101928
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup.3352278033
Short name	T499
Test name
Test status
Simulation time	308198868 ps
CPU time	1.17 seconds
Started	Sep 24 08:44:06 AM UTC 24
Finished	Sep 24 08:44:08 AM UTC 24
Peak memory	209424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352278033 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.3352278033
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup_reset.2760239673
Short name	T503
Test name
Test status
Simulation time	354658045 ps
CPU time	1.21 seconds
Started	Sep 24 08:44:06 AM UTC 24
Finished	Sep 24 08:44:09 AM UTC 24
Peak memory	210708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760239673 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.2760239673
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/23.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_aborted_low_power.2749674718
Short name	T518
Test name
Test status
Simulation time	27689413 ps
CPU time	1.09 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	209740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749674718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.2749674718
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_disable_rom_integrity_check.1821912683
Short name	T519
Test name
Test status
Simulation time	140281879 ps
CPU time	0.9 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	208620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821912683 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_disable_rom_integrity_check.1821912683
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.2135597522
Short name	T515
Test name
Test status
Simulation time	33098299 ps
CPU time	0.76 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:16 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135597522 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_malfunc.2135597522
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_escalation_timeout.2811973190
Short name	T520
Test name
Test status
Simulation time	404843997 ps
CPU time	1.07 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811973190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.2811973190
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_glitch.1237669570
Short name	T473
Test name
Test status
Simulation time	69572067 ps
CPU time	0.66 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:16 AM UTC 24
Peak memory	208728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237669570 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.1237669570
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_global_esc.3458812138
Short name	T466
Test name
Test status
Simulation time	32615465 ps
CPU time	0.85 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458812138 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.3458812138
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_wakeup_race.1568298849
Short name	T512
Test name
Test status
Simulation time	222117225 ps
CPU time	1.23 seconds
Started	Sep 24 08:44:07 AM UTC 24
Finished	Sep 24 08:44:09 AM UTC 24
Peak memory	210100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568298849 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_wakeup_race.1568298849
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset.3379638694
Short name	T509
Test name
Test status
Simulation time	69559479 ps
CPU time	0.71 seconds
Started	Sep 24 08:44:07 AM UTC 24
Finished	Sep 24 08:44:09 AM UTC 24
Peak memory	208680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379638694 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.3379638694
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset_invalid.4002280793
Short name	T451
Test name
Test status
Simulation time	101172291 ps
CPU time	1.07 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	220364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002280793 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.4002280793
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.2973959398
Short name	T516
Test name
Test status
Simulation time	157699941 ps
CPU time	0.8 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	208680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973959398 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_ctrl_config_regwen.2973959398
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4152428088
Short name	T532
Test name
Test status
Simulation time	908455448 ps
CPU time	2.89 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:18 AM UTC 24
Peak memory	211524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152428088 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.4152428088
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4256437844
Short name	T530
Test name
Test status
Simulation time	1011549745 ps
CPU time	2.25 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:18 AM UTC 24
Peak memory	211568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256437844 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.4256437844
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.850953957
Short name	T517
Test name
Test status
Simulation time	159289819 ps
CPU time	0.9 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	209208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850953957 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_mubi.850953957
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_smoke.1461832521
Short name	T507
Test name
Test status
Simulation time	64026947 ps
CPU time	0.75 seconds
Started	Sep 24 08:44:07 AM UTC 24
Finished	Sep 24 08:44:09 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461832521 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.1461832521
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all.438034750
Short name	T531
Test name
Test status
Simulation time	1052812527 ps
CPU time	2 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:18 AM UTC 24
Peak memory	210472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438034750 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.438034750
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all_with_rand_reset.1323356549
Short name	T563
Test name
Test status
Simulation time	3134247235 ps
CPU time	12.3 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:28 AM UTC 24
Peak memory	211628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1323356549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmg r_stress_all_with_rand_reset.1323356549
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup.561710463
Short name	T506
Test name
Test status
Simulation time	47813156 ps
CPU time	0.7 seconds
Started	Sep 24 08:44:07 AM UTC 24
Finished	Sep 24 08:44:09 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561710463 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.561710463
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup_reset.4148626443
Short name	T511
Test name
Test status
Simulation time	278878614 ps
CPU time	1.01 seconds
Started	Sep 24 08:44:07 AM UTC 24
Finished	Sep 24 08:44:09 AM UTC 24
Peak memory	210708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148626443 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.4148626443
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_aborted_low_power.2702658640
Short name	T523
Test name
Test status
Simulation time	52839323 ps
CPU time	0.94 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	209008 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702658640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.2702658640
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_disable_rom_integrity_check.3143555878
Short name	T536
Test name
Test status
Simulation time	70362987 ps
CPU time	0.89 seconds
Started	Sep 24 08:44:24 AM UTC 24
Finished	Sep 24 08:44:26 AM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143555878 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_disable_rom_integrity_check.3143555878
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.3786839288
Short name	T522
Test name
Test status
Simulation time	44804827 ps
CPU time	0.66 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786839288 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_malfunc.3786839288
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_escalation_timeout.2164222151
Short name	T529
Test name
Test status
Simulation time	470346547 ps
CPU time	0.84 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164222151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2164222151
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_glitch.2866122987
Short name	T526
Test name
Test status
Simulation time	49884622 ps
CPU time	0.76 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866122987 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.2866122987
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_global_esc.3719775743
Short name	T505
Test name
Test status
Simulation time	43401035 ps
CPU time	0.57 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719775743 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.3719775743
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_wakeup_race.3371052368
Short name	T521
Test name
Test status
Simulation time	642570055 ps
CPU time	0.95 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	209740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371052368 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wakeup_race.3371052368
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset.724011019
Short name	T453
Test name
Test status
Simulation time	71281384 ps
CPU time	1.01 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	210524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724011019 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.724011019
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset_invalid.2464614910
Short name	T537
Test name
Test status
Simulation time	161648355 ps
CPU time	0.8 seconds
Started	Sep 24 08:44:24 AM UTC 24
Finished	Sep 24 08:44:26 AM UTC 24
Peak memory	210152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464614910 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.2464614910
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.1606545340
Short name	T524
Test name
Test status
Simulation time	275034761 ps
CPU time	0.75 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	208740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606545340 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_ctrl_config_regwen.1606545340
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3424476073
Short name	T533
Test name
Test status
Simulation time	895826498 ps
CPU time	3.18 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:19 AM UTC 24
Peak memory	211576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424476073 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3424476073
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.711737199
Short name	T534
Test name
Test status
Simulation time	813073328 ps
CPU time	3.59 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:20 AM UTC 24
Peak memory	211580 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711737199 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.711737199
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1387619881
Short name	T525
Test name
Test status
Simulation time	191669355 ps
CPU time	0.82 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	209956 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387619881 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1387619881
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_smoke.1030223854
Short name	T495
Test name
Test status
Simulation time	30889279 ps
CPU time	0.71 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	208320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030223854 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.1030223854
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.2446350912
Short name	T564
Test name
Test status
Simulation time	2579983001 ps
CPU time	3.65 seconds
Started	Sep 24 08:44:24 AM UTC 24
Finished	Sep 24 08:44:29 AM UTC 24
Peak memory	211108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446350912 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.2446350912
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup.1438226655
Short name	T527
Test name
Test status
Simulation time	236151667 ps
CPU time	1.07 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	209708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438226655 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.1438226655
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup_reset.2986957826
Short name	T528
Test name
Test status
Simulation time	261774080 ps
CPU time	1.12 seconds
Started	Sep 24 08:44:15 AM UTC 24
Finished	Sep 24 08:44:17 AM UTC 24
Peak memory	210240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986957826 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.2986957826
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_aborted_low_power.3904679785
Short name	T540
Test name
Test status
Simulation time	25447267 ps
CPU time	0.62 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:26 AM UTC 24
Peak memory	209116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904679785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.3904679785
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.2574001779
Short name	T551
Test name
Test status
Simulation time	67067384 ps
CPU time	0.84 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:27 AM UTC 24
Peak memory	209140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574001779 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disable_rom_integrity_check.2574001779
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.685044077
Short name	T543
Test name
Test status
Simulation time	38905224 ps
CPU time	0.55 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:26 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685044077 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst_malfunc.685044077
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.1281765320
Short name	T553
Test name
Test status
Simulation time	114530324 ps
CPU time	1 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:27 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281765320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.1281765320
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.985828804
Short name	T549
Test name
Test status
Simulation time	76309050 ps
CPU time	0.76 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:27 AM UTC 24
Peak memory	208656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985828804 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.985828804
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.2988590521
Short name	T545
Test name
Test status
Simulation time	39443098 ps
CPU time	0.65 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:26 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988590521 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.2988590521
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_wakeup_race.3638159544
Short name	T546
Test name
Test status
Simulation time	339557936 ps
CPU time	1.05 seconds
Started	Sep 24 08:44:24 AM UTC 24
Finished	Sep 24 08:44:27 AM UTC 24
Peak memory	209800 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638159544 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_wakeup_race.3638159544
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset.3379596717
Short name	T542
Test name
Test status
Simulation time	104721780 ps
CPU time	0.84 seconds
Started	Sep 24 08:44:24 AM UTC 24
Finished	Sep 24 08:44:26 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379596717 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.3379596717
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.1806040541
Short name	T555
Test name
Test status
Simulation time	100023297 ps
CPU time	1.23 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:27 AM UTC 24
Peak memory	220368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806040541 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.1806040541
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.1713529372
Short name	T552
Test name
Test status
Simulation time	384809735 ps
CPU time	1.12 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:27 AM UTC 24
Peak memory	210000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713529372 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_ctrl_config_regwen.1713529372
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3133239346
Short name	T561
Test name
Test status
Simulation time	1198716955 ps
CPU time	2.44 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:28 AM UTC 24
Peak memory	211576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133239346 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3133239346
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2290515674
Short name	T562
Test name
Test status
Simulation time	1307143539 ps
CPU time	2.34 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:28 AM UTC 24
Peak memory	211400 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290515674 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2290515674
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.3930125613
Short name	T547
Test name
Test status
Simulation time	90743577 ps
CPU time	0.97 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:27 AM UTC 24
Peak memory	209212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930125613 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_mubi.3930125613
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_smoke.3228425897
Short name	T539
Test name
Test status
Simulation time	30629333 ps
CPU time	0.69 seconds
Started	Sep 24 08:44:24 AM UTC 24
Finished	Sep 24 08:44:26 AM UTC 24
Peak memory	208320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228425897 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.3228425897
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.1360671730
Short name	T566
Test name
Test status
Simulation time	2671742551 ps
CPU time	6.04 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:32 AM UTC 24
Peak memory	211600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360671730 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.1360671730
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.4088541946
Short name	T147
Test name
Test status
Simulation time	4057714595 ps
CPU time	6.39 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:33 AM UTC 24
Peak memory	211696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4088541946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmg r_stress_all_with_rand_reset.4088541946
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.615371054
Short name	T544
Test name
Test status
Simulation time	76610156 ps
CPU time	0.86 seconds
Started	Sep 24 08:44:24 AM UTC 24
Finished	Sep 24 08:44:26 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615371054 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.615371054
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup_reset.3003445965
Short name	T554
Test name
Test status
Simulation time	225231955 ps
CPU time	1.49 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:27 AM UTC 24
Peak memory	210528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003445965 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.3003445965
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/26.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.899010044
Short name	T556
Test name
Test status
Simulation time	72121347 ps
CPU time	0.81 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:27 AM UTC 24
Peak memory	210064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899010044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.899010044
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.1624047965
Short name	T573
Test name
Test status
Simulation time	54922559 ps
CPU time	0.99 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	209700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624047965 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disable_rom_integrity_check.1624047965
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1233384306
Short name	T567
Test name
Test status
Simulation time	39415554 ps
CPU time	0.6 seconds
Started	Sep 24 08:44:33 AM UTC 24
Finished	Sep 24 08:44:35 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233384306 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_malfunc.1233384306
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_escalation_timeout.2127147463
Short name	T571
Test name
Test status
Simulation time	440713330 ps
CPU time	0.82 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:35 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127147463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.2127147463
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_glitch.1057323524
Short name	T570
Test name
Test status
Simulation time	57006997 ps
CPU time	0.67 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:35 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057323524 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.1057323524
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_global_esc.1484548117
Short name	T568
Test name
Test status
Simulation time	26796254 ps
CPU time	0.64 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:35 AM UTC 24
Peak memory	208880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484548117 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.1484548117
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.2490122869
Short name	T557
Test name
Test status
Simulation time	204062846 ps
CPU time	1 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:27 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490122869 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_wakeup_race.2490122869
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.1020576784
Short name	T559
Test name
Test status
Simulation time	110021773 ps
CPU time	1.13 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:27 AM UTC 24
Peak memory	209676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020576784 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.1020576784
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset_invalid.3656715212
Short name	T575
Test name
Test status
Simulation time	119267955 ps
CPU time	1.06 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	220364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656715212 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.3656715212
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.4198829044
Short name	T577
Test name
Test status
Simulation time	302288071 ps
CPU time	1.23 seconds
Started	Sep 24 08:44:33 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	209736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198829044 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_ctrl_config_regwen.4198829044
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3511962357
Short name	T587
Test name
Test status
Simulation time	876637471 ps
CPU time	3.19 seconds
Started	Sep 24 08:44:33 AM UTC 24
Finished	Sep 24 08:44:38 AM UTC 24
Peak memory	211576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511962357 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3511962357
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2378688184
Short name	T584
Test name
Test status
Simulation time	1526009780 ps
CPU time	2.03 seconds
Started	Sep 24 08:44:33 AM UTC 24
Finished	Sep 24 08:44:37 AM UTC 24
Peak memory	211576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378688184 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2378688184
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.840406808
Short name	T569
Test name
Test status
Simulation time	83996892 ps
CPU time	0.87 seconds
Started	Sep 24 08:44:33 AM UTC 24
Finished	Sep 24 08:44:35 AM UTC 24
Peak memory	209772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840406808 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_mubi.840406808
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.3496308880
Short name	T548
Test name
Test status
Simulation time	32759705 ps
CPU time	0.64 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:27 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496308880 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.3496308880
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all.3494989017
Short name	T588
Test name
Test status
Simulation time	618548593 ps
CPU time	2.84 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:38 AM UTC 24
Peak memory	211476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494989017 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.3494989017
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all_with_rand_reset.742946806
Short name	T628
Test name
Test status
Simulation time	10167770150 ps
CPU time	16.78 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:52 AM UTC 24
Peak memory	211772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=742946806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr _stress_all_with_rand_reset.742946806
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.317245439
Short name	T560
Test name
Test status
Simulation time	240597545 ps
CPU time	1.26 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:27 AM UTC 24
Peak memory	209472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317245439 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.317245439
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.3751812145
Short name	T558
Test name
Test status
Simulation time	96726567 ps
CPU time	1.14 seconds
Started	Sep 24 08:44:25 AM UTC 24
Finished	Sep 24 08:44:27 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751812145 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.3751812145
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/27.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.718795183
Short name	T550
Test name
Test status
Simulation time	45975793 ps
CPU time	0.95 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	210268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718795183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.718795183
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.651466216
Short name	T541
Test name
Test status
Simulation time	61874345 ps
CPU time	0.82 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651466216 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_disable_rom_integrity_check.651466216
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.2947717794
Short name	T576
Test name
Test status
Simulation time	39953860 ps
CPU time	0.64 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947717794 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst_malfunc.2947717794
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_escalation_timeout.1972556891
Short name	T565
Test name
Test status
Simulation time	398587866 ps
CPU time	0.87 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972556891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.1972556891
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_glitch.1410670249
Short name	T581
Test name
Test status
Simulation time	48222922 ps
CPU time	0.76 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410670249 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.1410670249
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_global_esc.3285441875
Short name	T580
Test name
Test status
Simulation time	27687144 ps
CPU time	0.71 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285441875 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.3285441875
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_wakeup_race.3931982906
Short name	T572
Test name
Test status
Simulation time	39597846 ps
CPU time	0.69 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931982906 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_wakeup_race.3931982906
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset.2932096941
Short name	T579
Test name
Test status
Simulation time	106698238 ps
CPU time	0.98 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	210000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932096941 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.2932096941
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset_invalid.245904460
Short name	T582
Test name
Test status
Simulation time	119752786 ps
CPU time	0.9 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	220544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245904460 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.245904460
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.1328794280
Short name	T583
Test name
Test status
Simulation time	336689749 ps
CPU time	1.13 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	210264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328794280 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_ctrl_config_regwen.1328794280
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2086751546
Short name	T589
Test name
Test status
Simulation time	795544590 ps
CPU time	3.27 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:38 AM UTC 24
Peak memory	211560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086751546 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2086751546
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2874234040
Short name	T586
Test name
Test status
Simulation time	2190213439 ps
CPU time	2.46 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:38 AM UTC 24
Peak memory	211632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874234040 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2874234040
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2937165630
Short name	T538
Test name
Test status
Simulation time	164845225 ps
CPU time	0.89 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	209776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937165630 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2937165630
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_smoke.3372572282
Short name	T574
Test name
Test status
Simulation time	30424021 ps
CPU time	0.82 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	208320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372572282 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.3372572282
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all.1947364706
Short name	T621
Test name
Test status
Simulation time	758859764 ps
CPU time	2.91 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:48 AM UTC 24
Peak memory	211524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947364706 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.1947364706
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all_with_rand_reset.2666944564
Short name	T626
Test name
Test status
Simulation time	1140203806 ps
CPU time	5.12 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:50 AM UTC 24
Peak memory	211440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2666944564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmg r_stress_all_with_rand_reset.2666944564
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup.3181264521
Short name	T578
Test name
Test status
Simulation time	388895672 ps
CPU time	0.94 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:36 AM UTC 24
Peak memory	209732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181264521 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.3181264521
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup_reset.2401350700
Short name	T585
Test name
Test status
Simulation time	199520241 ps
CPU time	1.58 seconds
Started	Sep 24 08:44:34 AM UTC 24
Finished	Sep 24 08:44:37 AM UTC 24
Peak memory	210708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401350700 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.2401350700
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/28.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_aborted_low_power.2394223558
Short name	T597
Test name
Test status
Simulation time	20620175 ps
CPU time	0.78 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	208324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394223558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.2394223558
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_disable_rom_integrity_check.3383198091
Short name	T602
Test name
Test status
Simulation time	66197481 ps
CPU time	0.83 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	208560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383198091 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_disable_rom_integrity_check.3383198091
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2424854859
Short name	T594
Test name
Test status
Simulation time	38407887 ps
CPU time	0.62 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	208692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424854859 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_malfunc.2424854859
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_escalation_timeout.4163477871
Short name	T604
Test name
Test status
Simulation time	345427597 ps
CPU time	0.92 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163477871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.4163477871
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_glitch.975184346
Short name	T599
Test name
Test status
Simulation time	157968892 ps
CPU time	0.68 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	208676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975184346 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.975184346
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_global_esc.839740073
Short name	T598
Test name
Test status
Simulation time	43050272 ps
CPU time	0.8 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839740073 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.839740073
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_wakeup_race.2727792059
Short name	T601
Test name
Test status
Simulation time	160732367 ps
CPU time	1.12 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727792059 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_wakeup_race.2727792059
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset.3328845246
Short name	T591
Test name
Test status
Simulation time	52330804 ps
CPU time	0.62 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328845246 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.3328845246
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset_invalid.186128057
Short name	T610
Test name
Test status
Simulation time	106695283 ps
CPU time	0.99 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	220172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186128057 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.186128057
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.516397656
Short name	T603
Test name
Test status
Simulation time	259767533 ps
CPU time	1.01 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	210064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516397656 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_ctrl_config_regwen.516397656
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.381104048
Short name	T620
Test name
Test status
Simulation time	1127041031 ps
CPU time	2.11 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:47 AM UTC 24
Peak memory	211628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381104048 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.381104048
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2597203704
Short name	T624
Test name
Test status
Simulation time	890251906 ps
CPU time	3.64 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:49 AM UTC 24
Peak memory	211464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597203704 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2597203704
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1518584456
Short name	T600
Test name
Test status
Simulation time	66515644 ps
CPU time	1.01 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	209152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518584456 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1518584456
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_smoke.2907673862
Short name	T592
Test name
Test status
Simulation time	34706958 ps
CPU time	0.73 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907673862 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.2907673862
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all.982678736
Short name	T625
Test name
Test status
Simulation time	680254682 ps
CPU time	3.41 seconds
Started	Sep 24 08:44:45 AM UTC 24
Finished	Sep 24 08:44:49 AM UTC 24
Peak memory	211476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982678736 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.982678736
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all_with_rand_reset.3317288070
Short name	T627
Test name
Test status
Simulation time	2407258322 ps
CPU time	4.8 seconds
Started	Sep 24 08:44:45 AM UTC 24
Finished	Sep 24 08:44:50 AM UTC 24
Peak memory	211892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3317288070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmg r_stress_all_with_rand_reset.3317288070
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup.3196551546
Short name	T596
Test name
Test status
Simulation time	29234781 ps
CPU time	0.84 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	209036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196551546 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.3196551546
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup_reset.1737083137
Short name	T593
Test name
Test status
Simulation time	71247793 ps
CPU time	0.71 seconds
Started	Sep 24 08:44:44 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	209484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737083137 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.1737083137
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/29.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.85768138
Short name	T77
Test name
Test status
Simulation time	135701895 ps
CPU time	1.09 seconds
Started	Sep 24 08:42:21 AM UTC 24
Finished	Sep 24 08:42:24 AM UTC 24
Peak memory	209720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85768138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ= pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.85768138
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.2101879785
Short name	T158
Test name
Test status
Simulation time	61043122 ps
CPU time	1.31 seconds
Started	Sep 24 08:42:23 AM UTC 24
Finished	Sep 24 08:42:25 AM UTC 24
Peak memory	209112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101879785 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disable_rom_integrity_check.2101879785
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.3358542421
Short name	T155
Test name
Test status
Simulation time	31219648 ps
CPU time	0.95 seconds
Started	Sep 24 08:42:22 AM UTC 24
Finished	Sep 24 08:42:24 AM UTC 24
Peak memory	208864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358542421 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_malfunc.3358542421
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.1599551225
Short name	T152
Test name
Test status
Simulation time	209091715 ps
CPU time	1.31 seconds
Started	Sep 24 08:42:23 AM UTC 24
Finished	Sep 24 08:42:25 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599551225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.1599551225
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.4118719509
Short name	T34
Test name
Test status
Simulation time	44287536 ps
CPU time	1.02 seconds
Started	Sep 24 08:42:23 AM UTC 24
Finished	Sep 24 08:42:25 AM UTC 24
Peak memory	208676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118719509 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.4118719509
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.86609311
Short name	T201
Test name
Test status
Simulation time	25545300 ps
CPU time	0.93 seconds
Started	Sep 24 08:42:23 AM UTC 24
Finished	Sep 24 08:42:25 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86609311 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.86609311
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.426846026
Short name	T76
Test name
Test status
Simulation time	86152459 ps
CPU time	1.38 seconds
Started	Sep 24 08:42:20 AM UTC 24
Finished	Sep 24 08:42:22 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426846026 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wakeup_race.426846026
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.824358519
Short name	T196
Test name
Test status
Simulation time	95716442 ps
CPU time	1.35 seconds
Started	Sep 24 08:42:20 AM UTC 24
Finished	Sep 24 08:42:22 AM UTC 24
Peak memory	210304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824358519 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.824358519
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.3707888321
Short name	T202
Test name
Test status
Simulation time	106772689 ps
CPU time	1.63 seconds
Started	Sep 24 08:42:23 AM UTC 24
Finished	Sep 24 08:42:26 AM UTC 24
Peak memory	220372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707888321 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.3707888321
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.1588870712
Short name	T21
Test name
Test status
Simulation time	647527854 ps
CPU time	3.12 seconds
Started	Sep 24 08:42:23 AM UTC 24
Finished	Sep 24 08:42:27 AM UTC 24
Peak memory	239312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588870712 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.1588870712
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.1905300557
Short name	T200
Test name
Test status
Simulation time	162382651 ps
CPU time	1.28 seconds
Started	Sep 24 08:42:22 AM UTC 24
Finished	Sep 24 08:42:24 AM UTC 24
Peak memory	209308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905300557 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_ctrl_config_regwen.1905300557
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3956358444
Short name	T142
Test name
Test status
Simulation time	1031628101 ps
CPU time	3.28 seconds
Started	Sep 24 08:42:22 AM UTC 24
Finished	Sep 24 08:42:26 AM UTC 24
Peak memory	211576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956358444 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.3956358444
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1461770517
Short name	T204
Test name
Test status
Simulation time	978630985 ps
CPU time	4.27 seconds
Started	Sep 24 08:42:22 AM UTC 24
Finished	Sep 24 08:42:27 AM UTC 24
Peak memory	211408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461770517 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.1461770517
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.1647886377
Short name	T199
Test name
Test status
Simulation time	52967422 ps
CPU time	1.39 seconds
Started	Sep 24 08:42:22 AM UTC 24
Finished	Sep 24 08:42:24 AM UTC 24
Peak memory	209596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647886377 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_mubi.1647886377
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.1261790754
Short name	T195
Test name
Test status
Simulation time	28882978 ps
CPU time	0.97 seconds
Started	Sep 24 08:42:20 AM UTC 24
Finished	Sep 24 08:42:22 AM UTC 24
Peak memory	208316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261790754 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.1261790754
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.1435942073
Short name	T106
Test name
Test status
Simulation time	959944720 ps
CPU time	6.19 seconds
Started	Sep 24 08:42:25 AM UTC 24
Finished	Sep 24 08:42:32 AM UTC 24
Peak memory	211464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435942073 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.1435942073
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.1540648686
Short name	T96
Test name
Test status
Simulation time	24648855794 ps
CPU time	11.9 seconds
Started	Sep 24 08:42:25 AM UTC 24
Finished	Sep 24 08:42:38 AM UTC 24
Peak memory	211820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1540648686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr _stress_all_with_rand_reset.1540648686
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.3823824
Short name	T197
Test name
Test status
Simulation time	183271525 ps
CPU time	1.84 seconds
Started	Sep 24 08:42:20 AM UTC 24
Finished	Sep 24 08:42:23 AM UTC 24
Peak memory	209736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823824 -assert nopostproc +UVM_TESTNAME=pwrmgr_ base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.3823824
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.4206859371
Short name	T198
Test name
Test status
Simulation time	94544814 ps
CPU time	1.38 seconds
Started	Sep 24 08:42:21 AM UTC 24
Finished	Sep 24 08:42:24 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206859371 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.4206859371
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/3.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_aborted_low_power.3065517363
Short name	T613
Test name
Test status
Simulation time	177354682 ps
CPU time	0.79 seconds
Started	Sep 24 08:44:45 AM UTC 24
Finished	Sep 24 08:44:47 AM UTC 24
Peak memory	208864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065517363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.3065517363
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.1096078697
Short name	T637
Test name
Test status
Simulation time	66590810 ps
CPU time	1.02 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096078697 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disable_rom_integrity_check.1096078697
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.712047775
Short name	T614
Test name
Test status
Simulation time	38173203 ps
CPU time	0.74 seconds
Started	Sep 24 08:44:45 AM UTC 24
Finished	Sep 24 08:44:47 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712047775 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_malfunc.712047775
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_escalation_timeout.1883541564
Short name	T634
Test name
Test status
Simulation time	378259544 ps
CPU time	0.9 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	208772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883541564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.1883541564
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_glitch.2974998267
Short name	T630
Test name
Test status
Simulation time	82017289 ps
CPU time	0.6 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:56 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974998267 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.2974998267
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_global_esc.3225477132
Short name	T612
Test name
Test status
Simulation time	234366686 ps
CPU time	0.66 seconds
Started	Sep 24 08:44:45 AM UTC 24
Finished	Sep 24 08:44:47 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225477132 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.3225477132
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_wakeup_race.1007313470
Short name	T616
Test name
Test status
Simulation time	334076976 ps
CPU time	1.06 seconds
Started	Sep 24 08:44:45 AM UTC 24
Finished	Sep 24 08:44:47 AM UTC 24
Peak memory	209864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007313470 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_wakeup_race.1007313470
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset.2682550807
Short name	T615
Test name
Test status
Simulation time	59672032 ps
CPU time	1.11 seconds
Started	Sep 24 08:44:45 AM UTC 24
Finished	Sep 24 08:44:47 AM UTC 24
Peak memory	210528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682550807 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.2682550807
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset_invalid.4160275060
Short name	T635
Test name
Test status
Simulation time	118196417 ps
CPU time	0.89 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	220148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160275060 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.4160275060
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.1439084400
Short name	T618
Test name
Test status
Simulation time	199383533 ps
CPU time	1.01 seconds
Started	Sep 24 08:44:45 AM UTC 24
Finished	Sep 24 08:44:47 AM UTC 24
Peak memory	210000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439084400 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_ctrl_config_regwen.1439084400
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4143374732
Short name	T623
Test name
Test status
Simulation time	1044778136 ps
CPU time	2.47 seconds
Started	Sep 24 08:44:45 AM UTC 24
Finished	Sep 24 08:44:48 AM UTC 24
Peak memory	211656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143374732 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.4143374732
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4040750950
Short name	T622
Test name
Test status
Simulation time	1249968655 ps
CPU time	2.13 seconds
Started	Sep 24 08:44:45 AM UTC 24
Finished	Sep 24 08:44:48 AM UTC 24
Peak memory	211524 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040750950 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.4040750950
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3925706309
Short name	T617
Test name
Test status
Simulation time	65836019 ps
CPU time	1.05 seconds
Started	Sep 24 08:44:45 AM UTC 24
Finished	Sep 24 08:44:47 AM UTC 24
Peak memory	209772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925706309 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3925706309
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_smoke.2366332824
Short name	T605
Test name
Test status
Simulation time	96534117 ps
CPU time	0.66 seconds
Started	Sep 24 08:44:45 AM UTC 24
Finished	Sep 24 08:44:46 AM UTC 24
Peak memory	208680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366332824 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.2366332824
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all.4160039279
Short name	T631
Test name
Test status
Simulation time	633456218 ps
CPU time	3.25 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:59 AM UTC 24
Peak memory	211608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160039279 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.4160039279
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all_with_rand_reset.1322295677
Short name	T629
Test name
Test status
Simulation time	6194120957 ps
CPU time	11.26 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:45:07 AM UTC 24
Peak memory	211684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1322295677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmg r_stress_all_with_rand_reset.1322295677
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup.1967463740
Short name	T611
Test name
Test status
Simulation time	71543763 ps
CPU time	0.79 seconds
Started	Sep 24 08:44:45 AM UTC 24
Finished	Sep 24 08:44:47 AM UTC 24
Peak memory	208976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967463740 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.1967463740
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup_reset.4010897604
Short name	T619
Test name
Test status
Simulation time	211726530 ps
CPU time	1.41 seconds
Started	Sep 24 08:44:45 AM UTC 24
Finished	Sep 24 08:44:47 AM UTC 24
Peak memory	210240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010897604 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.4010897604
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/30.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_aborted_low_power.4011140745
Short name	T641
Test name
Test status
Simulation time	83263066 ps
CPU time	0.91 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	210172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011140745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.4011140745
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_disable_rom_integrity_check.514070878
Short name	T187
Test name
Test status
Simulation time	64538760 ps
CPU time	0.88 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514070878 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disable_rom_integrity_check.514070878
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2398172731
Short name	T640
Test name
Test status
Simulation time	31146564 ps
CPU time	0.78 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398172731 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_malfunc.2398172731
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_escalation_timeout.607763203
Short name	T646
Test name
Test status
Simulation time	398842457 ps
CPU time	0.84 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607763203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.607763203
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_glitch.2921776613
Short name	T645
Test name
Test status
Simulation time	27654942 ps
CPU time	0.72 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921776613 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.2921776613
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_global_esc.3791085435
Short name	T639
Test name
Test status
Simulation time	59145130 ps
CPU time	0.71 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791085435 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.3791085435
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_wakeup_race.3409785250
Short name	T649
Test name
Test status
Simulation time	248794517 ps
CPU time	1.33 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	209736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409785250 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_wakeup_race.3409785250
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset.412785929
Short name	T636
Test name
Test status
Simulation time	49179987 ps
CPU time	0.77 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	208640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412785929 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.412785929
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset_invalid.691775501
Short name	T647
Test name
Test status
Simulation time	158912123 ps
CPU time	0.82 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	220544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691775501 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.691775501
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.1600743430
Short name	T650
Test name
Test status
Simulation time	314263151 ps
CPU time	1.14 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	210060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600743430 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_ctrl_config_regwen.1600743430
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3814746606
Short name	T609
Test name
Test status
Simulation time	933066139 ps
CPU time	3.22 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:59 AM UTC 24
Peak memory	211444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814746606 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3814746606
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3879543630
Short name	T643
Test name
Test status
Simulation time	921754487 ps
CPU time	2.79 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:59 AM UTC 24
Peak memory	211544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879543630 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3879543630
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1246981617
Short name	T638
Test name
Test status
Simulation time	184834823 ps
CPU time	0.88 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	209476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246981617 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1246981617
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_smoke.2891930627
Short name	T633
Test name
Test status
Simulation time	33292762 ps
CPU time	0.65 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891930627 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.2891930627
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all.1263949341
Short name	T632
Test name
Test status
Simulation time	1675107722 ps
CPU time	5.91 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:45:02 AM UTC 24
Peak memory	211564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263949341 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.1263949341
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all_with_rand_reset.1657098576
Short name	T595
Test name
Test status
Simulation time	4605350190 ps
CPU time	7.51 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:45:04 AM UTC 24
Peak memory	211636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1657098576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmg r_stress_all_with_rand_reset.1657098576
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup.3971929395
Short name	T644
Test name
Test status
Simulation time	126921840 ps
CPU time	1.07 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	208976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971929395 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.3971929395
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup_reset.1372454449
Short name	T642
Test name
Test status
Simulation time	120254688 ps
CPU time	1.08 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372454449 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.1372454449
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/31.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.3915834936
Short name	T607
Test name
Test status
Simulation time	57005815 ps
CPU time	0.66 seconds
Started	Sep 24 08:44:56 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	208744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915834936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.3915834936
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.259966341
Short name	T663
Test name
Test status
Simulation time	51491177 ps
CPU time	0.96 seconds
Started	Sep 24 08:45:06 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	208648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259966341 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disable_rom_integrity_check.259966341
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.1907008139
Short name	T655
Test name
Test status
Simulation time	38864544 ps
CPU time	0.71 seconds
Started	Sep 24 08:45:06 AM UTC 24
Finished	Sep 24 08:45:08 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907008139 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_malfunc.1907008139
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_escalation_timeout.3316828212
Short name	T658
Test name
Test status
Simulation time	135428562 ps
CPU time	0.83 seconds
Started	Sep 24 08:45:06 AM UTC 24
Finished	Sep 24 08:45:08 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316828212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.3316828212
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_glitch.3655582213
Short name	T657
Test name
Test status
Simulation time	58092177 ps
CPU time	0.78 seconds
Started	Sep 24 08:45:06 AM UTC 24
Finished	Sep 24 08:45:08 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655582213 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.3655582213
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_global_esc.715100701
Short name	T654
Test name
Test status
Simulation time	40963167 ps
CPU time	0.64 seconds
Started	Sep 24 08:45:06 AM UTC 24
Finished	Sep 24 08:45:08 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715100701 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.715100701
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_wakeup_race.2492640148
Short name	T608
Test name
Test status
Simulation time	145679032 ps
CPU time	1.11 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:58 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492640148 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_wakeup_race.2492640148
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset.4289099638
Short name	T606
Test name
Test status
Simulation time	25072357 ps
CPU time	0.71 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	209016 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289099638 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.4289099638
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset_invalid.1456841702
Short name	T673
Test name
Test status
Simulation time	99088243 ps
CPU time	1.24 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	220304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456841702 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.1456841702
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.1020266237
Short name	T653
Test name
Test status
Simulation time	76272705 ps
CPU time	0.61 seconds
Started	Sep 24 08:45:06 AM UTC 24
Finished	Sep 24 08:45:08 AM UTC 24
Peak memory	208672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020266237 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_ctrl_config_regwen.1020266237
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1753017395
Short name	T687
Test name
Test status
Simulation time	860227251 ps
CPU time	3.12 seconds
Started	Sep 24 08:45:06 AM UTC 24
Finished	Sep 24 08:45:11 AM UTC 24
Peak memory	211480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753017395 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1753017395
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2318533211
Short name	T685
Test name
Test status
Simulation time	836930217 ps
CPU time	2.31 seconds
Started	Sep 24 08:45:06 AM UTC 24
Finished	Sep 24 08:45:10 AM UTC 24
Peak memory	211528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318533211 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2318533211
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3396321893
Short name	T656
Test name
Test status
Simulation time	54885780 ps
CPU time	0.99 seconds
Started	Sep 24 08:45:06 AM UTC 24
Finished	Sep 24 08:45:08 AM UTC 24
Peak memory	209152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396321893 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3396321893
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_smoke.3107905974
Short name	T648
Test name
Test status
Simulation time	54687012 ps
CPU time	0.66 seconds
Started	Sep 24 08:44:55 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	208680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107905974 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.3107905974
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all.3137912450
Short name	T661
Test name
Test status
Simulation time	65811008 ps
CPU time	0.83 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	209388 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137912450 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.3137912450
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.3526692057
Short name	T49
Test name
Test status
Simulation time	3273316194 ps
CPU time	12.59 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:20 AM UTC 24
Peak memory	211696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3526692057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmg r_stress_all_with_rand_reset.3526692057
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup.602874386
Short name	T651
Test name
Test status
Simulation time	125534661 ps
CPU time	0.92 seconds
Started	Sep 24 08:44:56 AM UTC 24
Finished	Sep 24 08:44:57 AM UTC 24
Peak memory	208792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602874386 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.602874386
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup_reset.1842190334
Short name	T652
Test name
Test status
Simulation time	260632054 ps
CPU time	1.32 seconds
Started	Sep 24 08:44:56 AM UTC 24
Finished	Sep 24 08:44:58 AM UTC 24
Peak memory	210648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842190334 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.1842190334
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/32.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_aborted_low_power.2275672553
Short name	T669
Test name
Test status
Simulation time	22077870 ps
CPU time	0.85 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	209000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275672553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.2275672553
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.2780853416
Short name	T679
Test name
Test status
Simulation time	59953341 ps
CPU time	1 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	208500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780853416 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_disable_rom_integrity_check.2780853416
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.54294374
Short name	T668
Test name
Test status
Simulation time	38917431 ps
CPU time	0.63 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54294374 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst_malfunc.54294374
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_escalation_timeout.1360503232
Short name	T683
Test name
Test status
Simulation time	112820419 ps
CPU time	1.15 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360503232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.1360503232
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_glitch.1350441262
Short name	T674
Test name
Test status
Simulation time	74764268 ps
CPU time	0.77 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	208144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350441262 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.1350441262
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_global_esc.2739534135
Short name	T672
Test name
Test status
Simulation time	58316104 ps
CPU time	0.77 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739534135 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.2739534135
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_wakeup_race.3577028619
Short name	T671
Test name
Test status
Simulation time	124789644 ps
CPU time	0.92 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	208860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577028619 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wakeup_race.3577028619
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset.2363313516
Short name	T666
Test name
Test status
Simulation time	90478123 ps
CPU time	0.82 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363313516 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.2363313516
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.3322587989
Short name	T681
Test name
Test status
Simulation time	120564103 ps
CPU time	1 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	220304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322587989 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.3322587989
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.852770493
Short name	T680
Test name
Test status
Simulation time	114169440 ps
CPU time	1.04 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	210000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852770493 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_ctrl_config_regwen.852770493
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.468446479
Short name	T686
Test name
Test status
Simulation time	1009911371 ps
CPU time	2.39 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:10 AM UTC 24
Peak memory	211688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468446479 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.468446479
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2441954992
Short name	T688
Test name
Test status
Simulation time	755426710 ps
CPU time	3.28 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:11 AM UTC 24
Peak memory	211324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441954992 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2441954992
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.1866480420
Short name	T677
Test name
Test status
Simulation time	73820024 ps
CPU time	1.02 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	209512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866480420 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_mubi.1866480420
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_smoke.941545568
Short name	T664
Test name
Test status
Simulation time	31398444 ps
CPU time	0.77 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	208316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941545568 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.941545568
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all.1467823005
Short name	T682
Test name
Test status
Simulation time	103207656 ps
CPU time	0.89 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	208740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467823005 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.1467823005
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all_with_rand_reset.4117131710
Short name	T148
Test name
Test status
Simulation time	2939441397 ps
CPU time	8.7 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:17 AM UTC 24
Peak memory	211696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4117131710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmg r_stress_all_with_rand_reset.4117131710
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup.292023265
Short name	T676
Test name
Test status
Simulation time	446050420 ps
CPU time	1.09 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	209448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292023265 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.292023265
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup_reset.650336696
Short name	T667
Test name
Test status
Simulation time	91335495 ps
CPU time	0.86 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	208824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650336696 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.650336696
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/33.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_aborted_low_power.1099529085
Short name	T695
Test name
Test status
Simulation time	75844760 ps
CPU time	0.89 seconds
Started	Sep 24 08:45:18 AM UTC 24
Finished	Sep 24 08:45:20 AM UTC 24
Peak memory	210268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099529085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.1099529085
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_disable_rom_integrity_check.142285963
Short name	T703
Test name
Test status
Simulation time	65215608 ps
CPU time	0.94 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	208608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142285963 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disable_rom_integrity_check.142285963
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.1812934319
Short name	T692
Test name
Test status
Simulation time	77412496 ps
CPU time	0.59 seconds
Started	Sep 24 08:45:18 AM UTC 24
Finished	Sep 24 08:45:20 AM UTC 24
Peak memory	208828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812934319 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_malfunc.1812934319
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_escalation_timeout.1639199223
Short name	T699
Test name
Test status
Simulation time	113289952 ps
CPU time	0.85 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639199223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.1639199223
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_glitch.1421158900
Short name	T694
Test name
Test status
Simulation time	66996537 ps
CPU time	0.58 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:20 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421158900 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.1421158900
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_global_esc.1464717648
Short name	T696
Test name
Test status
Simulation time	42209030 ps
CPU time	0.62 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:20 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464717648 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.1464717648
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_wakeup_race.2947257375
Short name	T693
Test name
Test status
Simulation time	257233781 ps
CPU time	0.96 seconds
Started	Sep 24 08:45:18 AM UTC 24
Finished	Sep 24 08:45:20 AM UTC 24
Peak memory	209420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947257375 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_wakeup_race.2947257375
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset.3698730690
Short name	T684
Test name
Test status
Simulation time	66698917 ps
CPU time	1.05 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:10 AM UTC 24
Peak memory	210528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698730690 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.3698730690
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset_invalid.2006441934
Short name	T706
Test name
Test status
Simulation time	139851067 ps
CPU time	1.05 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	220364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006441934 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.2006441934
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.2292612326
Short name	T702
Test name
Test status
Simulation time	135663758 ps
CPU time	1.04 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	209112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292612326 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_ctrl_config_regwen.2292612326
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2013753044
Short name	T659
Test name
Test status
Simulation time	902562738 ps
CPU time	2.08 seconds
Started	Sep 24 08:45:18 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	211704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013753044 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2013753044
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.998738960
Short name	T660
Test name
Test status
Simulation time	901560896 ps
CPU time	2.36 seconds
Started	Sep 24 08:45:18 AM UTC 24
Finished	Sep 24 08:45:22 AM UTC 24
Peak memory	211532 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998738960 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.998738960
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.3501007050
Short name	T697
Test name
Test status
Simulation time	180554696 ps
CPU time	0.94 seconds
Started	Sep 24 08:45:18 AM UTC 24
Finished	Sep 24 08:45:20 AM UTC 24
Peak memory	209152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501007050 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_mubi.3501007050
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_smoke.1832838065
Short name	T678
Test name
Test status
Simulation time	52724035 ps
CPU time	0.78 seconds
Started	Sep 24 08:45:07 AM UTC 24
Finished	Sep 24 08:45:09 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832838065 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.1832838065
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all.1587836579
Short name	T665
Test name
Test status
Simulation time	2962442823 ps
CPU time	4.57 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:25 AM UTC 24
Peak memory	211496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587836579 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.1587836579
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all_with_rand_reset.295691044
Short name	T95
Test name
Test status
Simulation time	4504748113 ps
CPU time	7.74 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:28 AM UTC 24
Peak memory	211684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=295691044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr _stress_all_with_rand_reset.295691044
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup.4267052620
Short name	T690
Test name
Test status
Simulation time	397235447 ps
CPU time	0.77 seconds
Started	Sep 24 08:45:18 AM UTC 24
Finished	Sep 24 08:45:20 AM UTC 24
Peak memory	209036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267052620 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.4267052620
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup_reset.2814606382
Short name	T698
Test name
Test status
Simulation time	446509916 ps
CPU time	1.25 seconds
Started	Sep 24 08:45:18 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	210504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814606382 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.2814606382
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/34.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_aborted_low_power.1913621684
Short name	T714
Test name
Test status
Simulation time	103690782 ps
CPU time	0.93 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	210408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913621684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.1913621684
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_disable_rom_integrity_check.2671404060
Short name	T712
Test name
Test status
Simulation time	122263176 ps
CPU time	0.66 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	208560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671404060 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disable_rom_integrity_check.2671404060
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.1110480831
Short name	T709
Test name
Test status
Simulation time	31799824 ps
CPU time	0.63 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110480831 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_malfunc.1110480831
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_escalation_timeout.3090863181
Short name	T717
Test name
Test status
Simulation time	229032014 ps
CPU time	0.9 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	208820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090863181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.3090863181
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_glitch.176184539
Short name	T713
Test name
Test status
Simulation time	45189811 ps
CPU time	0.68 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	208200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176184539 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.176184539
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_global_esc.1390389291
Short name	T711
Test name
Test status
Simulation time	37061159 ps
CPU time	0.65 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390389291 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.1390389291
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_wakeup_race.3655587980
Short name	T719
Test name
Test status
Simulation time	331666546 ps
CPU time	1.55 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:22 AM UTC 24
Peak memory	209740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655587980 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_wakeup_race.3655587980
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset.2585711166
Short name	T710
Test name
Test status
Simulation time	179131457 ps
CPU time	0.91 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	209584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585711166 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.2585711166
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset_invalid.3058984667
Short name	T718
Test name
Test status
Simulation time	107045422 ps
CPU time	0.97 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	219952 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058984667 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.3058984667
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.2296993663
Short name	T715
Test name
Test status
Simulation time	63079255 ps
CPU time	0.87 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296993663 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_ctrl_config_regwen.2296993663
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3007243630
Short name	T720
Test name
Test status
Simulation time	866639733 ps
CPU time	2.98 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:23 AM UTC 24
Peak memory	211568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007243630 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3007243630
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.183730436
Short name	T662
Test name
Test status
Simulation time	801585380 ps
CPU time	3.53 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:24 AM UTC 24
Peak memory	211512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183730436 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.183730436
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.1612969875
Short name	T716
Test name
Test status
Simulation time	72246654 ps
CPU time	1.01 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	209628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612969875 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_mubi.1612969875
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_smoke.1294740644
Short name	T701
Test name
Test status
Simulation time	32718694 ps
CPU time	0.75 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	208720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294740644 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.1294740644
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all.1169349152
Short name	T747
Test name
Test status
Simulation time	1363202925 ps
CPU time	5.03 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:38 AM UTC 24
Peak memory	211480 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169349152 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.1169349152
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all_with_rand_reset.159520909
Short name	T149
Test name
Test status
Simulation time	2600078540 ps
CPU time	4.82 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:38 AM UTC 24
Peak memory	211696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=159520909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr _stress_all_with_rand_reset.159520909
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup.2241649813
Short name	T704
Test name
Test status
Simulation time	38431993 ps
CPU time	0.66 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	208976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241649813 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.2241649813
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup_reset.564339559
Short name	T708
Test name
Test status
Simulation time	33878954 ps
CPU time	0.78 seconds
Started	Sep 24 08:45:19 AM UTC 24
Finished	Sep 24 08:45:21 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564339559 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.564339559
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/35.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_aborted_low_power.2378038830
Short name	T700
Test name
Test status
Simulation time	116496432 ps
CPU time	0.84 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:34 AM UTC 24
Peak memory	210484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378038830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.2378038830
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_disable_rom_integrity_check.3981244346
Short name	T724
Test name
Test status
Simulation time	57568969 ps
CPU time	0.82 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:34 AM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981244346 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_disable_rom_integrity_check.3981244346
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.4200155691
Short name	T590
Test name
Test status
Simulation time	39140264 ps
CPU time	0.66 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:34 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200155691 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_malfunc.4200155691
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_escalation_timeout.3049348177
Short name	T725
Test name
Test status
Simulation time	113579852 ps
CPU time	0.91 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	208448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049348177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.3049348177
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_glitch.1567979956
Short name	T722
Test name
Test status
Simulation time	46232114 ps
CPU time	0.72 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:34 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567979956 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.1567979956
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_global_esc.3253627430
Short name	T689
Test name
Test status
Simulation time	27064564 ps
CPU time	0.75 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:34 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253627430 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.3253627430
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_wakeup_race.1362438648
Short name	T705
Test name
Test status
Simulation time	70651237 ps
CPU time	0.7 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:34 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362438648 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_wakeup_race.1362438648
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset.1169351688
Short name	T675
Test name
Test status
Simulation time	85456533 ps
CPU time	0.9 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:34 AM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169351688 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.1169351688
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset_invalid.111313912
Short name	T728
Test name
Test status
Simulation time	161511413 ps
CPU time	0.89 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	220664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111313912 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.111313912
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.2706867598
Short name	T732
Test name
Test status
Simulation time	181774733 ps
CPU time	1.16 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	209736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706867598 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_ctrl_config_regwen.2706867598
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2705893740
Short name	T743
Test name
Test status
Simulation time	796692280 ps
CPU time	3.31 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:37 AM UTC 24
Peak memory	211500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705893740 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2705893740
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4269421420
Short name	T742
Test name
Test status
Simulation time	1366329553 ps
CPU time	2.28 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:36 AM UTC 24
Peak memory	211508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269421420 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.4269421420
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1212544144
Short name	T721
Test name
Test status
Simulation time	89496443 ps
CPU time	0.93 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:34 AM UTC 24
Peak memory	209536 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212544144 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1212544144
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_smoke.2409391118
Short name	T670
Test name
Test status
Simulation time	73172643 ps
CPU time	0.77 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:34 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409391118 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.2409391118
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all.1820499030
Short name	T746
Test name
Test status
Simulation time	2890325109 ps
CPU time	4.35 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:38 AM UTC 24
Peak memory	211740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820499030 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.1820499030
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.2727629334
Short name	T782
Test name
Test status
Simulation time	6117665046 ps
CPU time	20.28 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:54 AM UTC 24
Peak memory	211816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2727629334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmg r_stress_all_with_rand_reset.2727629334
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup.2639009937
Short name	T707
Test name
Test status
Simulation time	446793084 ps
CPU time	0.92 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:34 AM UTC 24
Peak memory	209468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639009937 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.2639009937
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup_reset.2020762599
Short name	T727
Test name
Test status
Simulation time	168124552 ps
CPU time	1.28 seconds
Started	Sep 24 08:45:32 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	210680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020762599 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.2020762599
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/36.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_aborted_low_power.393003990
Short name	T738
Test name
Test status
Simulation time	27943830 ps
CPU time	0.95 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	210292 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393003990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.393003990
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_disable_rom_integrity_check.1164873102
Short name	T749
Test name
Test status
Simulation time	52997964 ps
CPU time	0.8 seconds
Started	Sep 24 08:45:45 AM UTC 24
Finished	Sep 24 08:45:47 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164873102 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disable_rom_integrity_check.1164873102
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.544610797
Short name	T734
Test name
Test status
Simulation time	31387385 ps
CPU time	0.69 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544610797 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_malfunc.544610797
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_escalation_timeout.2470633793
Short name	T741
Test name
Test status
Simulation time	111459031 ps
CPU time	0.92 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470633793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.2470633793
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_glitch.791737009
Short name	T737
Test name
Test status
Simulation time	23645852 ps
CPU time	0.62 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	208680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791737009 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.791737009
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_global_esc.3399657842
Short name	T735
Test name
Test status
Simulation time	60619371 ps
CPU time	0.57 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399657842 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.3399657842
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_wakeup_race.3644095818
Short name	T729
Test name
Test status
Simulation time	58335261 ps
CPU time	0.76 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644095818 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_wakeup_race.3644095818
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset.4034459884
Short name	T731
Test name
Test status
Simulation time	213923761 ps
CPU time	0.86 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	209940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034459884 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.4034459884
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset_invalid.3520829796
Short name	T751
Test name
Test status
Simulation time	117086278 ps
CPU time	0.87 seconds
Started	Sep 24 08:45:45 AM UTC 24
Finished	Sep 24 08:45:47 AM UTC 24
Peak memory	220364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520829796 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.3520829796
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.3111030598
Short name	T740
Test name
Test status
Simulation time	83757297 ps
CPU time	0.91 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	208320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111030598 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_ctrl_config_regwen.3111030598
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1083565886
Short name	T745
Test name
Test status
Simulation time	844829589 ps
CPU time	2.97 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:37 AM UTC 24
Peak memory	211564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083565886 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1083565886
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3349662080
Short name	T744
Test name
Test status
Simulation time	824725551 ps
CPU time	2.58 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:37 AM UTC 24
Peak memory	211452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349662080 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3349662080
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.3795600293
Short name	T739
Test name
Test status
Simulation time	76953182 ps
CPU time	1.01 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	209632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795600293 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_mubi.3795600293
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_smoke.2935977207
Short name	T733
Test name
Test status
Simulation time	38880062 ps
CPU time	0.86 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935977207 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.2935977207
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all.1421132144
Short name	T763
Test name
Test status
Simulation time	567799371 ps
CPU time	1.41 seconds
Started	Sep 24 08:45:45 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	210336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421132144 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.1421132144
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.3807174199
Short name	T783
Test name
Test status
Simulation time	2159415393 ps
CPU time	8.47 seconds
Started	Sep 24 08:45:45 AM UTC 24
Finished	Sep 24 08:45:55 AM UTC 24
Peak memory	211764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3807174199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmg r_stress_all_with_rand_reset.3807174199
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup.1208960946
Short name	T736
Test name
Test status
Simulation time	153042307 ps
CPU time	0.9 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	209036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208960946 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.1208960946
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup_reset.1275525558
Short name	T730
Test name
Test status
Simulation time	60985920 ps
CPU time	0.67 seconds
Started	Sep 24 08:45:33 AM UTC 24
Finished	Sep 24 08:45:35 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275525558 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.1275525558
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/37.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_aborted_low_power.2104209391
Short name	T758
Test name
Test status
Simulation time	26213195 ps
CPU time	1 seconds
Started	Sep 24 08:45:45 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	210728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104209391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.2104209391
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_disable_rom_integrity_check.3942219661
Short name	T762
Test name
Test status
Simulation time	58531632 ps
CPU time	0.77 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942219661 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disable_rom_integrity_check.3942219661
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.555315356
Short name	T755
Test name
Test status
Simulation time	30821694 ps
CPU time	0.73 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:47 AM UTC 24
Peak memory	208908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555315356 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst_malfunc.555315356
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_escalation_timeout.1605635224
Short name	T766
Test name
Test status
Simulation time	199424305 ps
CPU time	0.94 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605635224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.1605635224
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_glitch.2738580881
Short name	T760
Test name
Test status
Simulation time	39171102 ps
CPU time	0.8 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738580881 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.2738580881
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_global_esc.4161588147
Short name	T753
Test name
Test status
Simulation time	104028533 ps
CPU time	0.65 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:47 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161588147 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.4161588147
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_wakeup_race.186458833
Short name	T754
Test name
Test status
Simulation time	352470080 ps
CPU time	0.87 seconds
Started	Sep 24 08:45:45 AM UTC 24
Finished	Sep 24 08:45:47 AM UTC 24
Peak memory	208792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186458833 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_wakeup_race.186458833
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset.2818118303
Short name	T750
Test name
Test status
Simulation time	48035215 ps
CPU time	0.61 seconds
Started	Sep 24 08:45:45 AM UTC 24
Finished	Sep 24 08:45:47 AM UTC 24
Peak memory	208380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818118303 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.2818118303
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset_invalid.3985704335
Short name	T770
Test name
Test status
Simulation time	91122448 ps
CPU time	0.97 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	220304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985704335 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.3985704335
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.3115103001
Short name	T768
Test name
Test status
Simulation time	192957952 ps
CPU time	1.25 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	210168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115103001 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_ctrl_config_regwen.3115103001
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1500851518
Short name	T777
Test name
Test status
Simulation time	1084067256 ps
CPU time	2.27 seconds
Started	Sep 24 08:45:45 AM UTC 24
Finished	Sep 24 08:45:49 AM UTC 24
Peak memory	211420 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500851518 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1500851518
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.862548738
Short name	T780
Test name
Test status
Simulation time	887684771 ps
CPU time	3.17 seconds
Started	Sep 24 08:45:45 AM UTC 24
Finished	Sep 24 08:45:50 AM UTC 24
Peak memory	211500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862548738 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.862548738
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3689556923
Short name	T756
Test name
Test status
Simulation time	69610152 ps
CPU time	0.92 seconds
Started	Sep 24 08:45:45 AM UTC 24
Finished	Sep 24 08:45:47 AM UTC 24
Peak memory	209596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689556923 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3689556923
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_smoke.3087672635
Short name	T752
Test name
Test status
Simulation time	32556150 ps
CPU time	0.74 seconds
Started	Sep 24 08:45:45 AM UTC 24
Finished	Sep 24 08:45:47 AM UTC 24
Peak memory	208500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087672635 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.3087672635
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.4262636710
Short name	T779
Test name
Test status
Simulation time	3034785490 ps
CPU time	2.45 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:50 AM UTC 24
Peak memory	211664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262636710 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.4262636710
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.2193950289
Short name	T784
Test name
Test status
Simulation time	2165012869 ps
CPU time	8.29 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:55 AM UTC 24
Peak memory	211564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2193950289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmg r_stress_all_with_rand_reset.2193950289
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup.3607251003
Short name	T757
Test name
Test status
Simulation time	166612319 ps
CPU time	0.94 seconds
Started	Sep 24 08:45:45 AM UTC 24
Finished	Sep 24 08:45:47 AM UTC 24
Peak memory	209036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607251003 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.3607251003
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup_reset.3151674901
Short name	T761
Test name
Test status
Simulation time	308584996 ps
CPU time	1.1 seconds
Started	Sep 24 08:45:45 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	209916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151674901 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.3151674901
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/38.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_aborted_low_power.3875558684
Short name	T769
Test name
Test status
Simulation time	22220689 ps
CPU time	0.75 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	208744 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875558684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.3875558684
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_disable_rom_integrity_check.1895793839
Short name	T186
Test name
Test status
Simulation time	63741281 ps
CPU time	0.73 seconds
Started	Sep 24 08:45:59 AM UTC 24
Finished	Sep 24 08:46:01 AM UTC 24
Peak memory	208392 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895793839 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disable_rom_integrity_check.1895793839
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.725878365
Short name	T771
Test name
Test status
Simulation time	39626931 ps
CPU time	0.7 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725878365 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_malfunc.725878365
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_escalation_timeout.2963662912
Short name	T788
Test name
Test status
Simulation time	119032047 ps
CPU time	0.91 seconds
Started	Sep 24 08:45:59 AM UTC 24
Finished	Sep 24 08:46:01 AM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963662912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.2963662912
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_glitch.108744743
Short name	T785
Test name
Test status
Simulation time	23328609 ps
CPU time	0.6 seconds
Started	Sep 24 08:45:59 AM UTC 24
Finished	Sep 24 08:46:01 AM UTC 24
Peak memory	208484 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108744743 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.108744743
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_global_esc.3481704349
Short name	T786
Test name
Test status
Simulation time	41911773 ps
CPU time	0.63 seconds
Started	Sep 24 08:45:59 AM UTC 24
Finished	Sep 24 08:46:01 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481704349 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.3481704349
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_wakeup_race.2834833387
Short name	T774
Test name
Test status
Simulation time	397850518 ps
CPU time	0.99 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834833387 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_wakeup_race.2834833387
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset.1960753395
Short name	T776
Test name
Test status
Simulation time	84224684 ps
CPU time	1.24 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	210468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960753395 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.1960753395
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.3725378343
Short name	T790
Test name
Test status
Simulation time	124514844 ps
CPU time	0.87 seconds
Started	Sep 24 08:45:59 AM UTC 24
Finished	Sep 24 08:46:01 AM UTC 24
Peak memory	210136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725378343 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.3725378343
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.482497634
Short name	T765
Test name
Test status
Simulation time	298971630 ps
CPU time	1.22 seconds
Started	Sep 24 08:45:59 AM UTC 24
Finished	Sep 24 08:46:01 AM UTC 24
Peak memory	210748 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482497634 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_ctrl_config_regwen.482497634
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1369421760
Short name	T778
Test name
Test status
Simulation time	991228646 ps
CPU time	2.09 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:49 AM UTC 24
Peak memory	211496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369421760 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1369421760
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.814332928
Short name	T781
Test name
Test status
Simulation time	902307201 ps
CPU time	2.48 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:50 AM UTC 24
Peak memory	211512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814332928 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.814332928
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.981955424
Short name	T775
Test name
Test status
Simulation time	88901919 ps
CPU time	0.97 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	209796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981955424 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_mubi.981955424
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.551202260
Short name	T767
Test name
Test status
Simulation time	89494973 ps
CPU time	0.64 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	208820 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551202260 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.551202260
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.4043033478
Short name	T808
Test name
Test status
Simulation time	1689145740 ps
CPU time	4.46 seconds
Started	Sep 24 08:45:59 AM UTC 24
Finished	Sep 24 08:46:05 AM UTC 24
Peak memory	211604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043033478 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.4043033478
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all_with_rand_reset.3876396657
Short name	T810
Test name
Test status
Simulation time	17461342715 ps
CPU time	14.34 seconds
Started	Sep 24 08:45:59 AM UTC 24
Finished	Sep 24 08:46:15 AM UTC 24
Peak memory	211628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3876396657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmg r_stress_all_with_rand_reset.3876396657
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.1891738902
Short name	T772
Test name
Test status
Simulation time	312380686 ps
CPU time	0.97 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	210084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891738902 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.1891738902
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup_reset.4083809726
Short name	T773
Test name
Test status
Simulation time	211310482 ps
CPU time	0.89 seconds
Started	Sep 24 08:45:46 AM UTC 24
Finished	Sep 24 08:45:48 AM UTC 24
Peak memory	208740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083809726 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.4083809726
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/39.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.4053530682
Short name	T129
Test name
Test status
Simulation time	23667181 ps
CPU time	1.3 seconds
Started	Sep 24 08:42:26 AM UTC 24
Finished	Sep 24 08:42:29 AM UTC 24
Peak memory	210384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053530682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.4053530682
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.686698982
Short name	T159
Test name
Test status
Simulation time	65080749 ps
CPU time	1.39 seconds
Started	Sep 24 08:42:28 AM UTC 24
Finished	Sep 24 08:42:31 AM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686698982 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disable_rom_integrity_check.686698982
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.3615163602
Short name	T133
Test name
Test status
Simulation time	32178077 ps
CPU time	0.84 seconds
Started	Sep 24 08:42:27 AM UTC 24
Finished	Sep 24 08:42:29 AM UTC 24
Peak memory	208864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615163602 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_malfunc.3615163602
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.3394917815
Short name	T139
Test name
Test status
Simulation time	407064309 ps
CPU time	1.4 seconds
Started	Sep 24 08:42:28 AM UTC 24
Finished	Sep 24 08:42:31 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394917815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.3394917815
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.1747495060
Short name	T136
Test name
Test status
Simulation time	51145742 ps
CPU time	0.85 seconds
Started	Sep 24 08:42:28 AM UTC 24
Finished	Sep 24 08:42:30 AM UTC 24
Peak memory	208676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747495060 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.1747495060
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.261181554
Short name	T137
Test name
Test status
Simulation time	33445321 ps
CPU time	1.01 seconds
Started	Sep 24 08:42:28 AM UTC 24
Finished	Sep 24 08:42:30 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261181554 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.261181554
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.2898404807
Short name	T207
Test name
Test status
Simulation time	137309420 ps
CPU time	1.18 seconds
Started	Sep 24 08:42:25 AM UTC 24
Finished	Sep 24 08:42:27 AM UTC 24
Peak memory	208320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898404807 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wakeup_race.2898404807
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.6651602
Short name	T205
Test name
Test status
Simulation time	40925338 ps
CPU time	1.13 seconds
Started	Sep 24 08:42:25 AM UTC 24
Finished	Sep 24 08:42:27 AM UTC 24
Peak memory	208824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6651602 -assert nopostproc +UVM_TESTNAME=pwrmgr_ base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.6651602
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.842401105
Short name	T208
Test name
Test status
Simulation time	120477135 ps
CPU time	1.38 seconds
Started	Sep 24 08:42:28 AM UTC 24
Finished	Sep 24 08:42:31 AM UTC 24
Peak memory	210244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842401105 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.842401105
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.4052597722
Short name	T30
Test name
Test status
Simulation time	661842034 ps
CPU time	3.24 seconds
Started	Sep 24 08:42:29 AM UTC 24
Finished	Sep 24 08:42:33 AM UTC 24
Peak memory	239564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052597722 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.4052597722
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.1796417234
Short name	T209
Test name
Test status
Simulation time	427868283 ps
CPU time	1.72 seconds
Started	Sep 24 08:42:28 AM UTC 24
Finished	Sep 24 08:42:31 AM UTC 24
Peak memory	210292 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796417234 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_ctrl_config_regwen.1796417234
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3377736417
Short name	T164
Test name
Test status
Simulation time	1029290845 ps
CPU time	3.93 seconds
Started	Sep 24 08:42:27 AM UTC 24
Finished	Sep 24 08:42:31 AM UTC 24
Peak memory	211516 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377736417 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.3377736417
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1524177654
Short name	T160
Test name
Test status
Simulation time	1221466434 ps
CPU time	3.52 seconds
Started	Sep 24 08:42:27 AM UTC 24
Finished	Sep 24 08:42:31 AM UTC 24
Peak memory	211468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524177654 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.1524177654
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.128380272
Short name	T135
Test name
Test status
Simulation time	187609867 ps
CPU time	1.31 seconds
Started	Sep 24 08:42:27 AM UTC 24
Finished	Sep 24 08:42:29 AM UTC 24
Peak memory	209772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128380272 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_mubi.128380272
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.2127765384
Short name	T203
Test name
Test status
Simulation time	134119960 ps
CPU time	0.92 seconds
Started	Sep 24 08:42:25 AM UTC 24
Finished	Sep 24 08:42:27 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127765384 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.2127765384
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.1204161835
Short name	T212
Test name
Test status
Simulation time	133130298 ps
CPU time	1.27 seconds
Started	Sep 24 08:42:30 AM UTC 24
Finished	Sep 24 08:42:32 AM UTC 24
Peak memory	210300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204161835 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.1204161835
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.1145521186
Short name	T130
Test name
Test status
Simulation time	2725740957 ps
CPU time	12.17 seconds
Started	Sep 24 08:42:29 AM UTC 24
Finished	Sep 24 08:42:42 AM UTC 24
Peak memory	211628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1145521186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr _stress_all_with_rand_reset.1145521186
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.2902783596
Short name	T206
Test name
Test status
Simulation time	154472743 ps
CPU time	1.17 seconds
Started	Sep 24 08:42:25 AM UTC 24
Finished	Sep 24 08:42:27 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902783596 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.2902783596
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.3625222762
Short name	T134
Test name
Test status
Simulation time	342124648 ps
CPU time	1.32 seconds
Started	Sep 24 08:42:26 AM UTC 24
Finished	Sep 24 08:42:29 AM UTC 24
Peak memory	210180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625222762 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.3625222762
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/4.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.721698125
Short name	T748
Test name
Test status
Simulation time	36784893 ps
CPU time	0.85 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	208948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721698125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.721698125
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.3936493632
Short name	T794
Test name
Test status
Simulation time	94264568 ps
CPU time	0.7 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936493632 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disable_rom_integrity_check.3936493632
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.2757418288
Short name	T723
Test name
Test status
Simulation time	39428242 ps
CPU time	0.65 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757418288 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_malfunc.2757418288
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.23280121
Short name	T796
Test name
Test status
Simulation time	114484401 ps
CPU time	0.92 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23280121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ= pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.23280121
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.2010383390
Short name	T793
Test name
Test status
Simulation time	83420271 ps
CPU time	0.72 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	208724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010383390 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.2010383390
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.4127910090
Short name	T726
Test name
Test status
Simulation time	181628796 ps
CPU time	0.61 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127910090 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.4127910090
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.4136551910
Short name	T787
Test name
Test status
Simulation time	176686412 ps
CPU time	0.72 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:01 AM UTC 24
Peak memory	208848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136551910 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_wakeup_race.4136551910
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.1296702605
Short name	T764
Test name
Test status
Simulation time	77638132 ps
CPU time	0.88 seconds
Started	Sep 24 08:45:59 AM UTC 24
Finished	Sep 24 08:46:01 AM UTC 24
Peak memory	208284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296702605 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.1296702605
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.2312011571
Short name	T797
Test name
Test status
Simulation time	579776376 ps
CPU time	0.82 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	220604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312011571 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.2312011571
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.1835553818
Short name	T792
Test name
Test status
Simulation time	425862727 ps
CPU time	0.85 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	210120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835553818 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_ctrl_config_regwen.1835553818
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.325992721
Short name	T804
Test name
Test status
Simulation time	940122841 ps
CPU time	2.05 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:03 AM UTC 24
Peak memory	211628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325992721 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.325992721
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4189421891
Short name	T805
Test name
Test status
Simulation time	864209460 ps
CPU time	2.35 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:03 AM UTC 24
Peak memory	211508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189421891 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.4189421891
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2020965540
Short name	T798
Test name
Test status
Simulation time	67980810 ps
CPU time	1 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	209776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020965540 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2020965540
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.403376542
Short name	T789
Test name
Test status
Simulation time	31679382 ps
CPU time	0.69 seconds
Started	Sep 24 08:45:59 AM UTC 24
Finished	Sep 24 08:46:01 AM UTC 24
Peak memory	208808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403376542 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.403376542
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.824158796
Short name	T806
Test name
Test status
Simulation time	1115219031 ps
CPU time	2.54 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:04 AM UTC 24
Peak memory	211372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824158796 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.824158796
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.241987467
Short name	T809
Test name
Test status
Simulation time	4981129135 ps
CPU time	5.18 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:06 AM UTC 24
Peak memory	211628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=241987467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr _stress_all_with_rand_reset.241987467
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.896661193
Short name	T791
Test name
Test status
Simulation time	54180101 ps
CPU time	0.79 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:01 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896661193 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.896661193
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.4231727035
Short name	T759
Test name
Test status
Simulation time	90733032 ps
CPU time	0.92 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	208824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231727035 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.4231727035
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/40.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.1719235453
Short name	T800
Test name
Test status
Simulation time	24538031 ps
CPU time	0.8 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	210268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719235453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.1719235453
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.3749748260
Short name	T815
Test name
Test status
Simulation time	59218502 ps
CPU time	0.81 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:16 AM UTC 24
Peak memory	208856 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749748260 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disable_rom_integrity_check.3749748260
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.953677535
Short name	T812
Test name
Test status
Simulation time	29060479 ps
CPU time	0.62 seconds
Started	Sep 24 08:46:14 AM UTC 24
Finished	Sep 24 08:46:16 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953677535 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_malfunc.953677535
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.2864634022
Short name	T817
Test name
Test status
Simulation time	116041522 ps
CPU time	0.98 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864634022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.2864634022
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.3045069346
Short name	T814
Test name
Test status
Simulation time	61336864 ps
CPU time	0.69 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:16 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045069346 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.3045069346
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.1841918033
Short name	T811
Test name
Test status
Simulation time	43939259 ps
CPU time	0.57 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:16 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841918033 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.1841918033
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.3088444640
Short name	T802
Test name
Test status
Simulation time	315123013 ps
CPU time	1.01 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088444640 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_wakeup_race.3088444640
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.363705243
Short name	T801
Test name
Test status
Simulation time	67301778 ps
CPU time	0.97 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	210464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363705243 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.363705243
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.322508746
Short name	T825
Test name
Test status
Simulation time	98368316 ps
CPU time	1.11 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	220268 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322508746 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.322508746
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.4031679903
Short name	T820
Test name
Test status
Simulation time	172486849 ps
CPU time	1.05 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	210060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031679903 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_ctrl_config_regwen.4031679903
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.389904387
Short name	T807
Test name
Test status
Simulation time	826838073 ps
CPU time	3.02 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:05 AM UTC 24
Peak memory	211512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389904387 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.389904387
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3040346547
Short name	T840
Test name
Test status
Simulation time	909607679 ps
CPU time	3.41 seconds
Started	Sep 24 08:46:14 AM UTC 24
Finished	Sep 24 08:46:19 AM UTC 24
Peak memory	211432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040346547 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3040346547
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3667747622
Short name	T813
Test name
Test status
Simulation time	95834074 ps
CPU time	0.81 seconds
Started	Sep 24 08:46:14 AM UTC 24
Finished	Sep 24 08:46:16 AM UTC 24
Peak memory	209448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667747622 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3667747622
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.582791935
Short name	T795
Test name
Test status
Simulation time	69555272 ps
CPU time	0.65 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582791935 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.582791935
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.4158409263
Short name	T839
Test name
Test status
Simulation time	1779115699 ps
CPU time	2.96 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:19 AM UTC 24
Peak memory	211608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158409263 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.4158409263
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.1052942306
Short name	T82
Test name
Test status
Simulation time	2311615665 ps
CPU time	7.13 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:23 AM UTC 24
Peak memory	211764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1052942306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmg r_stress_all_with_rand_reset.1052942306
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.47705559
Short name	T799
Test name
Test status
Simulation time	531415700 ps
CPU time	0.88 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	208792 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47705559 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.47705559
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.857126926
Short name	T803
Test name
Test status
Simulation time	355564867 ps
CPU time	1.07 seconds
Started	Sep 24 08:46:00 AM UTC 24
Finished	Sep 24 08:46:02 AM UTC 24
Peak memory	210408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857126926 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.857126926
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/41.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.3246136736
Short name	T828
Test name
Test status
Simulation time	31773002 ps
CPU time	1.11 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	210508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246136736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.3246136736
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.2452324124
Short name	T188
Test name
Test status
Simulation time	64505571 ps
CPU time	0.98 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452324124 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disable_rom_integrity_check.2452324124
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.669335182
Short name	T824
Test name
Test status
Simulation time	44718976 ps
CPU time	0.63 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669335182 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_malfunc.669335182
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.1998799750
Short name	T829
Test name
Test status
Simulation time	400016228 ps
CPU time	0.89 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998799750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.1998799750
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.1514324917
Short name	T830
Test name
Test status
Simulation time	54496030 ps
CPU time	0.78 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514324917 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.1514324917
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.2002781613
Short name	T826
Test name
Test status
Simulation time	38164718 ps
CPU time	0.67 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002781613 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.2002781613
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.265392783
Short name	T822
Test name
Test status
Simulation time	32514594 ps
CPU time	0.65 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265392783 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wakeup_race.265392783
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.3809429373
Short name	T821
Test name
Test status
Simulation time	64053644 ps
CPU time	0.8 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	208380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809429373 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.3809429373
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.3282018053
Short name	T833
Test name
Test status
Simulation time	109770860 ps
CPU time	0.97 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	220368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282018053 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.3282018053
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.2461477269
Short name	T834
Test name
Test status
Simulation time	274692189 ps
CPU time	1.19 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	210384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461477269 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_ctrl_config_regwen.2461477269
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3965786519
Short name	T842
Test name
Test status
Simulation time	864958527 ps
CPU time	3.12 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:19 AM UTC 24
Peak memory	211544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965786519 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3965786519
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3603671264
Short name	T841
Test name
Test status
Simulation time	826588610 ps
CPU time	3.08 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:19 AM UTC 24
Peak memory	211396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603671264 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3603671264
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.331550425
Short name	T827
Test name
Test status
Simulation time	98767960 ps
CPU time	0.88 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	209148 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331550425 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_mubi.331550425
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.2135106035
Short name	T819
Test name
Test status
Simulation time	45972492 ps
CPU time	0.71 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135106035 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.2135106035
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.2336013396
Short name	T843
Test name
Test status
Simulation time	2690867758 ps
CPU time	6.07 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:23 AM UTC 24
Peak memory	211740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336013396 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.2336013396
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.4085560982
Short name	T869
Test name
Test status
Simulation time	4710289583 ps
CPU time	17.67 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:34 AM UTC 24
Peak memory	211408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4085560982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmg r_stress_all_with_rand_reset.4085560982
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.2588934446
Short name	T823
Test name
Test status
Simulation time	157618365 ps
CPU time	0.86 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	209036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588934446 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.2588934446
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.4216931482
Short name	T838
Test name
Test status
Simulation time	316380013 ps
CPU time	1.8 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:18 AM UTC 24
Peak memory	210828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216931482 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.4216931482
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/42.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.1365473732
Short name	T844
Test name
Test status
Simulation time	27931839 ps
CPU time	0.73 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:31 AM UTC 24
Peak memory	209752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365473732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.1365473732
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.2506063376
Short name	T850
Test name
Test status
Simulation time	51323322 ps
CPU time	0.86 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506063376 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disable_rom_integrity_check.2506063376
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.1907651196
Short name	T845
Test name
Test status
Simulation time	32579943 ps
CPU time	0.6 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:31 AM UTC 24
Peak memory	208888 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907651196 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_malfunc.1907651196
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.860477867
Short name	T851
Test name
Test status
Simulation time	109793754 ps
CPU time	0.89 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	209236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860477867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.860477867
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.1049865423
Short name	T848
Test name
Test status
Simulation time	59759900 ps
CPU time	0.65 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049865423 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.1049865423
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.270464302
Short name	T846
Test name
Test status
Simulation time	51161707 ps
CPU time	0.67 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:31 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270464302 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.270464302
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.3428762027
Short name	T837
Test name
Test status
Simulation time	205624760 ps
CPU time	0.96 seconds
Started	Sep 24 08:46:16 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428762027 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_wakeup_race.3428762027
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.941590616
Short name	T831
Test name
Test status
Simulation time	41347184 ps
CPU time	0.69 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	208376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941590616 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.941590616
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.1208622087
Short name	T852
Test name
Test status
Simulation time	155809613 ps
CPU time	0.91 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	220604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208622087 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.1208622087
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.2948503588
Short name	T853
Test name
Test status
Simulation time	263349609 ps
CPU time	0.97 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	210000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948503588 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_ctrl_config_regwen.2948503588
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2843238879
Short name	T867
Test name
Test status
Simulation time	1195851692 ps
CPU time	2.22 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:33 AM UTC 24
Peak memory	211576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843238879 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2843238879
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2450804445
Short name	T868
Test name
Test status
Simulation time	892756696 ps
CPU time	2.52 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:33 AM UTC 24
Peak memory	211616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450804445 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2450804445
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.225500245
Short name	T847
Test name
Test status
Simulation time	51655359 ps
CPU time	0.91 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	209772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225500245 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig_mubi.225500245
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.103793158
Short name	T832
Test name
Test status
Simulation time	37545202 ps
CPU time	0.77 seconds
Started	Sep 24 08:46:15 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	208616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103793158 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.103793158
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.2335907130
Short name	T866
Test name
Test status
Simulation time	346453577 ps
CPU time	1.59 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:33 AM UTC 24
Peak memory	210228 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335907130 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.2335907130
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.1803521235
Short name	T83
Test name
Test status
Simulation time	2431538301 ps
CPU time	8.16 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:39 AM UTC 24
Peak memory	211764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1803521235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmg r_stress_all_with_rand_reset.1803521235
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.4186455376
Short name	T835
Test name
Test status
Simulation time	103335337 ps
CPU time	0.79 seconds
Started	Sep 24 08:46:16 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	209036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186455376 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.4186455376
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.3546676307
Short name	T836
Test name
Test status
Simulation time	154874310 ps
CPU time	0.8 seconds
Started	Sep 24 08:46:16 AM UTC 24
Finished	Sep 24 08:46:17 AM UTC 24
Peak memory	209304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546676307 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.3546676307
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/43.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.4031363849
Short name	T818
Test name
Test status
Simulation time	73732790 ps
CPU time	0.87 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	210628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031363849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.4031363849
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.2664532643
Short name	T859
Test name
Test status
Simulation time	60793920 ps
CPU time	0.82 seconds
Started	Sep 24 08:46:31 AM UTC 24
Finished	Sep 24 08:46:33 AM UTC 24
Peak memory	209700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664532643 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disable_rom_integrity_check.2664532643
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.2802624320
Short name	T858
Test name
Test status
Simulation time	30051437 ps
CPU time	0.64 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802624320 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_malfunc.2802624320
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.3035233455
Short name	T863
Test name
Test status
Simulation time	941227552 ps
CPU time	1.16 seconds
Started	Sep 24 08:46:31 AM UTC 24
Finished	Sep 24 08:46:33 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035233455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.3035233455
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.967801965
Short name	T816
Test name
Test status
Simulation time	58934889 ps
CPU time	0.77 seconds
Started	Sep 24 08:46:31 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	208680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967801965 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.967801965
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.1479984048
Short name	T849
Test name
Test status
Simulation time	104928933 ps
CPU time	0.65 seconds
Started	Sep 24 08:46:31 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479984048 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.1479984048
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.1904211454
Short name	T856
Test name
Test status
Simulation time	47322298 ps
CPU time	0.75 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904211454 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_wakeup_race.1904211454
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.4165915545
Short name	T857
Test name
Test status
Simulation time	77312390 ps
CPU time	0.84 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	209168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165915545 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.4165915545
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset_invalid.367841322
Short name	T864
Test name
Test status
Simulation time	111583795 ps
CPU time	1.04 seconds
Started	Sep 24 08:46:31 AM UTC 24
Finished	Sep 24 08:46:33 AM UTC 24
Peak memory	220308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367841322 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.367841322
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.3587155250
Short name	T861
Test name
Test status
Simulation time	305152366 ps
CPU time	1.03 seconds
Started	Sep 24 08:46:31 AM UTC 24
Finished	Sep 24 08:46:33 AM UTC 24
Peak memory	210444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587155250 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_ctrl_config_regwen.3587155250
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3457129766
Short name	T870
Test name
Test status
Simulation time	795832604 ps
CPU time	3.01 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:34 AM UTC 24
Peak memory	211492 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457129766 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3457129766
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4015627204
Short name	T871
Test name
Test status
Simulation time	888058108 ps
CPU time	3.51 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:35 AM UTC 24
Peak memory	211460 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015627204 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.4015627204
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1977039622
Short name	T691
Test name
Test status
Simulation time	81237906 ps
CPU time	0.95 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	209776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977039622 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1977039622
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.1749623385
Short name	T854
Test name
Test status
Simulation time	55001674 ps
CPU time	0.69 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749623385 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.1749623385
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all.3094584192
Short name	T872
Test name
Test status
Simulation time	1818805411 ps
CPU time	6.51 seconds
Started	Sep 24 08:46:31 AM UTC 24
Finished	Sep 24 08:46:38 AM UTC 24
Peak memory	211612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094584192 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.3094584192
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all_with_rand_reset.3291056208
Short name	T84
Test name
Test status
Simulation time	7487062665 ps
CPU time	9.74 seconds
Started	Sep 24 08:46:31 AM UTC 24
Finished	Sep 24 08:46:42 AM UTC 24
Peak memory	211828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3291056208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmg r_stress_all_with_rand_reset.3291056208
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.870058392
Short name	T855
Test name
Test status
Simulation time	39357001 ps
CPU time	0.63 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:32 AM UTC 24
Peak memory	208836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870058392 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.870058392
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.2043233285
Short name	T862
Test name
Test status
Simulation time	247628880 ps
CPU time	1.31 seconds
Started	Sep 24 08:46:30 AM UTC 24
Finished	Sep 24 08:46:33 AM UTC 24
Peak memory	210424 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043233285 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.2043233285
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/44.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.267601961
Short name	T884
Test name
Test status
Simulation time	42821207 ps
CPU time	1.09 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	210608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267601961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.267601961
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.2412657570
Short name	T888
Test name
Test status
Simulation time	76007673 ps
CPU time	0.79 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	208560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412657570 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disable_rom_integrity_check.2412657570
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.855432988
Short name	T875
Test name
Test status
Simulation time	29834807 ps
CPU time	0.64 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855432988 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst_malfunc.855432988
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.2418733662
Short name	T887
Test name
Test status
Simulation time	1348822541 ps
CPU time	0.83 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	208848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418733662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.2418733662
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.2922375879
Short name	T880
Test name
Test status
Simulation time	31000076 ps
CPU time	0.61 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922375879 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.2922375879
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_global_esc.2480624640
Short name	T881
Test name
Test status
Simulation time	48614962 ps
CPU time	0.63 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	208764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480624640 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.2480624640
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_wakeup_race.266822782
Short name	T874
Test name
Test status
Simulation time	242743107 ps
CPU time	0.89 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	208584 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266822782 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_wakeup_race.266822782
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset.4204499077
Short name	T865
Test name
Test status
Simulation time	182249925 ps
CPU time	0.93 seconds
Started	Sep 24 08:46:31 AM UTC 24
Finished	Sep 24 08:46:33 AM UTC 24
Peak memory	208380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204499077 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.4204499077
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.2653394948
Short name	T889
Test name
Test status
Simulation time	161094879 ps
CPU time	0.92 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	220364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653394948 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.2653394948
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.3067184084
Short name	T883
Test name
Test status
Simulation time	185949099 ps
CPU time	0.73 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	209004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067184084 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_ctrl_config_regwen.3067184084
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.23247263
Short name	T906
Test name
Test status
Simulation time	771935118 ps
CPU time	2.68 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:49 AM UTC 24
Peak memory	211624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23247263 -ass ert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_intersig _mubi.23247263
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3963183904
Short name	T909
Test name
Test status
Simulation time	879061663 ps
CPU time	3.48 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:50 AM UTC 24
Peak memory	211500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963183904 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3963183904
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2313862766
Short name	T890
Test name
Test status
Simulation time	173551140 ps
CPU time	1.13 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	209512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313862766 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2313862766
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_smoke.2516090977
Short name	T860
Test name
Test status
Simulation time	65561587 ps
CPU time	0.75 seconds
Started	Sep 24 08:46:31 AM UTC 24
Finished	Sep 24 08:46:33 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516090977 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.2516090977
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.535166026
Short name	T910
Test name
Test status
Simulation time	2241326651 ps
CPU time	4.2 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:51 AM UTC 24
Peak memory	211612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535166026 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.535166026
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.585950905
Short name	T72
Test name
Test status
Simulation time	3166707959 ps
CPU time	5.97 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:52 AM UTC 24
Peak memory	211616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=585950905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr _stress_all_with_rand_reset.585950905
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.2758929925
Short name	T873
Test name
Test status
Simulation time	81903732 ps
CPU time	0.77 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	208752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758929925 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.2758929925
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.2496690720
Short name	T876
Test name
Test status
Simulation time	108619202 ps
CPU time	0.88 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	208640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496690720 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.2496690720
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/45.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.1605145752
Short name	T895
Test name
Test status
Simulation time	56402372 ps
CPU time	0.73 seconds
Started	Sep 24 08:46:46 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605145752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.1605145752
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.763916210
Short name	T903
Test name
Test status
Simulation time	76726006 ps
CPU time	0.86 seconds
Started	Sep 24 08:46:46 AM UTC 24
Finished	Sep 24 08:46:48 AM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763916210 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disable_rom_integrity_check.763916210
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.2631813800
Short name	T893
Test name
Test status
Simulation time	38067262 ps
CPU time	0.61 seconds
Started	Sep 24 08:46:46 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631813800 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_malfunc.2631813800
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.4120489866
Short name	T902
Test name
Test status
Simulation time	686471870 ps
CPU time	0.93 seconds
Started	Sep 24 08:46:46 AM UTC 24
Finished	Sep 24 08:46:48 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120489866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.4120489866
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_glitch.927260100
Short name	T900
Test name
Test status
Simulation time	44494525 ps
CPU time	0.7 seconds
Started	Sep 24 08:46:46 AM UTC 24
Finished	Sep 24 08:46:48 AM UTC 24
Peak memory	208680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927260100 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.927260100
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.4111689879
Short name	T896
Test name
Test status
Simulation time	29331246 ps
CPU time	0.59 seconds
Started	Sep 24 08:46:46 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111689879 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.4111689879
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.3669415571
Short name	T891
Test name
Test status
Simulation time	154807548 ps
CPU time	0.75 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	208988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669415571 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_wakeup_race.3669415571
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset.3802339273
Short name	T897
Test name
Test status
Simulation time	70629413 ps
CPU time	0.96 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:48 AM UTC 24
Peak memory	209436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802339273 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.3802339273
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.153030423
Short name	T901
Test name
Test status
Simulation time	143943572 ps
CPU time	0.94 seconds
Started	Sep 24 08:46:46 AM UTC 24
Finished	Sep 24 08:46:48 AM UTC 24
Peak memory	220304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153030423 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.153030423
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.4154778709
Short name	T905
Test name
Test status
Simulation time	203852361 ps
CPU time	1.2 seconds
Started	Sep 24 08:46:46 AM UTC 24
Finished	Sep 24 08:46:48 AM UTC 24
Peak memory	210288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154778709 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_ctrl_config_regwen.4154778709
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.368932178
Short name	T907
Test name
Test status
Simulation time	921561149 ps
CPU time	2.69 seconds
Started	Sep 24 08:46:46 AM UTC 24
Finished	Sep 24 08:46:49 AM UTC 24
Peak memory	211448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368932178 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.368932178
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1900446152
Short name	T908
Test name
Test status
Simulation time	1047794524 ps
CPU time	2.64 seconds
Started	Sep 24 08:46:46 AM UTC 24
Finished	Sep 24 08:46:49 AM UTC 24
Peak memory	211560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900446152 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1900446152
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.2206350406
Short name	T899
Test name
Test status
Simulation time	65409415 ps
CPU time	0.92 seconds
Started	Sep 24 08:46:46 AM UTC 24
Finished	Sep 24 08:46:48 AM UTC 24
Peak memory	209568 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206350406 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig_mubi.2206350406
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.2200792957
Short name	T892
Test name
Test status
Simulation time	30837733 ps
CPU time	0.71 seconds
Started	Sep 24 08:46:45 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	208620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200792957 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2200792957
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.3306310371
Short name	T928
Test name
Test status
Simulation time	884837530 ps
CPU time	1.9 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:06 AM UTC 24
Peak memory	210528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306310371 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.3306310371
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.4218269394
Short name	T935
Test name
Test status
Simulation time	772126833 ps
CPU time	3.55 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:07 AM UTC 24
Peak memory	211632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4218269394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmg r_stress_all_with_rand_reset.4218269394
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.42798907
Short name	T894
Test name
Test status
Simulation time	297476074 ps
CPU time	0.72 seconds
Started	Sep 24 08:46:46 AM UTC 24
Finished	Sep 24 08:46:47 AM UTC 24
Peak memory	208912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42798907 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.42798907
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.4004367873
Short name	T904
Test name
Test status
Simulation time	280138287 ps
CPU time	1.24 seconds
Started	Sep 24 08:46:46 AM UTC 24
Finished	Sep 24 08:46:48 AM UTC 24
Peak memory	210648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004367873 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.4004367873
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/46.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.1198531921
Short name	T917
Test name
Test status
Simulation time	124985717 ps
CPU time	0.84 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	210004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198531921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.1198531921
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.2604096404
Short name	T877
Test name
Test status
Simulation time	64380483 ps
CPU time	0.78 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604096404 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_disable_rom_integrity_check.2604096404
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.1643760517
Short name	T918
Test name
Test status
Simulation time	57517851 ps
CPU time	0.65 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643760517 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_malfunc.1643760517
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.707100369
Short name	T922
Test name
Test status
Simulation time	157846123 ps
CPU time	0.83 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707100369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.707100369
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.2435036952
Short name	T921
Test name
Test status
Simulation time	59466278 ps
CPU time	0.65 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435036952 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.2435036952
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.3597854539
Short name	T919
Test name
Test status
Simulation time	56810148 ps
CPU time	0.61 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597854539 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.3597854539
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.4077454614
Short name	T916
Test name
Test status
Simulation time	67803867 ps
CPU time	0.68 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077454614 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_wakeup_race.4077454614
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.2801852871
Short name	T912
Test name
Test status
Simulation time	55099429 ps
CPU time	0.75 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	208380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801852871 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.2801852871
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.2790985942
Short name	T913
Test name
Test status
Simulation time	98226308 ps
CPU time	1.12 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	220364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790985942 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.2790985942
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.2468460809
Short name	T885
Test name
Test status
Simulation time	391036573 ps
CPU time	1.05 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	210000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468460809 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_ctrl_config_regwen.2468460809
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.646705611
Short name	T934
Test name
Test status
Simulation time	711220244 ps
CPU time	3.08 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:07 AM UTC 24
Peak memory	211448 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646705611 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.646705611
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3178524873
Short name	T936
Test name
Test status
Simulation time	891657127 ps
CPU time	3.25 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:07 AM UTC 24
Peak memory	211520 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178524873 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3178524873
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.808144759
Short name	T920
Test name
Test status
Simulation time	65867107 ps
CPU time	0.83 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	209772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808144759 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig_mubi.808144759
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.2659983353
Short name	T911
Test name
Test status
Simulation time	32924526 ps
CPU time	0.67 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:04 AM UTC 24
Peak memory	208680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659983353 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.2659983353
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.2615826985
Short name	T938
Test name
Test status
Simulation time	729554187 ps
CPU time	3.43 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:08 AM UTC 24
Peak memory	211344 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615826985 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.2615826985
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.63525748
Short name	T937
Test name
Test status
Simulation time	663009250 ps
CPU time	3.3 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:08 AM UTC 24
Peak memory	210752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=63525748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_ stress_all_with_rand_reset.63525748
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.2453601247
Short name	T915
Test name
Test status
Simulation time	217581955 ps
CPU time	0.84 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	209036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453601247 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.2453601247
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.1138442196
Short name	T923
Test name
Test status
Simulation time	328707867 ps
CPU time	1 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	210708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138442196 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.1138442196
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/47.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.3924132089
Short name	T898
Test name
Test status
Simulation time	31344932 ps
CPU time	0.86 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:06 AM UTC 24
Peak memory	210000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924132089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.3924132089
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.2186938343
Short name	T927
Test name
Test status
Simulation time	61527741 ps
CPU time	0.74 seconds
Started	Sep 24 08:47:04 AM UTC 24
Finished	Sep 24 08:47:06 AM UTC 24
Peak memory	208380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186938343 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disable_rom_integrity_check.2186938343
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2865715932
Short name	T879
Test name
Test status
Simulation time	31621426 ps
CPU time	0.74 seconds
Started	Sep 24 08:47:04 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865715932 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_malfunc.2865715932
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.2863611058
Short name	T931
Test name
Test status
Simulation time	112004636 ps
CPU time	0.88 seconds
Started	Sep 24 08:47:04 AM UTC 24
Finished	Sep 24 08:47:06 AM UTC 24
Peak memory	208336 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863611058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.2863611058
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.133334993
Short name	T886
Test name
Test status
Simulation time	72929909 ps
CPU time	0.69 seconds
Started	Sep 24 08:47:04 AM UTC 24
Finished	Sep 24 08:47:06 AM UTC 24
Peak memory	208504 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133334993 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.133334993
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.2017586509
Short name	T926
Test name
Test status
Simulation time	30912091 ps
CPU time	0.75 seconds
Started	Sep 24 08:47:04 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017586509 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.2017586509
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.133888423
Short name	T914
Test name
Test status
Simulation time	169160839 ps
CPU time	1.01 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:06 AM UTC 24
Peak memory	208428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133888423 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_wakeup_race.133888423
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.3831668693
Short name	T924
Test name
Test status
Simulation time	27440853 ps
CPU time	0.73 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831668693 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.3831668693
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.3888012667
Short name	T882
Test name
Test status
Simulation time	246841504 ps
CPU time	0.74 seconds
Started	Sep 24 08:47:04 AM UTC 24
Finished	Sep 24 08:47:06 AM UTC 24
Peak memory	220604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888012667 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.3888012667
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.3933657863
Short name	T929
Test name
Test status
Simulation time	295478822 ps
CPU time	0.86 seconds
Started	Sep 24 08:47:04 AM UTC 24
Finished	Sep 24 08:47:06 AM UTC 24
Peak memory	209796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933657863 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_ctrl_config_regwen.3933657863
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.825376072
Short name	T933
Test name
Test status
Simulation time	1192279853 ps
CPU time	2.28 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:07 AM UTC 24
Peak memory	211436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825376072 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.825376072
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4229039802
Short name	T939
Test name
Test status
Simulation time	871152840 ps
CPU time	3.43 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:08 AM UTC 24
Peak memory	211444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229039802 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.4229039802
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3226303890
Short name	T930
Test name
Test status
Simulation time	104839122 ps
CPU time	0.89 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:06 AM UTC 24
Peak memory	209152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226303890 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3226303890
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.3036155608
Short name	T925
Test name
Test status
Simulation time	29343922 ps
CPU time	0.88 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036155608 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.3036155608
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.1839887242
Short name	T957
Test name
Test status
Simulation time	2540440463 ps
CPU time	5.6 seconds
Started	Sep 24 08:47:20 AM UTC 24
Finished	Sep 24 08:47:27 AM UTC 24
Peak memory	211600 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839887242 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.1839887242
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all_with_rand_reset.975533375
Short name	T105
Test name
Test status
Simulation time	3284634772 ps
CPU time	11.87 seconds
Started	Sep 24 08:47:04 AM UTC 24
Finished	Sep 24 08:47:17 AM UTC 24
Peak memory	211816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=975533375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr _stress_all_with_rand_reset.975533375
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.3601913805
Short name	T932
Test name
Test status
Simulation time	159358460 ps
CPU time	1.18 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:06 AM UTC 24
Peak memory	209036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601913805 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.3601913805
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.1528783868
Short name	T878
Test name
Test status
Simulation time	39931444 ps
CPU time	0.66 seconds
Started	Sep 24 08:47:03 AM UTC 24
Finished	Sep 24 08:47:05 AM UTC 24
Peak memory	208500 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528783868 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.1528783868
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/48.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.2751475118
Short name	T945
Test name
Test status
Simulation time	62785625 ps
CPU time	0.75 seconds
Started	Sep 24 08:47:20 AM UTC 24
Finished	Sep 24 08:47:22 AM UTC 24
Peak memory	210064 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751475118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.2751475118
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.557884580
Short name	T950
Test name
Test status
Simulation time	59887783 ps
CPU time	0.8 seconds
Started	Sep 24 08:47:21 AM UTC 24
Finished	Sep 24 08:47:23 AM UTC 24
Peak memory	209632 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557884580 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_disable_rom_integrity_check.557884580
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3412222755
Short name	T943
Test name
Test status
Simulation time	39381368 ps
CPU time	0.58 seconds
Started	Sep 24 08:47:20 AM UTC 24
Finished	Sep 24 08:47:22 AM UTC 24
Peak memory	208624 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412222755 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_malfunc.3412222755
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.3608130067
Short name	T951
Test name
Test status
Simulation time	370945693 ps
CPU time	0.83 seconds
Started	Sep 24 08:47:21 AM UTC 24
Finished	Sep 24 08:47:23 AM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608130067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.3608130067
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.3863997605
Short name	T948
Test name
Test status
Simulation time	49138020 ps
CPU time	0.66 seconds
Started	Sep 24 08:47:21 AM UTC 24
Finished	Sep 24 08:47:23 AM UTC 24
Peak memory	208736 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863997605 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.3863997605
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.2582170114
Short name	T946
Test name
Test status
Simulation time	81737665 ps
CPU time	0.6 seconds
Started	Sep 24 08:47:21 AM UTC 24
Finished	Sep 24 08:47:23 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582170114 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.2582170114
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.1659408656
Short name	T942
Test name
Test status
Simulation time	181011224 ps
CPU time	0.77 seconds
Started	Sep 24 08:47:20 AM UTC 24
Finished	Sep 24 08:47:22 AM UTC 24
Peak memory	208868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659408656 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_wakeup_race.1659408656
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.2784565616
Short name	T940
Test name
Test status
Simulation time	58123129 ps
CPU time	0.7 seconds
Started	Sep 24 08:47:20 AM UTC 24
Finished	Sep 24 08:47:22 AM UTC 24
Peak memory	208380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784565616 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.2784565616
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.2520329757
Short name	T953
Test name
Test status
Simulation time	101390784 ps
CPU time	0.98 seconds
Started	Sep 24 08:47:21 AM UTC 24
Finished	Sep 24 08:47:23 AM UTC 24
Peak memory	220664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520329757 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.2520329757
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.3042074697
Short name	T954
Test name
Test status
Simulation time	241698660 ps
CPU time	1.12 seconds
Started	Sep 24 08:47:21 AM UTC 24
Finished	Sep 24 08:47:23 AM UTC 24
Peak memory	210000 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042074697 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_ctrl_config_regwen.3042074697
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4102114158
Short name	T955
Test name
Test status
Simulation time	1310952531 ps
CPU time	2.14 seconds
Started	Sep 24 08:47:20 AM UTC 24
Finished	Sep 24 08:47:24 AM UTC 24
Peak memory	211508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102114158 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.4102114158
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1099155212
Short name	T956
Test name
Test status
Simulation time	818352196 ps
CPU time	3.01 seconds
Started	Sep 24 08:47:20 AM UTC 24
Finished	Sep 24 08:47:25 AM UTC 24
Peak memory	211496 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099155212 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1099155212
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.3544076081
Short name	T947
Test name
Test status
Simulation time	73517102 ps
CPU time	0.94 seconds
Started	Sep 24 08:47:20 AM UTC 24
Finished	Sep 24 08:47:23 AM UTC 24
Peak memory	209384 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544076081 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_mubi.3544076081
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.1769620097
Short name	T941
Test name
Test status
Simulation time	31175463 ps
CPU time	0.63 seconds
Started	Sep 24 08:47:20 AM UTC 24
Finished	Sep 24 08:47:22 AM UTC 24
Peak memory	208980 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769620097 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.1769620097
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.3958776526
Short name	T952
Test name
Test status
Simulation time	65245593 ps
CPU time	0.72 seconds
Started	Sep 24 08:47:21 AM UTC 24
Finished	Sep 24 08:47:23 AM UTC 24
Peak memory	208680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958776526 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.3958776526
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.54072315
Short name	T958
Test name
Test status
Simulation time	3239676233 ps
CPU time	5.7 seconds
Started	Sep 24 08:47:21 AM UTC 24
Finished	Sep 24 08:47:28 AM UTC 24
Peak memory	211684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=54072315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_ stress_all_with_rand_reset.54072315
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.1578155251
Short name	T944
Test name
Test status
Simulation time	198357356 ps
CPU time	0.9 seconds
Started	Sep 24 08:47:20 AM UTC 24
Finished	Sep 24 08:47:22 AM UTC 24
Peak memory	209428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578155251 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.1578155251
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.1612199424
Short name	T949
Test name
Test status
Simulation time	171418174 ps
CPU time	1.14 seconds
Started	Sep 24 08:47:20 AM UTC 24
Finished	Sep 24 08:47:23 AM UTC 24
Peak memory	210708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612199424 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.1612199424
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/49.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.564878289
Short name	T107
Test name
Test status
Simulation time	54479650 ps
CPU time	1.09 seconds
Started	Sep 24 08:42:32 AM UTC 24
Finished	Sep 24 08:42:34 AM UTC 24
Peak memory	208948 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564878289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.564878289
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.1539353452
Short name	T162
Test name
Test status
Simulation time	60019434 ps
CPU time	1.25 seconds
Started	Sep 24 08:42:34 AM UTC 24
Finished	Sep 24 08:42:36 AM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539353452 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disable_rom_integrity_check.1539353452
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.2853678149
Short name	T217
Test name
Test status
Simulation time	31719774 ps
CPU time	0.98 seconds
Started	Sep 24 08:42:32 AM UTC 24
Finished	Sep 24 08:42:34 AM UTC 24
Peak memory	208864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853678149 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_malfunc.2853678149
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.2833242649
Short name	T153
Test name
Test status
Simulation time	476898714 ps
CPU time	1.27 seconds
Started	Sep 24 08:42:32 AM UTC 24
Finished	Sep 24 08:42:35 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833242649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.2833242649
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.1574564569
Short name	T222
Test name
Test status
Simulation time	34261550 ps
CPU time	1.04 seconds
Started	Sep 24 08:42:34 AM UTC 24
Finished	Sep 24 08:42:36 AM UTC 24
Peak memory	208588 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574564569 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.1574564569
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.3501610088
Short name	T216
Test name
Test status
Simulation time	61142544 ps
CPU time	0.84 seconds
Started	Sep 24 08:42:32 AM UTC 24
Finished	Sep 24 08:42:34 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501610088 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.3501610088
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.3643705262
Short name	T211
Test name
Test status
Simulation time	136323301 ps
CPU time	1.06 seconds
Started	Sep 24 08:42:30 AM UTC 24
Finished	Sep 24 08:42:32 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643705262 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wakeup_race.3643705262
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.386507268
Short name	T213
Test name
Test status
Simulation time	76810526 ps
CPU time	1.43 seconds
Started	Sep 24 08:42:30 AM UTC 24
Finished	Sep 24 08:42:33 AM UTC 24
Peak memory	210472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386507268 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.386507268
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.4293083940
Short name	T223
Test name
Test status
Simulation time	235592583 ps
CPU time	1.08 seconds
Started	Sep 24 08:42:34 AM UTC 24
Finished	Sep 24 08:42:36 AM UTC 24
Peak memory	220604 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293083940 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.4293083940
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.769961491
Short name	T220
Test name
Test status
Simulation time	102126056 ps
CPU time	1.46 seconds
Started	Sep 24 08:42:32 AM UTC 24
Finished	Sep 24 08:42:35 AM UTC 24
Peak memory	208684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769961491 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_ctrl_config_regwen.769961491
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1868239692
Short name	T225
Test name
Test status
Simulation time	1916262167 ps
CPU time	3.06 seconds
Started	Sep 24 08:42:32 AM UTC 24
Finished	Sep 24 08:42:36 AM UTC 24
Peak memory	211512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868239692 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.1868239692
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.339360549
Short name	T161
Test name
Test status
Simulation time	963425343 ps
CPU time	2.24 seconds
Started	Sep 24 08:42:32 AM UTC 24
Finished	Sep 24 08:42:36 AM UTC 24
Peak memory	211464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339360549 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_inters ig_mubi.339360549
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1060972578
Short name	T219
Test name
Test status
Simulation time	65922314 ps
CPU time	1.23 seconds
Started	Sep 24 08:42:32 AM UTC 24
Finished	Sep 24 08:42:35 AM UTC 24
Peak memory	209152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060972578 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1060972578
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.1145741640
Short name	T210
Test name
Test status
Simulation time	46595205 ps
CPU time	0.98 seconds
Started	Sep 24 08:42:30 AM UTC 24
Finished	Sep 24 08:42:32 AM UTC 24
Peak memory	208316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145741640 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.1145741640
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.3420418844
Short name	T102
Test name
Test status
Simulation time	468093728 ps
CPU time	2.8 seconds
Started	Sep 24 08:42:34 AM UTC 24
Finished	Sep 24 08:42:38 AM UTC 24
Peak memory	211416 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420418844 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.3420418844
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.3568898260
Short name	T131
Test name
Test status
Simulation time	3299521831 ps
CPU time	13.08 seconds
Started	Sep 24 08:42:34 AM UTC 24
Finished	Sep 24 08:42:49 AM UTC 24
Peak memory	211692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3568898260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr _stress_all_with_rand_reset.3568898260
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.7081870
Short name	T214
Test name
Test status
Simulation time	202482858 ps
CPU time	2.27 seconds
Started	Sep 24 08:42:30 AM UTC 24
Finished	Sep 24 08:42:34 AM UTC 24
Peak memory	209964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7081870 -assert nopostproc +UVM_TESTNAME=pwrmgr_ base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23 /pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.7081870
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.1390371037
Short name	T218
Test name
Test status
Simulation time	193512460 ps
CPU time	1.52 seconds
Started	Sep 24 08:42:32 AM UTC 24
Finished	Sep 24 08:42:35 AM UTC 24
Peak memory	210676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390371037 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.1390371037
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/5.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.4142810751
Short name	T101
Test name
Test status
Simulation time	53531213 ps
CPU time	1.01 seconds
Started	Sep 24 08:42:36 AM UTC 24
Finished	Sep 24 08:42:38 AM UTC 24
Peak memory	209364 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142810751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.4142810751
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.2726275374
Short name	T229
Test name
Test status
Simulation time	58463172 ps
CPU time	1.04 seconds
Started	Sep 24 08:42:38 AM UTC 24
Finished	Sep 24 08:42:40 AM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726275374 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disable_rom_integrity_check.2726275374
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2289555667
Short name	T226
Test name
Test status
Simulation time	30724559 ps
CPU time	0.88 seconds
Started	Sep 24 08:42:38 AM UTC 24
Finished	Sep 24 08:42:39 AM UTC 24
Peak memory	208864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289555667 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_malfunc.2289555667
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.1056851427
Short name	T154
Test name
Test status
Simulation time	208631953 ps
CPU time	1.08 seconds
Started	Sep 24 08:42:38 AM UTC 24
Finished	Sep 24 08:42:40 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056851427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.1056851427
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.2562938809
Short name	T228
Test name
Test status
Simulation time	78234339 ps
CPU time	0.85 seconds
Started	Sep 24 08:42:38 AM UTC 24
Finished	Sep 24 08:42:40 AM UTC 24
Peak memory	208676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562938809 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.2562938809
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.548558260
Short name	T227
Test name
Test status
Simulation time	43615236 ps
CPU time	0.95 seconds
Started	Sep 24 08:42:38 AM UTC 24
Finished	Sep 24 08:42:40 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548558260 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.548558260
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.4036518795
Short name	T99
Test name
Test status
Simulation time	48821492 ps
CPU time	1.01 seconds
Started	Sep 24 08:42:36 AM UTC 24
Finished	Sep 24 08:42:38 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036518795 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wakeup_race.4036518795
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.1802489249
Short name	T97
Test name
Test status
Simulation time	21290816 ps
CPU time	0.99 seconds
Started	Sep 24 08:42:36 AM UTC 24
Finished	Sep 24 08:42:38 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802489249 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.1802489249
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.933267838
Short name	T231
Test name
Test status
Simulation time	172051545 ps
CPU time	1.35 seconds
Started	Sep 24 08:42:38 AM UTC 24
Finished	Sep 24 08:42:40 AM UTC 24
Peak memory	210244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933267838 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.933267838
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1710564858
Short name	T230
Test name
Test status
Simulation time	137527333 ps
CPU time	1.27 seconds
Started	Sep 24 08:42:38 AM UTC 24
Finished	Sep 24 08:42:40 AM UTC 24
Peak memory	208684 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710564858 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_ctrl_config_regwen.1710564858
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2697632828
Short name	T232
Test name
Test status
Simulation time	738077119 ps
CPU time	3.98 seconds
Started	Sep 24 08:42:36 AM UTC 24
Finished	Sep 24 08:42:41 AM UTC 24
Peak memory	211512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697632828 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.2697632828
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2766729834
Short name	T233
Test name
Test status
Simulation time	866800966 ps
CPU time	4.99 seconds
Started	Sep 24 08:42:36 AM UTC 24
Finished	Sep 24 08:42:42 AM UTC 24
Peak memory	211464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766729834 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.2766729834
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.1598337556
Short name	T103
Test name
Test status
Simulation time	65447119 ps
CPU time	1.15 seconds
Started	Sep 24 08:42:36 AM UTC 24
Finished	Sep 24 08:42:38 AM UTC 24
Peak memory	209572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598337556 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_mubi.1598337556
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.4256973392
Short name	T224
Test name
Test status
Simulation time	76778487 ps
CPU time	1.03 seconds
Started	Sep 24 08:42:34 AM UTC 24
Finished	Sep 24 08:42:36 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256973392 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.4256973392
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.3883306499
Short name	T108
Test name
Test status
Simulation time	1344584872 ps
CPU time	4.66 seconds
Started	Sep 24 08:42:41 AM UTC 24
Finished	Sep 24 08:42:47 AM UTC 24
Peak memory	211528 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883306499 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.3883306499
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.3643894971
Short name	T104
Test name
Test status
Simulation time	308917346 ps
CPU time	1.89 seconds
Started	Sep 24 08:42:36 AM UTC 24
Finished	Sep 24 08:42:39 AM UTC 24
Peak memory	209852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643894971 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.3643894971
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.3538195391
Short name	T100
Test name
Test status
Simulation time	39444838 ps
CPU time	1.04 seconds
Started	Sep 24 08:42:36 AM UTC 24
Finished	Sep 24 08:42:38 AM UTC 24
Peak memory	208560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538195391 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.3538195391
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/6.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.2433053659
Short name	T236
Test name
Test status
Simulation time	31897912 ps
CPU time	1.02 seconds
Started	Sep 24 08:42:41 AM UTC 24
Finished	Sep 24 08:42:43 AM UTC 24
Peak memory	209304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433053659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.2433053659
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.1709983912
Short name	T247
Test name
Test status
Simulation time	86965779 ps
CPU time	1.13 seconds
Started	Sep 24 08:42:43 AM UTC 24
Finished	Sep 24 08:42:46 AM UTC 24
Peak memory	208380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709983912 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disable_rom_integrity_check.1709983912
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3505986982
Short name	T237
Test name
Test status
Simulation time	30068085 ps
CPU time	0.89 seconds
Started	Sep 24 08:42:41 AM UTC 24
Finished	Sep 24 08:42:43 AM UTC 24
Peak memory	208864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505986982 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_malfunc.3505986982
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.2417074901
Short name	T243
Test name
Test status
Simulation time	114281019 ps
CPU time	1.17 seconds
Started	Sep 24 08:42:42 AM UTC 24
Finished	Sep 24 08:42:44 AM UTC 24
Peak memory	208440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417074901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.2417074901
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.2715628319
Short name	T245
Test name
Test status
Simulation time	80398107 ps
CPU time	0.98 seconds
Started	Sep 24 08:42:43 AM UTC 24
Finished	Sep 24 08:42:45 AM UTC 24
Peak memory	208676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715628319 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.2715628319
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.3251588193
Short name	T241
Test name
Test status
Simulation time	43263560 ps
CPU time	0.98 seconds
Started	Sep 24 08:42:42 AM UTC 24
Finished	Sep 24 08:42:44 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251588193 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.3251588193
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.870939823
Short name	T238
Test name
Test status
Simulation time	167725924 ps
CPU time	1.36 seconds
Started	Sep 24 08:42:41 AM UTC 24
Finished	Sep 24 08:42:44 AM UTC 24
Peak memory	209476 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870939823 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wakeup_race.870939823
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.3240807521
Short name	T240
Test name
Test status
Simulation time	78765009 ps
CPU time	1.44 seconds
Started	Sep 24 08:42:41 AM UTC 24
Finished	Sep 24 08:42:44 AM UTC 24
Peak memory	209432 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240807521 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.3240807521
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.2074365070
Short name	T249
Test name
Test status
Simulation time	112355939 ps
CPU time	1.36 seconds
Started	Sep 24 08:42:44 AM UTC 24
Finished	Sep 24 08:42:46 AM UTC 24
Peak memory	220664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074365070 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.2074365070
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.4214963249
Short name	T242
Test name
Test status
Simulation time	153186460 ps
CPU time	1.09 seconds
Started	Sep 24 08:42:41 AM UTC 24
Finished	Sep 24 08:42:44 AM UTC 24
Peak memory	208804 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214963249 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_ctrl_config_regwen.4214963249
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.556081223
Short name	T248
Test name
Test status
Simulation time	947844013 ps
CPU time	3.34 seconds
Started	Sep 24 08:42:41 AM UTC 24
Finished	Sep 24 08:42:46 AM UTC 24
Peak memory	211440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556081223 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersig _mubi.556081223
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.987163564
Short name	T250
Test name
Test status
Simulation time	1052305312 ps
CPU time	4 seconds
Started	Sep 24 08:42:41 AM UTC 24
Finished	Sep 24 08:42:46 AM UTC 24
Peak memory	211428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987163564 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_inters ig_mubi.987163564
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3763272505
Short name	T244
Test name
Test status
Simulation time	114489797 ps
CPU time	1.51 seconds
Started	Sep 24 08:42:41 AM UTC 24
Finished	Sep 24 08:42:45 AM UTC 24
Peak memory	209836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763272505 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3763272505
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.3795499176
Short name	T234
Test name
Test status
Simulation time	56866406 ps
CPU time	0.99 seconds
Started	Sep 24 08:42:41 AM UTC 24
Finished	Sep 24 08:42:43 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795499176 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.3795499176
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.1732865310
Short name	T92
Test name
Test status
Simulation time	1905961901 ps
CPU time	6.38 seconds
Started	Sep 24 08:42:48 AM UTC 24
Finished	Sep 24 08:42:56 AM UTC 24
Peak memory	211472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732865310 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.1732865310
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.2858275789
Short name	T78
Test name
Test status
Simulation time	4362666898 ps
CPU time	7.95 seconds
Started	Sep 24 08:42:48 AM UTC 24
Finished	Sep 24 08:42:58 AM UTC 24
Peak memory	211616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2858275789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr _stress_all_with_rand_reset.2858275789
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.1771475196
Short name	T239
Test name
Test status
Simulation time	223015859 ps
CPU time	1.49 seconds
Started	Sep 24 08:42:41 AM UTC 24
Finished	Sep 24 08:42:44 AM UTC 24
Peak memory	209768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771475196 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.1771475196
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.3706940536
Short name	T235
Test name
Test status
Simulation time	105238132 ps
CPU time	1.11 seconds
Started	Sep 24 08:42:41 AM UTC 24
Finished	Sep 24 08:42:43 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706940536 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.3706940536
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/7.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.3044980477
Short name	T109
Test name
Test status
Simulation time	51008012 ps
CPU time	1.43 seconds
Started	Sep 24 08:42:48 AM UTC 24
Finished	Sep 24 08:42:51 AM UTC 24
Peak memory	210264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044980477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.3044980477
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.2417152844
Short name	T86
Test name
Test status
Simulation time	57340049 ps
CPU time	1.21 seconds
Started	Sep 24 08:42:50 AM UTC 24
Finished	Sep 24 08:42:53 AM UTC 24
Peak memory	208644 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417152844 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disable_rom_integrity_check.2417152844
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_disable_rom_integrity_check/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.227327174
Short name	T251
Test name
Test status
Simulation time	31041126 ps
CPU time	0.93 seconds
Started	Sep 24 08:42:48 AM UTC 24
Finished	Sep 24 08:42:51 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227327174 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_malfunc.227327174
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2685974423
Short name	T255
Test name
Test status
Simulation time	378286627 ps
CPU time	1.23 seconds
Started	Sep 24 08:42:49 AM UTC 24
Finished	Sep 24 08:42:51 AM UTC 24
Peak memory	208920 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685974423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.2685974423
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.4219681159
Short name	T253
Test name
Test status
Simulation time	67404547 ps
CPU time	1 seconds
Started	Sep 24 08:42:49 AM UTC 24
Finished	Sep 24 08:42:51 AM UTC 24
Peak memory	208676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219681159 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.4219681159
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.4143515293
Short name	T221
Test name
Test status
Simulation time	38530475 ps
CPU time	0.79 seconds
Started	Sep 24 08:42:49 AM UTC 24
Finished	Sep 24 08:42:51 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143515293 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.4143515293
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.1395427907
Short name	T256
Test name
Test status
Simulation time	271078282 ps
CPU time	1.69 seconds
Started	Sep 24 08:42:48 AM UTC 24
Finished	Sep 24 08:42:51 AM UTC 24
Peak memory	209452 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395427907 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wakeup_race.1395427907
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.2403155766
Short name	T138
Test name
Test status
Simulation time	91437752 ps
CPU time	1.07 seconds
Started	Sep 24 08:42:48 AM UTC 24
Finished	Sep 24 08:42:51 AM UTC 24
Peak memory	208640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403155766 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.2403155766
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.2357213975
Short name	T87
Test name
Test status
Simulation time	112117827 ps
CPU time	1.3 seconds
Started	Sep 24 08:42:50 AM UTC 24
Finished	Sep 24 08:42:53 AM UTC 24
Peak memory	220348 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357213975 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.2357213975
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.3342197082
Short name	T252
Test name
Test status
Simulation time	271042191 ps
CPU time	1.02 seconds
Started	Sep 24 08:42:48 AM UTC 24
Finished	Sep 24 08:42:51 AM UTC 24
Peak memory	209740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342197082 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_ctrl_config_regwen.3342197082
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3915671301
Short name	T89
Test name
Test status
Simulation time	738752769 ps
CPU time	3.68 seconds
Started	Sep 24 08:42:48 AM UTC 24
Finished	Sep 24 08:42:54 AM UTC 24
Peak memory	211508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915671301 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.3915671301
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.731229343
Short name	T88
Test name
Test status
Simulation time	1024742506 ps
CPU time	3.55 seconds
Started	Sep 24 08:42:48 AM UTC 24
Finished	Sep 24 08:42:53 AM UTC 24
Peak memory	211492 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731229343 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_inters ig_mubi.731229343
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3187333006
Short name	T254
Test name
Test status
Simulation time	51512057 ps
CPU time	1.35 seconds
Started	Sep 24 08:42:48 AM UTC 24
Finished	Sep 24 08:42:51 AM UTC 24
Peak memory	209272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187333006 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3187333006
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.2614784070
Short name	T98
Test name
Test status
Simulation time	53718684 ps
CPU time	0.84 seconds
Started	Sep 24 08:42:48 AM UTC 24
Finished	Sep 24 08:42:50 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614784070 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.2614784070
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1417515739
Short name	T110
Test name
Test status
Simulation time	3891116870 ps
CPU time	6.27 seconds
Started	Sep 24 08:42:54 AM UTC 24
Finished	Sep 24 08:43:01 AM UTC 24
Peak memory	211544 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417515739 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.1417515739
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.1191434935
Short name	T132
Test name
Test status
Simulation time	4508426380 ps
CPU time	13.63 seconds
Started	Sep 24 08:42:50 AM UTC 24
Finished	Sep 24 08:43:06 AM UTC 24
Peak memory	211628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1191434935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr _stress_all_with_rand_reset.1191434935
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.2806854472
Short name	T246
Test name
Test status
Simulation time	991590840 ps
CPU time	1.28 seconds
Started	Sep 24 08:42:48 AM UTC 24
Finished	Sep 24 08:42:51 AM UTC 24
Peak memory	210072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806854472 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.2806854472
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.166035596
Short name	T215
Test name
Test status
Simulation time	196815994 ps
CPU time	1.11 seconds
Started	Sep 24 08:42:48 AM UTC 24
Finished	Sep 24 08:42:51 AM UTC 24
Peak memory	208560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166035596 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.166035596
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/8.pwrmgr_wakeup_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.3608785203
Short name	T257
Test name
Test status
Simulation time	29112341 ps
CPU time	1.15 seconds
Started	Sep 24 08:42:54 AM UTC 24
Finished	Sep 24 08:42:56 AM UTC 24
Peak memory	210060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608785203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.3608785203
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_aborted_low_power/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3214535780
Short name	T93
Test name
Test status
Simulation time	28653801 ps
CPU time	0.92 seconds
Started	Sep 24 08:42:54 AM UTC 24
Finished	Sep 24 08:42:56 AM UTC 24
Peak memory	208864 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214535780 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_malfunc.3214535780
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.402447840
Short name	T263
Test name
Test status
Simulation time	400492181 ps
CPU time	1.1 seconds
Started	Sep 24 08:42:54 AM UTC 24
Finished	Sep 24 08:42:56 AM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402447840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.402447840
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_escalation_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1396190967
Short name	T268
Test name
Test status
Simulation time	39007574 ps
CPU time	0.84 seconds
Started	Sep 24 08:42:56 AM UTC 24
Finished	Sep 24 08:42:58 AM UTC 24
Peak memory	208616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396190967 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.1396190967
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_glitch/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.1443726313
Short name	T259
Test name
Test status
Simulation time	22967896 ps
CPU time	0.88 seconds
Started	Sep 24 08:42:54 AM UTC 24
Finished	Sep 24 08:42:56 AM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443726313 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.1443726313
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_global_esc/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.4284266392
Short name	T258
Test name
Test status
Simulation time	204582530 ps
CPU time	1.33 seconds
Started	Sep 24 08:42:54 AM UTC 24
Finished	Sep 24 08:42:56 AM UTC 24
Peak memory	209472 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284266392 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wakeup_race.4284266392
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_lowpower_wakeup_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2622413481
Short name	T91
Test name
Test status
Simulation time	62423573 ps
CPU time	1.03 seconds
Started	Sep 24 08:42:54 AM UTC 24
Finished	Sep 24 08:42:56 AM UTC 24
Peak memory	208676 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622413481 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.2622413481
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.30697627
Short name	T270
Test name
Test status
Simulation time	172877283 ps
CPU time	1.07 seconds
Started	Sep 24 08:42:56 AM UTC 24
Finished	Sep 24 08:42:58 AM UTC 24
Peak memory	220428 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30697627 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.30697627
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_reset_invalid/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3715069896
Short name	T264
Test name
Test status
Simulation time	168958632 ps
CPU time	1.29 seconds
Started	Sep 24 08:42:54 AM UTC 24
Finished	Sep 24 08:42:56 AM UTC 24
Peak memory	209740 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715069896 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_ctrl_config_regwen.3715069896
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1388244080
Short name	T265
Test name
Test status
Simulation time	2013165098 ps
CPU time	2.16 seconds
Started	Sep 24 08:42:54 AM UTC 24
Finished	Sep 24 08:42:57 AM UTC 24
Peak memory	211576 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388244080 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.1388244080
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2491733774
Short name	T267
Test name
Test status
Simulation time	2893747474 ps
CPU time	2.25 seconds
Started	Sep 24 08:42:54 AM UTC 24
Finished	Sep 24 08:42:57 AM UTC 24
Peak memory	211512 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491733774 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.2491733774
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3171986090
Short name	T260
Test name
Test status
Simulation time	194573845 ps
CPU time	1.16 seconds
Started	Sep 24 08:42:54 AM UTC 24
Finished	Sep 24 08:42:56 AM UTC 24
Peak memory	209152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171986090 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3171986090
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.4086411349
Short name	T90
Test name
Test status
Simulation time	30534888 ps
CPU time	0.96 seconds
Started	Sep 24 08:42:54 AM UTC 24
Finished	Sep 24 08:42:56 AM UTC 24
Peak memory	208916 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086411349 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.4086411349
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.422675605
Short name	T291
Test name
Test status
Simulation time	4398708366 ps
CPU time	4.57 seconds
Started	Sep 24 08:42:59 AM UTC 24
Finished	Sep 24 08:43:05 AM UTC 24
Peak memory	211596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422675605 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.422675605
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.3581797501
Short name	T79
Test name
Test status
Simulation time	5292474096 ps
CPU time	9.35 seconds
Started	Sep 24 08:42:56 AM UTC 24
Finished	Sep 24 08:43:06 AM UTC 24
Peak memory	211756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3581797501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr _stress_all_with_rand_reset.3581797501
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.1776654943
Short name	T261
Test name
Test status
Simulation time	256691907 ps
CPU time	1.51 seconds
Started	Sep 24 08:42:54 AM UTC 24
Finished	Sep 24 08:42:56 AM UTC 24
Peak memory	209732 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776654943 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.1776654943
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_wakeup/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.2509667889
Short name	T262
Test name
Test status
Simulation time	487840156 ps
CPU time	1.38 seconds
Started	Sep 24 08:42:54 AM UTC 24
Finished	Sep 24 08:42:56 AM UTC 24
Peak memory	210564 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509667889 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.2509667889
Directory	/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/9.pwrmgr_wakeup_reset/latest