| T810 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all_with_rand_reset.3876396657 |
|
|
Sep 24 08:45:59 AM UTC 24 |
Sep 24 08:46:15 AM UTC 24 |
17461342715 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.1841918033 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:16 AM UTC 24 |
43939259 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.953677535 |
|
|
Sep 24 08:46:14 AM UTC 24 |
Sep 24 08:46:16 AM UTC 24 |
29060479 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3667747622 |
|
|
Sep 24 08:46:14 AM UTC 24 |
Sep 24 08:46:16 AM UTC 24 |
95834074 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.3045069346 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:16 AM UTC 24 |
61336864 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.3749748260 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:16 AM UTC 24 |
59218502 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.967801965 |
|
|
Sep 24 08:46:31 AM UTC 24 |
Sep 24 08:46:32 AM UTC 24 |
58934889 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.2864634022 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
116041522 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.4031363849 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:32 AM UTC 24 |
73732790 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.2135106035 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
45972492 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.4031679903 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
172486849 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.3809429373 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
64053644 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.265392783 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
32514594 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.2588934446 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
157618365 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.669335182 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
44718976 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.322508746 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
98368316 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.2002781613 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
38164718 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.331550425 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
98767960 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.3246136736 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
31773002 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.1998799750 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
400016228 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.1514324917 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
54496030 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.941590616 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
41347184 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.103793158 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
37545202 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.3282018053 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
109770860 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.2452324124 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
64505571 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.2461477269 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
274692189 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.4186455376 |
|
|
Sep 24 08:46:16 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
103335337 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.3546676307 |
|
|
Sep 24 08:46:16 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
154874310 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.3428762027 |
|
|
Sep 24 08:46:16 AM UTC 24 |
Sep 24 08:46:17 AM UTC 24 |
205624760 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.4216931482 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:18 AM UTC 24 |
316380013 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.4158409263 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:19 AM UTC 24 |
1779115699 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3040346547 |
|
|
Sep 24 08:46:14 AM UTC 24 |
Sep 24 08:46:19 AM UTC 24 |
909607679 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3603671264 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:19 AM UTC 24 |
826588610 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3965786519 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:19 AM UTC 24 |
864958527 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.2336013396 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:23 AM UTC 24 |
2690867758 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.1052942306 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:23 AM UTC 24 |
2311615665 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.1365473732 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:31 AM UTC 24 |
27931839 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.1907651196 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:31 AM UTC 24 |
32579943 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.270464302 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:31 AM UTC 24 |
51161707 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.225500245 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:32 AM UTC 24 |
51655359 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.1049865423 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:32 AM UTC 24 |
59759900 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.1479984048 |
|
|
Sep 24 08:46:31 AM UTC 24 |
Sep 24 08:46:32 AM UTC 24 |
104928933 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.2506063376 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:32 AM UTC 24 |
51323322 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.860477867 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:32 AM UTC 24 |
109793754 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.1208622087 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:32 AM UTC 24 |
155809613 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.2948503588 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:32 AM UTC 24 |
263349609 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.1749623385 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:32 AM UTC 24 |
55001674 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.870058392 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:32 AM UTC 24 |
39357001 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.1904211454 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:32 AM UTC 24 |
47322298 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.4165915545 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:32 AM UTC 24 |
77312390 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.2802624320 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:32 AM UTC 24 |
30051437 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.2664532643 |
|
|
Sep 24 08:46:31 AM UTC 24 |
Sep 24 08:46:33 AM UTC 24 |
60793920 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_smoke.2516090977 |
|
|
Sep 24 08:46:31 AM UTC 24 |
Sep 24 08:46:33 AM UTC 24 |
65561587 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.3587155250 |
|
|
Sep 24 08:46:31 AM UTC 24 |
Sep 24 08:46:33 AM UTC 24 |
305152366 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.2043233285 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:33 AM UTC 24 |
247628880 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.3035233455 |
|
|
Sep 24 08:46:31 AM UTC 24 |
Sep 24 08:46:33 AM UTC 24 |
941227552 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset_invalid.367841322 |
|
|
Sep 24 08:46:31 AM UTC 24 |
Sep 24 08:46:33 AM UTC 24 |
111583795 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset.4204499077 |
|
|
Sep 24 08:46:31 AM UTC 24 |
Sep 24 08:46:33 AM UTC 24 |
182249925 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.2335907130 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:33 AM UTC 24 |
346453577 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2843238879 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:33 AM UTC 24 |
1195851692 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2450804445 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:33 AM UTC 24 |
892756696 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.4085560982 |
|
|
Sep 24 08:46:15 AM UTC 24 |
Sep 24 08:46:34 AM UTC 24 |
4710289583 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3457129766 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:34 AM UTC 24 |
795832604 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4015627204 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:35 AM UTC 24 |
888058108 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all.3094584192 |
|
|
Sep 24 08:46:31 AM UTC 24 |
Sep 24 08:46:38 AM UTC 24 |
1818805411 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.1803521235 |
|
|
Sep 24 08:46:30 AM UTC 24 |
Sep 24 08:46:39 AM UTC 24 |
2431538301 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all_with_rand_reset.3291056208 |
|
|
Sep 24 08:46:31 AM UTC 24 |
Sep 24 08:46:42 AM UTC 24 |
7487062665 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.2758929925 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
81903732 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_wakeup_race.266822782 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
242743107 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.855432988 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
29834807 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.2496690720 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
108619202 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.2604096404 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
64380483 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.1528783868 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
39931444 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2865715932 |
|
|
Sep 24 08:47:04 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
31621426 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.2922375879 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
31000076 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_global_esc.2480624640 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
48614962 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.3888012667 |
|
|
Sep 24 08:47:04 AM UTC 24 |
Sep 24 08:47:06 AM UTC 24 |
246841504 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.3067184084 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
185949099 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.267601961 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
42821207 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.2468460809 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
391036573 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.133334993 |
|
|
Sep 24 08:47:04 AM UTC 24 |
Sep 24 08:47:06 AM UTC 24 |
72929909 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.2418733662 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
1348822541 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.2412657570 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
76007673 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.2653394948 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
161094879 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2313862766 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
173551140 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.3669415571 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
154807548 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.2200792957 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
30837733 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.2631813800 |
|
|
Sep 24 08:46:46 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
38067262 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.42798907 |
|
|
Sep 24 08:46:46 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
297476074 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.1605145752 |
|
|
Sep 24 08:46:46 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
56402372 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.4111689879 |
|
|
Sep 24 08:46:46 AM UTC 24 |
Sep 24 08:46:47 AM UTC 24 |
29331246 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset.3802339273 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:48 AM UTC 24 |
70629413 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.3924132089 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:06 AM UTC 24 |
31344932 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.2206350406 |
|
|
Sep 24 08:46:46 AM UTC 24 |
Sep 24 08:46:48 AM UTC 24 |
65409415 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_glitch.927260100 |
|
|
Sep 24 08:46:46 AM UTC 24 |
Sep 24 08:46:48 AM UTC 24 |
44494525 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.153030423 |
|
|
Sep 24 08:46:46 AM UTC 24 |
Sep 24 08:46:48 AM UTC 24 |
143943572 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.4120489866 |
|
|
Sep 24 08:46:46 AM UTC 24 |
Sep 24 08:46:48 AM UTC 24 |
686471870 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.763916210 |
|
|
Sep 24 08:46:46 AM UTC 24 |
Sep 24 08:46:48 AM UTC 24 |
76726006 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.4004367873 |
|
|
Sep 24 08:46:46 AM UTC 24 |
Sep 24 08:46:48 AM UTC 24 |
280138287 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.4154778709 |
|
|
Sep 24 08:46:46 AM UTC 24 |
Sep 24 08:46:48 AM UTC 24 |
203852361 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.23247263 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:49 AM UTC 24 |
771935118 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.368932178 |
|
|
Sep 24 08:46:46 AM UTC 24 |
Sep 24 08:46:49 AM UTC 24 |
921561149 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1900446152 |
|
|
Sep 24 08:46:46 AM UTC 24 |
Sep 24 08:46:49 AM UTC 24 |
1047794524 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3963183904 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:50 AM UTC 24 |
879061663 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.535166026 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:51 AM UTC 24 |
2241326651 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.585950905 |
|
|
Sep 24 08:46:45 AM UTC 24 |
Sep 24 08:46:52 AM UTC 24 |
3166707959 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.2659983353 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:04 AM UTC 24 |
32924526 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.2801852871 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
55099429 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.2790985942 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
98226308 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.133888423 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:06 AM UTC 24 |
169160839 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.2453601247 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
217581955 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.4077454614 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
67803867 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.1198531921 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
124985717 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.1643760517 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
57517851 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.3597854539 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
56810148 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.808144759 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
65867107 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.2435036952 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
59466278 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.707100369 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
157846123 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.1138442196 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
328707867 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.3831668693 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
27440853 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.3036155608 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
29343922 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.2017586509 |
|
|
Sep 24 08:47:04 AM UTC 24 |
Sep 24 08:47:05 AM UTC 24 |
30912091 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.2186938343 |
|
|
Sep 24 08:47:04 AM UTC 24 |
Sep 24 08:47:06 AM UTC 24 |
61527741 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.3306310371 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:06 AM UTC 24 |
884837530 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.3933657863 |
|
|
Sep 24 08:47:04 AM UTC 24 |
Sep 24 08:47:06 AM UTC 24 |
295478822 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3226303890 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:06 AM UTC 24 |
104839122 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.2863611058 |
|
|
Sep 24 08:47:04 AM UTC 24 |
Sep 24 08:47:06 AM UTC 24 |
112004636 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.3601913805 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:06 AM UTC 24 |
159358460 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.825376072 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:07 AM UTC 24 |
1192279853 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.646705611 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:07 AM UTC 24 |
711220244 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.4218269394 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:07 AM UTC 24 |
772126833 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3178524873 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:07 AM UTC 24 |
891657127 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.63525748 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:08 AM UTC 24 |
663009250 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.2615826985 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:08 AM UTC 24 |
729554187 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4229039802 |
|
|
Sep 24 08:47:03 AM UTC 24 |
Sep 24 08:47:08 AM UTC 24 |
871152840 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all_with_rand_reset.975533375 |
|
|
Sep 24 08:47:04 AM UTC 24 |
Sep 24 08:47:17 AM UTC 24 |
3284634772 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.2784565616 |
|
|
Sep 24 08:47:20 AM UTC 24 |
Sep 24 08:47:22 AM UTC 24 |
58123129 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.1769620097 |
|
|
Sep 24 08:47:20 AM UTC 24 |
Sep 24 08:47:22 AM UTC 24 |
31175463 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.1659408656 |
|
|
Sep 24 08:47:20 AM UTC 24 |
Sep 24 08:47:22 AM UTC 24 |
181011224 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3412222755 |
|
|
Sep 24 08:47:20 AM UTC 24 |
Sep 24 08:47:22 AM UTC 24 |
39381368 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.1578155251 |
|
|
Sep 24 08:47:20 AM UTC 24 |
Sep 24 08:47:22 AM UTC 24 |
198357356 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.2751475118 |
|
|
Sep 24 08:47:20 AM UTC 24 |
Sep 24 08:47:22 AM UTC 24 |
62785625 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.2582170114 |
|
|
Sep 24 08:47:21 AM UTC 24 |
Sep 24 08:47:23 AM UTC 24 |
81737665 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.3544076081 |
|
|
Sep 24 08:47:20 AM UTC 24 |
Sep 24 08:47:23 AM UTC 24 |
73517102 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.3863997605 |
|
|
Sep 24 08:47:21 AM UTC 24 |
Sep 24 08:47:23 AM UTC 24 |
49138020 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.1612199424 |
|
|
Sep 24 08:47:20 AM UTC 24 |
Sep 24 08:47:23 AM UTC 24 |
171418174 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.557884580 |
|
|
Sep 24 08:47:21 AM UTC 24 |
Sep 24 08:47:23 AM UTC 24 |
59887783 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.3608130067 |
|
|
Sep 24 08:47:21 AM UTC 24 |
Sep 24 08:47:23 AM UTC 24 |
370945693 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.3958776526 |
|
|
Sep 24 08:47:21 AM UTC 24 |
Sep 24 08:47:23 AM UTC 24 |
65245593 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.2520329757 |
|
|
Sep 24 08:47:21 AM UTC 24 |
Sep 24 08:47:23 AM UTC 24 |
101390784 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.3042074697 |
|
|
Sep 24 08:47:21 AM UTC 24 |
Sep 24 08:47:23 AM UTC 24 |
241698660 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4102114158 |
|
|
Sep 24 08:47:20 AM UTC 24 |
Sep 24 08:47:24 AM UTC 24 |
1310952531 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1099155212 |
|
|
Sep 24 08:47:20 AM UTC 24 |
Sep 24 08:47:25 AM UTC 24 |
818352196 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.1839887242 |
|
|
Sep 24 08:47:20 AM UTC 24 |
Sep 24 08:47:27 AM UTC 24 |
2540440463 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.54072315 |
|
|
Sep 24 08:47:21 AM UTC 24 |
Sep 24 08:47:28 AM UTC 24 |
3239676233 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.1345946408 |
|
|
Sep 24 06:49:44 AM UTC 24 |
Sep 24 06:49:46 AM UTC 24 |
43312102 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2066078902 |
|
|
Sep 24 06:49:43 AM UTC 24 |
Sep 24 06:49:46 AM UTC 24 |
193038582 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1870281876 |
|
|
Sep 24 06:49:45 AM UTC 24 |
Sep 24 06:49:47 AM UTC 24 |
224124190 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.1325557578 |
|
|
Sep 24 06:49:43 AM UTC 24 |
Sep 24 06:49:47 AM UTC 24 |
473542226 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.147074353 |
|
|
Sep 24 06:49:45 AM UTC 24 |
Sep 24 06:49:47 AM UTC 24 |
19682901 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2180805228 |
|
|
Sep 24 06:49:45 AM UTC 24 |
Sep 24 06:49:47 AM UTC 24 |
52452594 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.4215523048 |
|
|
Sep 24 06:49:46 AM UTC 24 |
Sep 24 06:49:48 AM UTC 24 |
215506475 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1165974938 |
|
|
Sep 24 06:49:46 AM UTC 24 |
Sep 24 06:49:48 AM UTC 24 |
50061278 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1604201474 |
|
|
Sep 24 06:49:45 AM UTC 24 |
Sep 24 06:49:48 AM UTC 24 |
171929260 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3274684894 |
|
|
Sep 24 06:49:46 AM UTC 24 |
Sep 24 06:49:49 AM UTC 24 |
591996485 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.3747466034 |
|
|
Sep 24 06:49:57 AM UTC 24 |
Sep 24 06:49:59 AM UTC 24 |
67918764 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.1050060588 |
|
|
Sep 24 06:49:46 AM UTC 24 |
Sep 24 06:49:49 AM UTC 24 |
226656151 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.2204485987 |
|
|
Sep 24 06:49:47 AM UTC 24 |
Sep 24 06:49:49 AM UTC 24 |
24344051 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.3874215152 |
|
|
Sep 24 06:49:47 AM UTC 24 |
Sep 24 06:49:49 AM UTC 24 |
23209333 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3948523622 |
|
|
Sep 24 06:49:47 AM UTC 24 |
Sep 24 06:49:49 AM UTC 24 |
42836942 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.71125213 |
|
|
Sep 24 06:49:48 AM UTC 24 |
Sep 24 06:49:49 AM UTC 24 |
60314980 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3043550442 |
|
|
Sep 24 06:49:48 AM UTC 24 |
Sep 24 06:49:50 AM UTC 24 |
98251621 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.2395720516 |
|
|
Sep 24 06:49:49 AM UTC 24 |
Sep 24 06:49:51 AM UTC 24 |
39641217 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.170226711 |
|
|
Sep 24 06:49:48 AM UTC 24 |
Sep 24 06:49:51 AM UTC 24 |
122180077 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.748580289 |
|
|
Sep 24 06:49:49 AM UTC 24 |
Sep 24 06:49:51 AM UTC 24 |
68869297 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.582947703 |
|
|
Sep 24 06:49:49 AM UTC 24 |
Sep 24 06:49:51 AM UTC 24 |
25269643 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.478906218 |
|
|
Sep 24 06:49:49 AM UTC 24 |
Sep 24 06:49:51 AM UTC 24 |
82787752 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2595678358 |
|
|
Sep 24 06:49:49 AM UTC 24 |
Sep 24 06:49:51 AM UTC 24 |
51616870 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.1603976977 |
|
|
Sep 24 06:49:49 AM UTC 24 |
Sep 24 06:49:51 AM UTC 24 |
45415205 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1130403006 |
|
|
Sep 24 06:49:49 AM UTC 24 |
Sep 24 06:49:52 AM UTC 24 |
851928086 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.513041513 |
|
|
Sep 24 06:49:50 AM UTC 24 |
Sep 24 06:49:52 AM UTC 24 |
20855465 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3506863521 |
|
|
Sep 24 06:49:50 AM UTC 24 |
Sep 24 06:49:52 AM UTC 24 |
276659279 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.1990384357 |
|
|
Sep 24 06:49:50 AM UTC 24 |
Sep 24 06:49:52 AM UTC 24 |
19960879 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2244263524 |
|
|
Sep 24 06:49:50 AM UTC 24 |
Sep 24 06:49:53 AM UTC 24 |
123297914 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3504061167 |
|
|
Sep 24 06:49:50 AM UTC 24 |
Sep 24 06:49:53 AM UTC 24 |
116267232 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.321766992 |
|
|
Sep 24 06:49:51 AM UTC 24 |
Sep 24 06:49:53 AM UTC 24 |
138885812 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.1452367436 |
|
|
Sep 24 06:49:50 AM UTC 24 |
Sep 24 06:49:53 AM UTC 24 |
41205551 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1417326557 |
|
|
Sep 24 06:49:51 AM UTC 24 |
Sep 24 06:49:53 AM UTC 24 |
131102065 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3087637464 |
|
|
Sep 24 06:49:50 AM UTC 24 |
Sep 24 06:49:53 AM UTC 24 |
492117944 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.479151344 |
|
|
Sep 24 06:49:51 AM UTC 24 |
Sep 24 06:49:53 AM UTC 24 |
129657190 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.3966745771 |
|
|
Sep 24 06:49:51 AM UTC 24 |
Sep 24 06:49:53 AM UTC 24 |
155901602 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2384324597 |
|
|
Sep 24 06:49:49 AM UTC 24 |
Sep 24 06:49:53 AM UTC 24 |
221156007 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.4282915834 |
|
|
Sep 24 06:49:52 AM UTC 24 |
Sep 24 06:49:54 AM UTC 24 |
24837707 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.1066221481 |
|
|
Sep 24 06:49:52 AM UTC 24 |
Sep 24 06:49:54 AM UTC 24 |
20881035 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2261992864 |
|
|
Sep 24 06:49:51 AM UTC 24 |
Sep 24 06:49:54 AM UTC 24 |
900278804 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3410885834 |
|
|
Sep 24 06:49:52 AM UTC 24 |
Sep 24 06:49:54 AM UTC 24 |
132066127 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.2146964634 |
|
|
Sep 24 06:49:52 AM UTC 24 |
Sep 24 06:49:54 AM UTC 24 |
17038634 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2848342799 |
|
|
Sep 24 06:49:52 AM UTC 24 |
Sep 24 06:49:54 AM UTC 24 |
51030523 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2883522561 |
|
|
Sep 24 06:49:52 AM UTC 24 |
Sep 24 06:49:54 AM UTC 24 |
35985165 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1950085286 |
|
|
Sep 24 06:49:52 AM UTC 24 |
Sep 24 06:49:54 AM UTC 24 |
111626251 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.389505583 |
|
|
Sep 24 06:49:52 AM UTC 24 |
Sep 24 06:49:55 AM UTC 24 |
158154705 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.1259111192 |
|
|
Sep 24 06:49:57 AM UTC 24 |
Sep 24 06:49:59 AM UTC 24 |
86668904 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.2726440360 |
|
|
Sep 24 06:49:53 AM UTC 24 |
Sep 24 06:49:55 AM UTC 24 |
21057362 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.1451347121 |
|
|
Sep 24 06:49:51 AM UTC 24 |
Sep 24 06:49:55 AM UTC 24 |
627796935 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1066335177 |
|
|
Sep 24 06:49:52 AM UTC 24 |
Sep 24 06:49:55 AM UTC 24 |
736478950 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.2127874997 |
|
|
Sep 24 06:49:53 AM UTC 24 |
Sep 24 06:49:55 AM UTC 24 |
42784018 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1287399237 |
|
|
Sep 24 06:49:53 AM UTC 24 |
Sep 24 06:49:56 AM UTC 24 |
80867604 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.366754439 |
|
|
Sep 24 06:49:54 AM UTC 24 |
Sep 24 06:49:56 AM UTC 24 |
18969007 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.751429809 |
|
|
Sep 24 06:49:54 AM UTC 24 |
Sep 24 06:49:56 AM UTC 24 |
19631701 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.4105444103 |
|
|
Sep 24 06:49:54 AM UTC 24 |
Sep 24 06:49:56 AM UTC 24 |
97353493 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.1804452201 |
|
|
Sep 24 06:49:52 AM UTC 24 |
Sep 24 06:49:56 AM UTC 24 |
475056472 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.767325933 |
|
|
Sep 24 06:49:54 AM UTC 24 |
Sep 24 06:49:56 AM UTC 24 |
58645670 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2195408732 |
|
|
Sep 24 06:49:54 AM UTC 24 |
Sep 24 06:49:56 AM UTC 24 |
580827423 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1996235232 |
|
|
Sep 24 06:49:54 AM UTC 24 |
Sep 24 06:49:56 AM UTC 24 |
355450912 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1056939976 |
|
|
Sep 24 06:49:54 AM UTC 24 |
Sep 24 06:49:56 AM UTC 24 |
51577602 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2417026789 |
|
|
Sep 24 06:49:54 AM UTC 24 |
Sep 24 06:49:56 AM UTC 24 |
280249165 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1761275928 |
|
|
Sep 24 06:49:57 AM UTC 24 |
Sep 24 06:49:59 AM UTC 24 |
71272481 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.2859765842 |
|
|
Sep 24 06:49:54 AM UTC 24 |
Sep 24 06:49:57 AM UTC 24 |
76362962 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1840447812 |
|
|
Sep 24 06:49:55 AM UTC 24 |
Sep 24 06:49:57 AM UTC 24 |
28852459 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.394543835 |
|
|
Sep 24 06:49:55 AM UTC 24 |
Sep 24 06:49:57 AM UTC 24 |
30373167 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.267254628 |
|
|
Sep 24 06:49:55 AM UTC 24 |
Sep 24 06:49:57 AM UTC 24 |
52232730 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.2536751976 |
|
|
Sep 24 06:49:55 AM UTC 24 |
Sep 24 06:49:57 AM UTC 24 |
17847833 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.4283544386 |
|
|
Sep 24 06:49:55 AM UTC 24 |
Sep 24 06:49:57 AM UTC 24 |
120183649 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2901546314 |
|
|
Sep 24 06:49:55 AM UTC 24 |
Sep 24 06:49:57 AM UTC 24 |
75660481 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.3012442526 |
|
|
Sep 24 06:49:54 AM UTC 24 |
Sep 24 06:49:58 AM UTC 24 |
271365630 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.827029778 |
|
|
Sep 24 06:49:55 AM UTC 24 |
Sep 24 06:49:58 AM UTC 24 |
177727837 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.209732658 |
|
|
Sep 24 06:49:55 AM UTC 24 |
Sep 24 06:49:58 AM UTC 24 |
232757066 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.116333318 |
|
|
Sep 24 06:49:55 AM UTC 24 |
Sep 24 06:49:58 AM UTC 24 |
42324487 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.749512847 |
|
|
Sep 24 06:49:57 AM UTC 24 |
Sep 24 06:49:58 AM UTC 24 |
29610000 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.414384592 |
|
|
Sep 24 06:49:56 AM UTC 24 |
Sep 24 06:49:58 AM UTC 24 |
119728108 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.3589536470 |
|
|
Sep 24 06:49:57 AM UTC 24 |
Sep 24 06:49:58 AM UTC 24 |
31153193 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.416776958 |
|
|
Sep 24 06:49:57 AM UTC 24 |
Sep 24 06:49:59 AM UTC 24 |
19106417 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.109312025 |
|
|
Sep 24 06:49:55 AM UTC 24 |
Sep 24 06:49:59 AM UTC 24 |
143060085 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.4261409062 |
|
|
Sep 24 06:49:57 AM UTC 24 |
Sep 24 06:49:59 AM UTC 24 |
112661353 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.3030724358 |
|
|
Sep 24 06:49:57 AM UTC 24 |
Sep 24 06:49:59 AM UTC 24 |
19632430 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.1986918434 |
|
|
Sep 24 06:49:58 AM UTC 24 |
Sep 24 06:50:00 AM UTC 24 |
51083035 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2492391881 |
|
|
Sep 24 06:49:57 AM UTC 24 |
Sep 24 06:49:59 AM UTC 24 |
40523815 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1124062539 |
|
|
Sep 24 06:49:57 AM UTC 24 |
Sep 24 06:49:59 AM UTC 24 |
203723507 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.1437557114 |
|
|
Sep 24 06:49:58 AM UTC 24 |
Sep 24 06:50:00 AM UTC 24 |
44139913 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.999190807 |
|
|
Sep 24 06:49:57 AM UTC 24 |
Sep 24 06:50:00 AM UTC 24 |
199076686 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3026138273 |
|
|
Sep 24 06:49:58 AM UTC 24 |
Sep 24 06:50:00 AM UTC 24 |
32712320 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.621812116 |
|
|
Sep 24 06:49:58 AM UTC 24 |
Sep 24 06:50:00 AM UTC 24 |
22792763 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.2396367978 |
|
|
Sep 24 06:49:58 AM UTC 24 |
Sep 24 06:50:00 AM UTC 24 |
17253919 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.3794161470 |
|
|
Sep 24 06:49:58 AM UTC 24 |
Sep 24 06:50:00 AM UTC 24 |
63366953 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.1142259982 |
|
|
Sep 24 06:49:58 AM UTC 24 |
Sep 24 06:50:00 AM UTC 24 |
146945614 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3630415163 |
|
|
Sep 24 06:49:58 AM UTC 24 |
Sep 24 06:50:00 AM UTC 24 |
56529576 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.944942927 |
|
|
Sep 24 06:49:58 AM UTC 24 |
Sep 24 06:50:01 AM UTC 24 |
412529097 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.2159273777 |
|
|
Sep 24 06:49:58 AM UTC 24 |
Sep 24 06:50:01 AM UTC 24 |
116228127 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.3287364384 |
|
|
Sep 24 06:50:06 AM UTC 24 |
Sep 24 06:50:08 AM UTC 24 |
49974558 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.107354446 |
|
|
Sep 24 06:50:00 AM UTC 24 |
Sep 24 06:50:01 AM UTC 24 |
21223240 ps |