| T326 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset_invalid.967655945 |
|
|
Oct 02 10:53:39 PM UTC 24 |
Oct 02 10:53:41 PM UTC 24 |
158032171 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.699969296 |
|
|
Oct 02 10:53:39 PM UTC 24 |
Oct 02 10:53:41 PM UTC 24 |
133324190 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.1207969253 |
|
|
Oct 02 10:53:40 PM UTC 24 |
Oct 02 10:53:41 PM UTC 24 |
157176753 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset.1676925631 |
|
|
Oct 02 10:53:40 PM UTC 24 |
Oct 02 10:53:42 PM UTC 24 |
50402029 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup_reset.2886386805 |
|
|
Oct 02 10:53:45 PM UTC 24 |
Oct 02 10:53:47 PM UTC 24 |
208221333 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_smoke.1945830843 |
|
|
Oct 02 10:53:39 PM UTC 24 |
Oct 02 10:53:42 PM UTC 24 |
29755308 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_wakeup_race.3937636378 |
|
|
Oct 02 10:53:40 PM UTC 24 |
Oct 02 10:53:42 PM UTC 24 |
65525057 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1479177086 |
|
|
Oct 02 10:53:38 PM UTC 24 |
Oct 02 10:53:42 PM UTC 24 |
921761086 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.3286343709 |
|
|
Oct 02 10:53:40 PM UTC 24 |
Oct 02 10:53:42 PM UTC 24 |
67378206 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup.2239331578 |
|
|
Oct 02 10:53:40 PM UTC 24 |
Oct 02 10:53:42 PM UTC 24 |
246219593 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all.1242904265 |
|
|
Oct 02 10:53:39 PM UTC 24 |
Oct 02 10:53:42 PM UTC 24 |
578531901 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.2127499146 |
|
|
Oct 02 10:53:34 PM UTC 24 |
Oct 02 10:53:42 PM UTC 24 |
8704208911 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all.2792800544 |
|
|
Oct 02 10:53:37 PM UTC 24 |
Oct 02 10:53:42 PM UTC 24 |
5548622813 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.791873072 |
|
|
Oct 02 10:53:41 PM UTC 24 |
Oct 02 10:53:43 PM UTC 24 |
30071734 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.3341868413 |
|
|
Oct 02 10:53:41 PM UTC 24 |
Oct 02 10:53:43 PM UTC 24 |
50853356 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_global_esc.4178363431 |
|
|
Oct 02 10:53:41 PM UTC 24 |
Oct 02 10:53:43 PM UTC 24 |
85646147 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_escalation_timeout.4013325981 |
|
|
Oct 02 10:53:45 PM UTC 24 |
Oct 02 10:53:47 PM UTC 24 |
112932922 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3821903155 |
|
|
Oct 02 10:53:41 PM UTC 24 |
Oct 02 10:53:43 PM UTC 24 |
98505544 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.3108903800 |
|
|
Oct 02 10:53:41 PM UTC 24 |
Oct 02 10:53:43 PM UTC 24 |
228430764 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.1520997316 |
|
|
Oct 02 10:53:41 PM UTC 24 |
Oct 02 10:53:43 PM UTC 24 |
58930635 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_escalation_timeout.970813327 |
|
|
Oct 02 10:53:41 PM UTC 24 |
Oct 02 10:53:43 PM UTC 24 |
109358451 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.2174852661 |
|
|
Oct 02 10:53:41 PM UTC 24 |
Oct 02 10:53:43 PM UTC 24 |
114384461 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1098345860 |
|
|
Oct 02 10:53:40 PM UTC 24 |
Oct 02 10:53:44 PM UTC 24 |
952926441 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all_with_rand_reset.1311303315 |
|
|
Oct 02 10:53:37 PM UTC 24 |
Oct 02 10:53:44 PM UTC 24 |
3808511189 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset.3988842727 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:44 PM UTC 24 |
49226474 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.3995687759 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
41446764 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_wakeup_race.181043380 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
308963433 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3163582002 |
|
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Oct 02 10:53:41 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
865216383 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_aborted_low_power.4070696137 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
107547706 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.3953855095 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
30353245 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup_reset.1868242860 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
147123585 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_global_esc.517464417 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
36742158 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.242028784 |
|
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Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
98367656 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset.1864165126 |
|
|
Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:48 PM UTC 24 |
67813653 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all.2491295573 |
|
|
Oct 02 10:53:41 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
627392330 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.3336643743 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
382425566 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup.1052678073 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
254135240 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.4216049896 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
117427629 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.3091005402 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
85867078 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.356030227 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
362850854 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.3055334601 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
56606084 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.2934566020 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:47 PM UTC 24 |
987358537 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.1648775141 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
69164436 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset_invalid.1036855939 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:45 PM UTC 24 |
116694839 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_wakeup_race.819045173 |
|
|
Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:46 PM UTC 24 |
423846059 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1529581031 |
|
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Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:46 PM UTC 24 |
1337006314 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2025266731 |
|
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Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:47 PM UTC 24 |
975053205 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_aborted_low_power.2894187646 |
|
|
Oct 02 10:53:45 PM UTC 24 |
Oct 02 10:53:47 PM UTC 24 |
32232678 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.4228747610 |
|
|
Oct 02 10:53:45 PM UTC 24 |
Oct 02 10:53:47 PM UTC 24 |
33167526 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.1493252521 |
|
|
Oct 02 10:53:45 PM UTC 24 |
Oct 02 10:53:47 PM UTC 24 |
231580668 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.3235914194 |
|
|
Oct 02 10:53:45 PM UTC 24 |
Oct 02 10:53:47 PM UTC 24 |
230586726 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_global_esc.2874340761 |
|
|
Oct 02 10:53:45 PM UTC 24 |
Oct 02 10:53:47 PM UTC 24 |
72600440 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.1920555531 |
|
|
Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:48 PM UTC 24 |
48968133 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.3639088067 |
|
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Oct 02 10:53:45 PM UTC 24 |
Oct 02 10:53:47 PM UTC 24 |
72450438 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2996054975 |
|
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Oct 02 10:53:45 PM UTC 24 |
Oct 02 10:53:47 PM UTC 24 |
68742966 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.1855498653 |
|
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Oct 02 10:53:43 PM UTC 24 |
Oct 02 10:53:48 PM UTC 24 |
2570888553 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.513323635 |
|
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Oct 02 10:53:45 PM UTC 24 |
Oct 02 10:53:48 PM UTC 24 |
991524991 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.576825080 |
|
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Oct 02 10:53:45 PM UTC 24 |
Oct 02 10:53:48 PM UTC 24 |
950158882 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_aborted_low_power.1968119834 |
|
|
Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:48 PM UTC 24 |
118140409 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_wakeup_race.626216213 |
|
|
Oct 02 10:54:11 PM UTC 24 |
Oct 02 10:54:20 PM UTC 24 |
34528377 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup.2019460581 |
|
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Oct 02 10:54:12 PM UTC 24 |
Oct 02 10:54:25 PM UTC 24 |
58075912 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset_invalid.2254030472 |
|
|
Oct 02 10:53:46 PM UTC 24 |
Oct 02 10:53:49 PM UTC 24 |
155568794 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup_reset.1273546 |
|
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Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:49 PM UTC 24 |
156554890 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset.1053431144 |
|
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Oct 02 10:54:31 PM UTC 24 |
Oct 02 10:54:40 PM UTC 24 |
88686488 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.268388856 |
|
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Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:49 PM UTC 24 |
39840492 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_global_esc.3794532282 |
|
|
Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:49 PM UTC 24 |
47396584 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup.3137550603 |
|
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Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:49 PM UTC 24 |
199491442 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_glitch.2534623813 |
|
|
Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:49 PM UTC 24 |
55524996 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_wakeup_race.3938075050 |
|
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Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:49 PM UTC 24 |
153886184 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.1962200910 |
|
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Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:49 PM UTC 24 |
60910985 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_escalation_timeout.3312328206 |
|
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Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:49 PM UTC 24 |
440806522 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1367835684 |
|
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Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:49 PM UTC 24 |
66097294 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset_invalid.2803599065 |
|
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Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:49 PM UTC 24 |
125411256 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.879469798 |
|
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Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:49 PM UTC 24 |
316215970 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.245869010 |
|
|
Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:50 PM UTC 24 |
1151700787 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_invalid.759195637 |
|
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Oct 02 10:53:48 PM UTC 24 |
Oct 02 10:53:50 PM UTC 24 |
58185384 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_smoke.3109377923 |
|
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Oct 02 10:54:11 PM UTC 24 |
Oct 02 10:54:20 PM UTC 24 |
66570782 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset.2869657373 |
|
|
Oct 02 10:54:11 PM UTC 24 |
Oct 02 10:54:20 PM UTC 24 |
40442594 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_smoke.3905403851 |
|
|
Oct 02 10:53:49 PM UTC 24 |
Oct 02 10:53:50 PM UTC 24 |
54635805 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1078585780 |
|
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Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:50 PM UTC 24 |
908375678 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset.2122079984 |
|
|
Oct 02 10:53:49 PM UTC 24 |
Oct 02 10:53:50 PM UTC 24 |
31472062 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup.2870050879 |
|
|
Oct 02 10:53:49 PM UTC 24 |
Oct 02 10:53:50 PM UTC 24 |
75244396 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all.910712058 |
|
|
Oct 02 10:53:47 PM UTC 24 |
Oct 02 10:53:50 PM UTC 24 |
1863180975 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.3436831557 |
|
|
Oct 02 10:53:49 PM UTC 24 |
Oct 02 10:53:50 PM UTC 24 |
100060757 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_wakeup_race.2852850422 |
|
|
Oct 02 10:53:49 PM UTC 24 |
Oct 02 10:53:51 PM UTC 24 |
331061242 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup_reset.1613849176 |
|
|
Oct 02 10:53:49 PM UTC 24 |
Oct 02 10:53:51 PM UTC 24 |
194101429 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_aborted_low_power.3832259029 |
|
|
Oct 02 10:53:49 PM UTC 24 |
Oct 02 10:53:51 PM UTC 24 |
66331366 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.4007086666 |
|
|
Oct 02 10:53:49 PM UTC 24 |
Oct 02 10:53:51 PM UTC 24 |
29301703 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_global_esc.4211402605 |
|
|
Oct 02 10:53:49 PM UTC 24 |
Oct 02 10:53:51 PM UTC 24 |
37541762 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1889289237 |
|
|
Oct 02 10:53:49 PM UTC 24 |
Oct 02 10:53:51 PM UTC 24 |
65848027 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_escalation_timeout.2237062492 |
|
|
Oct 02 10:53:49 PM UTC 24 |
Oct 02 10:53:51 PM UTC 24 |
112869497 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all.625408178 |
|
|
Oct 02 10:53:48 PM UTC 24 |
Oct 02 10:53:51 PM UTC 24 |
736363727 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_glitch.4044730464 |
|
|
Oct 02 10:53:50 PM UTC 24 |
Oct 02 10:53:52 PM UTC 24 |
64564170 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_disable_rom_integrity_check.2598368549 |
|
|
Oct 02 10:53:50 PM UTC 24 |
Oct 02 10:53:52 PM UTC 24 |
76304693 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all_with_rand_reset.815199579 |
|
|
Oct 02 10:53:46 PM UTC 24 |
Oct 02 10:53:52 PM UTC 24 |
994327661 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_glitch.3042899430 |
|
|
Oct 02 10:54:22 PM UTC 24 |
Oct 02 10:54:31 PM UTC 24 |
46400219 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset_invalid.3256427334 |
|
|
Oct 02 10:53:50 PM UTC 24 |
Oct 02 10:53:52 PM UTC 24 |
124708684 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1281911631 |
|
|
Oct 02 10:53:49 PM UTC 24 |
Oct 02 10:53:53 PM UTC 24 |
831011541 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.3407021949 |
|
|
Oct 02 10:53:39 PM UTC 24 |
Oct 02 10:53:53 PM UTC 24 |
4678502530 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.343056468 |
|
|
Oct 02 10:53:49 PM UTC 24 |
Oct 02 10:53:53 PM UTC 24 |
814559369 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all_with_rand_reset.1198656267 |
|
|
Oct 02 10:53:41 PM UTC 24 |
Oct 02 10:53:53 PM UTC 24 |
2782908599 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.4111618529 |
|
|
Oct 02 10:53:51 PM UTC 24 |
Oct 02 10:53:59 PM UTC 24 |
38768615 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_aborted_low_power.3940310662 |
|
|
Oct 02 10:53:51 PM UTC 24 |
Oct 02 10:53:59 PM UTC 24 |
36864274 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.2952366594 |
|
|
Oct 02 10:53:51 PM UTC 24 |
Oct 02 10:54:00 PM UTC 24 |
51590940 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup.1436263215 |
|
|
Oct 02 10:53:51 PM UTC 24 |
Oct 02 10:54:00 PM UTC 24 |
293095404 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup_reset.3169543433 |
|
|
Oct 02 10:53:51 PM UTC 24 |
Oct 02 10:54:00 PM UTC 24 |
382685991 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4137215888 |
|
|
Oct 02 10:53:51 PM UTC 24 |
Oct 02 10:54:01 PM UTC 24 |
1938962243 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1515756230 |
|
|
Oct 02 10:53:51 PM UTC 24 |
Oct 02 10:54:02 PM UTC 24 |
870213070 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_glitch.4210587460 |
|
|
Oct 02 10:53:51 PM UTC 24 |
Oct 02 10:54:03 PM UTC 24 |
112191982 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_disable_rom_integrity_check.3749577998 |
|
|
Oct 02 10:53:51 PM UTC 24 |
Oct 02 10:54:03 PM UTC 24 |
66760464 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_aborted_low_power.2763826414 |
|
|
Oct 02 10:53:53 PM UTC 24 |
Oct 02 10:54:04 PM UTC 24 |
40156912 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3186393064 |
|
|
Oct 02 10:54:03 PM UTC 24 |
Oct 02 10:54:04 PM UTC 24 |
63802570 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all_with_rand_reset.3723219858 |
|
|
Oct 02 10:53:50 PM UTC 24 |
Oct 02 10:54:08 PM UTC 24 |
8226260467 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_wakeup_race.1473964177 |
|
|
Oct 02 10:53:51 PM UTC 24 |
Oct 02 10:54:09 PM UTC 24 |
85161324 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.2332295605 |
|
|
Oct 02 10:53:51 PM UTC 24 |
Oct 02 10:54:10 PM UTC 24 |
163314062 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_global_esc.2139088305 |
|
|
Oct 02 10:53:51 PM UTC 24 |
Oct 02 10:54:10 PM UTC 24 |
67538918 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_escalation_timeout.311848885 |
|
|
Oct 02 10:53:51 PM UTC 24 |
Oct 02 10:54:10 PM UTC 24 |
1590190690 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset.817143205 |
|
|
Oct 02 10:53:55 PM UTC 24 |
Oct 02 10:54:10 PM UTC 24 |
58893757 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_glitch.2536429732 |
|
|
Oct 02 10:54:09 PM UTC 24 |
Oct 02 10:54:11 PM UTC 24 |
121661198 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.2023069038 |
|
|
Oct 02 10:54:09 PM UTC 24 |
Oct 02 10:54:11 PM UTC 24 |
61093025 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.3445713913 |
|
|
Oct 02 10:53:53 PM UTC 24 |
Oct 02 10:54:11 PM UTC 24 |
39871644 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4110241667 |
|
|
Oct 02 10:54:02 PM UTC 24 |
Oct 02 10:54:12 PM UTC 24 |
984522298 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.3093212615 |
|
|
Oct 02 10:53:53 PM UTC 24 |
Oct 02 10:54:12 PM UTC 24 |
280906117 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset_invalid.1655584812 |
|
|
Oct 02 10:54:22 PM UTC 24 |
Oct 02 10:54:31 PM UTC 24 |
108607680 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset_invalid.784341857 |
|
|
Oct 02 10:54:10 PM UTC 24 |
Oct 02 10:54:15 PM UTC 24 |
212225732 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all.1721097854 |
|
|
Oct 02 10:54:10 PM UTC 24 |
Oct 02 10:54:20 PM UTC 24 |
2035921143 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1603282022 |
|
|
Oct 02 10:54:16 PM UTC 24 |
Oct 02 10:54:22 PM UTC 24 |
1176220924 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1852597361 |
|
|
Oct 02 10:54:16 PM UTC 24 |
Oct 02 10:54:22 PM UTC 24 |
1346747298 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all_with_rand_reset.1196939687 |
|
|
Oct 02 10:54:10 PM UTC 24 |
Oct 02 10:54:26 PM UTC 24 |
3233959167 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_disable_rom_integrity_check.3066693871 |
|
|
Oct 02 10:54:22 PM UTC 24 |
Oct 02 10:54:31 PM UTC 24 |
63077891 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all.2082251717 |
|
|
Oct 02 10:54:27 PM UTC 24 |
Oct 02 10:54:33 PM UTC 24 |
2346477776 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3052328999 |
|
|
Oct 02 10:54:20 PM UTC 24 |
Oct 02 10:54:35 PM UTC 24 |
313092797 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup_reset.3686684505 |
|
|
Oct 02 10:54:33 PM UTC 24 |
Oct 02 10:54:35 PM UTC 24 |
325167293 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3728690302 |
|
|
Oct 02 10:54:33 PM UTC 24 |
Oct 02 10:54:37 PM UTC 24 |
1003447012 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_wakeup_race.2280579588 |
|
|
Oct 02 10:54:31 PM UTC 24 |
Oct 02 10:54:40 PM UTC 24 |
284291234 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup.1079032319 |
|
|
Oct 02 10:54:31 PM UTC 24 |
Oct 02 10:54:40 PM UTC 24 |
336899206 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.2987919853 |
|
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Oct 02 10:55:08 PM UTC 24 |
Oct 02 10:55:10 PM UTC 24 |
73526077 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_smoke.4032711833 |
|
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Oct 02 10:54:29 PM UTC 24 |
Oct 02 10:54:41 PM UTC 24 |
57593174 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all.2632476807 |
|
|
Oct 02 10:54:36 PM UTC 24 |
Oct 02 10:54:41 PM UTC 24 |
78520676 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all_with_rand_reset.3300155755 |
|
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Oct 02 10:54:26 PM UTC 24 |
Oct 02 10:54:42 PM UTC 24 |
8395356687 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_smoke.4092301984 |
|
|
Oct 02 10:54:37 PM UTC 24 |
Oct 02 10:54:42 PM UTC 24 |
45865157 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_aborted_low_power.3160393918 |
|
|
Oct 02 10:54:33 PM UTC 24 |
Oct 02 10:54:42 PM UTC 24 |
156590909 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all_with_rand_reset.3515280598 |
|
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Oct 02 10:54:36 PM UTC 24 |
Oct 02 10:54:44 PM UTC 24 |
1650146733 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1851833677 |
|
|
Oct 02 10:54:34 PM UTC 24 |
Oct 02 10:54:44 PM UTC 24 |
1385738131 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_aborted_low_power.3050481978 |
|
|
Oct 02 10:54:43 PM UTC 24 |
Oct 02 10:54:45 PM UTC 24 |
90743981 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.152238383 |
|
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Oct 02 10:54:43 PM UTC 24 |
Oct 02 10:54:46 PM UTC 24 |
38002547 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_global_esc.4183917382 |
|
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Oct 02 10:54:43 PM UTC 24 |
Oct 02 10:54:46 PM UTC 24 |
73738683 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.372174277 |
|
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Oct 02 10:54:43 PM UTC 24 |
Oct 02 10:54:46 PM UTC 24 |
105528368 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.1327200801 |
|
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Oct 02 10:54:43 PM UTC 24 |
Oct 02 10:54:46 PM UTC 24 |
298270968 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3082825699 |
|
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Oct 02 10:54:43 PM UTC 24 |
Oct 02 10:54:48 PM UTC 24 |
790914862 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2453619382 |
|
|
Oct 02 10:54:43 PM UTC 24 |
Oct 02 10:54:48 PM UTC 24 |
870059201 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_global_esc.725640560 |
|
|
Oct 02 10:53:54 PM UTC 24 |
Oct 02 10:54:50 PM UTC 24 |
42795798 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_glitch.906550070 |
|
|
Oct 02 10:53:54 PM UTC 24 |
Oct 02 10:54:50 PM UTC 24 |
69015978 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.1770771213 |
|
|
Oct 02 10:55:02 PM UTC 24 |
Oct 02 10:55:10 PM UTC 24 |
55794148 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_escalation_timeout.1465906392 |
|
|
Oct 02 10:53:54 PM UTC 24 |
Oct 02 10:54:51 PM UTC 24 |
380638124 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.283102717 |
|
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Oct 02 10:53:54 PM UTC 24 |
Oct 02 10:54:51 PM UTC 24 |
56918934 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_wakeup_race.1765158616 |
|
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Oct 02 10:54:46 PM UTC 24 |
Oct 02 10:54:55 PM UTC 24 |
256106284 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup_reset.605836893 |
|
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Oct 02 10:54:46 PM UTC 24 |
Oct 02 10:54:55 PM UTC 24 |
52641060 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_aborted_low_power.4268787321 |
|
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Oct 02 10:54:46 PM UTC 24 |
Oct 02 10:54:55 PM UTC 24 |
68147313 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_global_esc.4293231375 |
|
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Oct 02 10:54:51 PM UTC 24 |
Oct 02 10:54:55 PM UTC 24 |
31231934 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset_invalid.3151430741 |
|
|
Oct 02 10:54:51 PM UTC 24 |
Oct 02 10:54:56 PM UTC 24 |
163149027 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_escalation_timeout.133272187 |
|
|
Oct 02 10:54:51 PM UTC 24 |
Oct 02 10:54:56 PM UTC 24 |
866567944 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_disable_rom_integrity_check.4206779548 |
|
|
Oct 02 10:54:51 PM UTC 24 |
Oct 02 10:54:56 PM UTC 24 |
59281632 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup.3880064311 |
|
|
Oct 02 10:54:46 PM UTC 24 |
Oct 02 10:54:56 PM UTC 24 |
314390298 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.311663301 |
|
|
Oct 02 10:54:51 PM UTC 24 |
Oct 02 10:54:56 PM UTC 24 |
115759546 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset.122114768 |
|
|
Oct 02 10:54:41 PM UTC 24 |
Oct 02 10:55:00 PM UTC 24 |
124334546 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_smoke.3550334838 |
|
|
Oct 02 10:54:45 PM UTC 24 |
Oct 02 10:55:00 PM UTC 24 |
31159095 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_wakeup_race.178332074 |
|
|
Oct 02 10:54:41 PM UTC 24 |
Oct 02 10:55:00 PM UTC 24 |
272167290 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset.2027594835 |
|
|
Oct 02 10:54:45 PM UTC 24 |
Oct 02 10:55:01 PM UTC 24 |
86911299 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_smoke.359936539 |
|
|
Oct 02 10:54:52 PM UTC 24 |
Oct 02 10:55:01 PM UTC 24 |
71209416 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_invalid.556268629 |
|
|
Oct 02 10:54:52 PM UTC 24 |
Oct 02 10:55:01 PM UTC 24 |
200920952 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset_invalid.1210945737 |
|
|
Oct 02 10:53:54 PM UTC 24 |
Oct 02 10:55:01 PM UTC 24 |
111902727 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.2195147788 |
|
|
Oct 02 10:54:52 PM UTC 24 |
Oct 02 10:55:03 PM UTC 24 |
783794500 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.152482321 |
|
|
Oct 02 10:54:56 PM UTC 24 |
Oct 02 10:55:05 PM UTC 24 |
70637627 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all.503694772 |
|
|
Oct 02 10:54:45 PM UTC 24 |
Oct 02 10:55:05 PM UTC 24 |
1712786882 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2020761405 |
|
|
Oct 02 10:54:56 PM UTC 24 |
Oct 02 10:55:06 PM UTC 24 |
1194841519 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.516630290 |
|
|
Oct 02 10:54:57 PM UTC 24 |
Oct 02 10:55:06 PM UTC 24 |
31480720 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.2074729456 |
|
|
Oct 02 10:54:57 PM UTC 24 |
Oct 02 10:55:06 PM UTC 24 |
63982449 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.1520611722 |
|
|
Oct 02 10:55:01 PM UTC 24 |
Oct 02 10:55:06 PM UTC 24 |
38902616 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.3395323441 |
|
|
Oct 02 10:55:01 PM UTC 24 |
Oct 02 10:55:06 PM UTC 24 |
83289658 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_glitch.4237178413 |
|
|
Oct 02 10:54:51 PM UTC 24 |
Oct 02 10:55:06 PM UTC 24 |
40502017 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.1558557806 |
|
|
Oct 02 10:54:57 PM UTC 24 |
Oct 02 10:55:06 PM UTC 24 |
388560163 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.2110558432 |
|
|
Oct 02 10:55:04 PM UTC 24 |
Oct 02 10:55:06 PM UTC 24 |
177787816 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all_with_rand_reset.521882769 |
|
|
Oct 02 10:53:54 PM UTC 24 |
Oct 02 10:55:06 PM UTC 24 |
1591376499 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.3229547282 |
|
|
Oct 02 10:54:57 PM UTC 24 |
Oct 02 10:55:06 PM UTC 24 |
191817348 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_smoke.2984009809 |
|
|
Oct 02 10:53:54 PM UTC 24 |
Oct 02 10:55:06 PM UTC 24 |
30808068 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.1831069639 |
|
|
Oct 02 10:55:02 PM UTC 24 |
Oct 02 10:55:07 PM UTC 24 |
100792774 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.1528045577 |
|
|
Oct 02 10:54:35 PM UTC 24 |
Oct 02 10:55:07 PM UTC 24 |
31696135 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_global_esc.2207863806 |
|
|
Oct 02 10:55:08 PM UTC 24 |
Oct 02 10:55:10 PM UTC 24 |
54471846 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_global_esc.3930740431 |
|
|
Oct 02 10:54:35 PM UTC 24 |
Oct 02 10:55:07 PM UTC 24 |
42562078 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.4020127702 |
|
|
Oct 02 10:54:35 PM UTC 24 |
Oct 02 10:55:07 PM UTC 24 |
110188353 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_global_esc.1308516870 |
|
|
Oct 02 10:54:05 PM UTC 24 |
Oct 02 10:55:07 PM UTC 24 |
36172925 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_glitch.835962674 |
|
|
Oct 02 10:54:35 PM UTC 24 |
Oct 02 10:55:07 PM UTC 24 |
55969577 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_invalid.4060497577 |
|
|
Oct 02 10:55:02 PM UTC 24 |
Oct 02 10:55:07 PM UTC 24 |
77929568 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_escalation_timeout.1890331156 |
|
|
Oct 02 10:54:05 PM UTC 24 |
Oct 02 10:55:07 PM UTC 24 |
111996563 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_disable_rom_integrity_check.3802249488 |
|
|
Oct 02 10:54:35 PM UTC 24 |
Oct 02 10:55:07 PM UTC 24 |
78222049 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_escalation_timeout.2273163979 |
|
|
Oct 02 10:54:35 PM UTC 24 |
Oct 02 10:55:07 PM UTC 24 |
215191676 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset_invalid.1815760542 |
|
|
Oct 02 10:54:35 PM UTC 24 |
Oct 02 10:55:07 PM UTC 24 |
172319148 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1519374527 |
|
|
Oct 02 10:54:35 PM UTC 24 |
Oct 02 10:55:07 PM UTC 24 |
73003633 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset_invalid.92550069 |
|
|
Oct 02 10:54:45 PM UTC 24 |
Oct 02 10:55:07 PM UTC 24 |
105234577 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.3789936324 |
|
|
Oct 02 10:55:05 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
198328695 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all_with_rand_reset.3119444617 |
|
|
Oct 02 10:54:52 PM UTC 24 |
Oct 02 10:55:09 PM UTC 24 |
6820525674 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup.396491249 |
|
|
Oct 02 10:55:11 PM UTC 24 |
Oct 02 10:55:20 PM UTC 24 |
185578155 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.3101811745 |
|
|
Oct 02 10:55:08 PM UTC 24 |
Oct 02 10:55:10 PM UTC 24 |
97976401 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_glitch.4084781721 |
|
|
Oct 02 10:55:08 PM UTC 24 |
Oct 02 10:55:10 PM UTC 24 |
66758639 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_escalation_timeout.3379738004 |
|
|
Oct 02 10:55:08 PM UTC 24 |
Oct 02 10:55:10 PM UTC 24 |
208335631 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.1332791142 |
|
|
Oct 02 10:55:08 PM UTC 24 |
Oct 02 10:55:10 PM UTC 24 |
166708341 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.2491990950 |
|
|
Oct 02 10:55:05 PM UTC 24 |
Oct 02 10:55:10 PM UTC 24 |
317065574 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.499563474 |
|
|
Oct 02 10:55:08 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
194016425 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.637101578 |
|
|
Oct 02 10:55:02 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
269754221 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_wakeup_race.1028713813 |
|
|
Oct 02 10:55:08 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
67190509 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3428717945 |
|
|
Oct 02 10:55:08 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
1811372317 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.3899466208 |
|
|
Oct 02 10:55:08 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
60962032 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_escalation_timeout.1783655274 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:16 PM UTC 24 |
109732794 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3671631180 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:17 PM UTC 24 |
1881932260 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1464196408 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:17 PM UTC 24 |
864619105 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.1323062654 |
|
|
Oct 02 10:55:18 PM UTC 24 |
Oct 02 10:55:20 PM UTC 24 |
54861945 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup.18923363 |
|
|
Oct 02 10:55:08 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
322759720 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset.709390876 |
|
|
Oct 02 10:54:56 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
62243841 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.1968472991 |
|
|
Oct 02 10:54:56 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
134884157 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.2110373148 |
|
|
Oct 02 10:54:50 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
34807550 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all_with_rand_reset.934169651 |
|
|
Oct 02 10:55:07 PM UTC 24 |
Oct 02 10:55:20 PM UTC 24 |
6662918208 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.1152450528 |
|
|
Oct 02 10:55:02 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
1020101799 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_global_esc.1419398651 |
|
|
Oct 02 10:55:18 PM UTC 24 |
Oct 02 10:55:21 PM UTC 24 |
24250566 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_wakeup_race.613716248 |
|
|
Oct 02 10:54:56 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
74923059 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup_reset.2002443265 |
|
|
Oct 02 10:55:08 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
377359932 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.804182322 |
|
|
Oct 02 10:55:07 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
40463585 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset_invalid.4284499939 |
|
|
Oct 02 10:55:10 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
166748298 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.971034247 |
|
|
Oct 02 10:55:08 PM UTC 24 |
Oct 02 10:55:11 PM UTC 24 |
1319835140 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_global_esc.2793821605 |
|
|
Oct 02 10:55:07 PM UTC 24 |
Oct 02 10:55:12 PM UTC 24 |
110678049 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.1850093453 |
|
|
Oct 02 10:55:06 PM UTC 24 |
Oct 02 10:55:12 PM UTC 24 |
128924891 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_glitch.2037160377 |
|
|
Oct 02 10:55:07 PM UTC 24 |
Oct 02 10:55:12 PM UTC 24 |
23003357 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.2839866286 |
|
|
Oct 02 10:55:07 PM UTC 24 |
Oct 02 10:55:12 PM UTC 24 |
240907484 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.3391357530 |
|
|
Oct 02 10:55:07 PM UTC 24 |
Oct 02 10:55:12 PM UTC 24 |
93371865 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_aborted_low_power.1521401630 |
|
|
Oct 02 10:54:56 PM UTC 24 |
Oct 02 10:55:12 PM UTC 24 |
70968630 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.4157602393 |
|
|
Oct 02 10:55:06 PM UTC 24 |
Oct 02 10:55:12 PM UTC 24 |
43091130 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1269947813 |
|
|
Oct 02 10:54:50 PM UTC 24 |
Oct 02 10:55:12 PM UTC 24 |
111871359 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup_reset.1913015255 |
|
|
Oct 02 10:54:56 PM UTC 24 |
Oct 02 10:55:12 PM UTC 24 |
182933408 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.2880292304 |
|
|
Oct 02 10:55:07 PM UTC 24 |
Oct 02 10:55:12 PM UTC 24 |
218987560 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset_invalid.922187665 |
|
|
Oct 02 10:55:07 PM UTC 24 |
Oct 02 10:55:12 PM UTC 24 |
152785842 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_escalation_timeout.322063835 |
|
|
Oct 02 10:55:07 PM UTC 24 |
Oct 02 10:55:12 PM UTC 24 |
203209051 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset.362479209 |
|
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Oct 02 10:55:07 PM UTC 24 |
Oct 02 10:55:12 PM UTC 24 |
89678301 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_smoke.450196443 |
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Oct 02 10:55:07 PM UTC 24 |
Oct 02 10:55:12 PM UTC 24 |
29513094 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_smoke.93866395 |
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|
Oct 02 10:55:11 PM UTC 24 |
Oct 02 10:55:13 PM UTC 24 |
34927596 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset.2851597832 |
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|
Oct 02 10:55:11 PM UTC 24 |
Oct 02 10:55:13 PM UTC 24 |
132212786 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1965364348 |
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|
Oct 02 10:55:06 PM UTC 24 |
Oct 02 10:55:13 PM UTC 24 |
838949313 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2226687614 |
|
|
Oct 02 10:54:56 PM UTC 24 |
Oct 02 10:55:14 PM UTC 24 |
755913751 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.773666056 |
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|
Oct 02 10:55:07 PM UTC 24 |
Oct 02 10:55:14 PM UTC 24 |
777750476 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all.2004273486 |
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|
Oct 02 10:55:11 PM UTC 24 |
Oct 02 10:55:14 PM UTC 24 |
705067963 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_global_esc.1578785073 |
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Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:15 PM UTC 24 |
37715004 ps |