| T564 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_glitch.1553920807 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:15 PM UTC 24 |
54958345 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all.2079838609 |
|
|
Oct 02 10:55:14 PM UTC 24 |
Oct 02 10:55:18 PM UTC 24 |
1469115871 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup_reset.618231505 |
|
|
Oct 02 10:55:11 PM UTC 24 |
Oct 02 10:55:20 PM UTC 24 |
65478363 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_escalation_timeout.1784263477 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:15 PM UTC 24 |
347989024 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_wakeup_race.1507149364 |
|
|
Oct 02 10:55:11 PM UTC 24 |
Oct 02 10:55:20 PM UTC 24 |
290919201 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset_invalid.4190564816 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:15 PM UTC 24 |
323423228 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.1977001251 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:15 PM UTC 24 |
212522886 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_smoke.3965073203 |
|
|
Oct 02 10:55:14 PM UTC 24 |
Oct 02 10:55:15 PM UTC 24 |
32863754 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2506421628 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:15 PM UTC 24 |
31267894 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.1075188836 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:15 PM UTC 24 |
58238003 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset.3429147890 |
|
|
Oct 02 10:55:14 PM UTC 24 |
Oct 02 10:55:15 PM UTC 24 |
87278258 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup.1053984443 |
|
|
Oct 02 10:55:14 PM UTC 24 |
Oct 02 10:55:15 PM UTC 24 |
240957489 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1367060742 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:15 PM UTC 24 |
174962241 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_invalid.4208396164 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:15 PM UTC 24 |
39040277 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_global_esc.645861788 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:15 PM UTC 24 |
74017147 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.1990701881 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:15 PM UTC 24 |
31565741 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_wakeup_race.125465741 |
|
|
Oct 02 10:55:14 PM UTC 24 |
Oct 02 10:55:16 PM UTC 24 |
235187015 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all.4167505369 |
|
|
Oct 02 10:55:07 PM UTC 24 |
Oct 02 10:55:17 PM UTC 24 |
1530341017 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_aborted_low_power.765414316 |
|
|
Oct 02 10:55:11 PM UTC 24 |
Oct 02 10:55:20 PM UTC 24 |
28753171 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.1610640887 |
|
|
Oct 02 10:55:18 PM UTC 24 |
Oct 02 10:55:21 PM UTC 24 |
208945885 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_global_esc.1348469651 |
|
|
Oct 02 10:55:16 PM UTC 24 |
Oct 02 10:55:21 PM UTC 24 |
24404685 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_escalation_timeout.3775958811 |
|
|
Oct 02 10:55:19 PM UTC 24 |
Oct 02 10:55:21 PM UTC 24 |
338786887 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_glitch.3250601696 |
|
|
Oct 02 10:55:16 PM UTC 24 |
Oct 02 10:55:21 PM UTC 24 |
40720689 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_disable_rom_integrity_check.2338718590 |
|
|
Oct 02 10:55:16 PM UTC 24 |
Oct 02 10:55:21 PM UTC 24 |
58830321 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_escalation_timeout.291273977 |
|
|
Oct 02 10:55:16 PM UTC 24 |
Oct 02 10:55:21 PM UTC 24 |
1835823777 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_smoke.2485038448 |
|
|
Oct 02 10:55:16 PM UTC 24 |
Oct 02 10:55:21 PM UTC 24 |
76466674 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset.2661991834 |
|
|
Oct 02 10:55:17 PM UTC 24 |
Oct 02 10:55:21 PM UTC 24 |
67051187 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset_invalid.529923539 |
|
|
Oct 02 10:55:16 PM UTC 24 |
Oct 02 10:55:21 PM UTC 24 |
126735787 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_wakeup_race.3173745681 |
|
|
Oct 02 10:55:17 PM UTC 24 |
Oct 02 10:55:21 PM UTC 24 |
90984985 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup.443660618 |
|
|
Oct 02 10:55:17 PM UTC 24 |
Oct 02 10:55:21 PM UTC 24 |
106172141 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.1527298614 |
|
|
Oct 02 10:55:17 PM UTC 24 |
Oct 02 10:55:22 PM UTC 24 |
38702615 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_glitch.2758011255 |
|
|
Oct 02 10:55:20 PM UTC 24 |
Oct 02 10:55:22 PM UTC 24 |
343007239 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2337892622 |
|
|
Oct 02 10:55:17 PM UTC 24 |
Oct 02 10:55:22 PM UTC 24 |
139491798 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup_reset.784464641 |
|
|
Oct 02 10:55:17 PM UTC 24 |
Oct 02 10:55:22 PM UTC 24 |
489818087 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.333180436 |
|
|
Oct 02 10:55:17 PM UTC 24 |
Oct 02 10:55:23 PM UTC 24 |
2451248369 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1290437430 |
|
|
Oct 02 10:55:17 PM UTC 24 |
Oct 02 10:55:23 PM UTC 24 |
1009706960 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all.3346305365 |
|
|
Oct 02 10:55:16 PM UTC 24 |
Oct 02 10:55:24 PM UTC 24 |
922304975 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all_with_rand_reset.2223300774 |
|
|
Oct 02 10:55:11 PM UTC 24 |
Oct 02 10:55:24 PM UTC 24 |
30840322463 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.3134677213 |
|
|
Oct 02 10:55:20 PM UTC 24 |
Oct 02 10:55:25 PM UTC 24 |
168157472 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset_invalid.1388991257 |
|
|
Oct 02 10:55:20 PM UTC 24 |
Oct 02 10:55:25 PM UTC 24 |
151420226 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_invalid.1251668701 |
|
|
Oct 02 10:55:20 PM UTC 24 |
Oct 02 10:55:25 PM UTC 24 |
81728849 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_glitch.1575128816 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:25 PM UTC 24 |
34514056 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_disable_rom_integrity_check.2493971333 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
85179522 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_global_esc.967995835 |
|
|
Oct 02 10:55:23 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
26605884 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.1297225315 |
|
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Oct 02 10:55:23 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
128734980 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.1514978429 |
|
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Oct 02 10:55:23 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
28900853 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_smoke.2562941874 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
53053432 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset.119614636 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
41687327 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset_invalid.2764769463 |
|
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Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
162157915 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_escalation_timeout.2134688787 |
|
|
Oct 02 10:55:23 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
230426277 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_glitch.257035671 |
|
|
Oct 02 10:55:23 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
50127508 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.4100215824 |
|
|
Oct 02 10:55:23 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
540452088 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup.317034208 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
288465514 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_aborted_low_power.4114700372 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
59478247 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.417545056 |
|
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Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
27905403 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.3428242608 |
|
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Oct 02 10:55:23 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
62392954 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_wakeup_race.2011097022 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
183971707 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.3337761695 |
|
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Oct 02 10:55:23 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
122146689 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3087323772 |
|
|
Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
64320944 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_smoke.2757178803 |
|
|
Oct 02 10:55:21 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
26670034 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup_reset.1128082370 |
|
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Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
264159240 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset.1502634512 |
|
|
Oct 02 10:55:21 PM UTC 24 |
Oct 02 10:55:26 PM UTC 24 |
108036383 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_wakeup_race.2866448725 |
|
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Oct 02 10:55:22 PM UTC 24 |
Oct 02 10:55:27 PM UTC 24 |
182333666 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.218025538 |
|
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Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:28 PM UTC 24 |
1285099921 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2882733427 |
|
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Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:28 PM UTC 24 |
888039483 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2987987925 |
|
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Oct 02 10:55:23 PM UTC 24 |
Oct 02 10:55:28 PM UTC 24 |
881087747 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all.484859713 |
|
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Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:29 PM UTC 24 |
3185153616 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all.2714749345 |
|
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Oct 02 10:55:21 PM UTC 24 |
Oct 02 10:55:29 PM UTC 24 |
2155379539 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all.2944830755 |
|
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Oct 02 10:55:24 PM UTC 24 |
Oct 02 10:55:29 PM UTC 24 |
5773167387 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup_reset.2119694969 |
|
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Oct 02 10:55:22 PM UTC 24 |
Oct 02 10:55:29 PM UTC 24 |
66798920 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup.3994291664 |
|
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Oct 02 10:55:22 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
198970310 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_aborted_low_power.2471589252 |
|
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Oct 02 10:55:22 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
80203877 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2602266098 |
|
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Oct 02 10:55:15 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
36469245 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_aborted_low_power.4027478690 |
|
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Oct 02 10:55:15 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
66404229 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup_reset.1047556713 |
|
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Oct 02 10:55:15 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
118187522 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_aborted_low_power.753337770 |
|
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Oct 02 10:55:28 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
39164031 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_smoke.91125008 |
|
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Oct 02 10:55:25 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
31340953 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_wakeup_race.1001213811 |
|
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Oct 02 10:55:25 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
170819543 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_wakeup_race.168287897 |
|
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Oct 02 10:55:28 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
173204960 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1778768377 |
|
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Oct 02 10:55:15 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
126199943 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup.2217658168 |
|
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Oct 02 10:55:25 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
95822632 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup.1524429144 |
|
|
Oct 02 10:55:28 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
249321922 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset.3270061726 |
|
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Oct 02 10:55:25 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
147084730 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_global_esc.162165878 |
|
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Oct 02 10:55:29 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
163496292 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.901738043 |
|
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Oct 02 10:55:29 PM UTC 24 |
Oct 02 10:55:30 PM UTC 24 |
38055558 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup_reset.1954087473 |
|
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Oct 02 10:55:28 PM UTC 24 |
Oct 02 10:55:31 PM UTC 24 |
215239354 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup_reset.1612418127 |
|
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Oct 02 10:55:25 PM UTC 24 |
Oct 02 10:55:31 PM UTC 24 |
164936620 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all_with_rand_reset.1324887157 |
|
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Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:31 PM UTC 24 |
11464831155 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.891533291 |
|
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Oct 02 10:55:29 PM UTC 24 |
Oct 02 10:55:31 PM UTC 24 |
164783902 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.2328031689 |
|
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Oct 02 10:55:15 PM UTC 24 |
Oct 02 10:55:31 PM UTC 24 |
205265692 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.550889692 |
|
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Oct 02 10:55:29 PM UTC 24 |
Oct 02 10:55:31 PM UTC 24 |
131794139 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.4185491430 |
|
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Oct 02 10:55:20 PM UTC 24 |
Oct 02 10:55:31 PM UTC 24 |
2068546831 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all_with_rand_reset.1785149315 |
|
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Oct 02 10:54:45 PM UTC 24 |
Oct 02 10:55:31 PM UTC 24 |
17237586760 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.851885688 |
|
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Oct 02 10:55:22 PM UTC 24 |
Oct 02 10:55:31 PM UTC 24 |
1082549972 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_aborted_low_power.2859923163 |
|
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Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:32 PM UTC 24 |
19952396 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1827398809 |
|
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Oct 02 10:55:28 PM UTC 24 |
Oct 02 10:55:32 PM UTC 24 |
1254463061 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2854388021 |
|
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Oct 02 10:55:15 PM UTC 24 |
Oct 02 10:55:32 PM UTC 24 |
958486755 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_escalation_timeout.1880918143 |
|
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Oct 02 10:55:30 PM UTC 24 |
Oct 02 10:55:32 PM UTC 24 |
394093874 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.636008773 |
|
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Oct 02 10:55:15 PM UTC 24 |
Oct 02 10:55:32 PM UTC 24 |
934794545 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3799373379 |
|
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Oct 02 10:55:28 PM UTC 24 |
Oct 02 10:55:32 PM UTC 24 |
930347372 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all_with_rand_reset.877775680 |
|
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Oct 02 10:55:24 PM UTC 24 |
Oct 02 10:55:32 PM UTC 24 |
1992527736 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all_with_rand_reset.685128052 |
|
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Oct 02 10:55:16 PM UTC 24 |
Oct 02 10:55:32 PM UTC 24 |
5052277668 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2776633223 |
|
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Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:34 PM UTC 24 |
777387270 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3261358392 |
|
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Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:34 PM UTC 24 |
885261202 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all_with_rand_reset.3817056097 |
|
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Oct 02 10:55:13 PM UTC 24 |
Oct 02 10:55:34 PM UTC 24 |
4580918948 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_disable_rom_integrity_check.551640784 |
|
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Oct 02 10:55:30 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
47325489 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_glitch.2228107701 |
|
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Oct 02 10:55:30 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
59165637 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.3380120736 |
|
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Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
61623572 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_glitch.1512702850 |
|
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Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
75733054 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_smoke.1661022569 |
|
|
Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
38770469 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_disable_rom_integrity_check.2401973805 |
|
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Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
83239430 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup.3745399568 |
|
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Oct 02 10:55:33 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
51553578 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_global_esc.365535598 |
|
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Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
34822884 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_wakeup_race.4156949389 |
|
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Oct 02 10:55:38 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
239471268 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset_invalid.2543969744 |
|
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Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
353407513 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.2202625055 |
|
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Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
29556123 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset.3996682055 |
|
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Oct 02 10:55:33 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
74184998 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_escalation_timeout.1287698993 |
|
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Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
110382979 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset.3355179576 |
|
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Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
103195092 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset.2850941122 |
|
|
Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
144468128 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_aborted_low_power.2668872909 |
|
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Oct 02 10:55:33 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
28506664 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup_reset.3192193723 |
|
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Oct 02 10:55:33 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
284829890 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.709248949 |
|
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Oct 02 10:55:33 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
29545993 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.2800378700 |
|
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Oct 02 10:55:33 PM UTC 24 |
Oct 02 10:55:35 PM UTC 24 |
67208635 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_wakeup_race.2524980798 |
|
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Oct 02 10:55:33 PM UTC 24 |
Oct 02 10:55:36 PM UTC 24 |
165895220 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.4020045482 |
|
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Oct 02 10:55:34 PM UTC 24 |
Oct 02 10:55:36 PM UTC 24 |
150487572 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.4141938083 |
|
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Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
33725811 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.2147999979 |
|
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Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:36 PM UTC 24 |
250828193 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_smoke.2248924885 |
|
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Oct 02 10:55:33 PM UTC 24 |
Oct 02 10:55:36 PM UTC 24 |
32405652 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_global_esc.3129419041 |
|
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Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
33279568 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset_invalid.2258912709 |
|
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Oct 02 10:55:31 PM UTC 24 |
Oct 02 10:55:36 PM UTC 24 |
108275907 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1102890846 |
|
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Oct 02 10:55:33 PM UTC 24 |
Oct 02 10:55:37 PM UTC 24 |
1029509056 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all.1756171844 |
|
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Oct 02 10:55:33 PM UTC 24 |
Oct 02 10:55:37 PM UTC 24 |
2633687387 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1822952608 |
|
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Oct 02 10:55:33 PM UTC 24 |
Oct 02 10:55:37 PM UTC 24 |
3595641437 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all.3445626263 |
|
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Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:38 PM UTC 24 |
1473813657 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all.3152668293 |
|
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Oct 02 10:55:31 PM UTC 24 |
Oct 02 10:55:39 PM UTC 24 |
731316462 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_glitch.2389991471 |
|
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Oct 02 10:55:32 PM UTC 24 |
Oct 02 10:55:39 PM UTC 24 |
41116468 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_global_esc.3808921569 |
|
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Oct 02 10:55:35 PM UTC 24 |
Oct 02 10:55:39 PM UTC 24 |
49654951 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_smoke.3928192317 |
|
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Oct 02 10:55:31 PM UTC 24 |
Oct 02 10:55:39 PM UTC 24 |
56134843 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_disable_rom_integrity_check.1681843778 |
|
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Oct 02 10:55:32 PM UTC 24 |
Oct 02 10:55:39 PM UTC 24 |
69396831 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_glitch.1885638179 |
|
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Oct 02 10:55:35 PM UTC 24 |
Oct 02 10:55:39 PM UTC 24 |
64618236 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_escalation_timeout.1798795362 |
|
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Oct 02 10:55:32 PM UTC 24 |
Oct 02 10:55:40 PM UTC 24 |
396585769 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset_invalid.3737009278 |
|
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Oct 02 10:55:32 PM UTC 24 |
Oct 02 10:55:40 PM UTC 24 |
101272395 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_escalation_timeout.1284812543 |
|
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Oct 02 10:55:35 PM UTC 24 |
Oct 02 10:55:40 PM UTC 24 |
111614422 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_global_esc.1942373696 |
|
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Oct 02 10:55:31 PM UTC 24 |
Oct 02 10:55:40 PM UTC 24 |
44158756 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_aborted_low_power.3899592093 |
|
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Oct 02 10:55:31 PM UTC 24 |
Oct 02 10:55:40 PM UTC 24 |
27872537 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_glitch.521291233 |
|
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Oct 02 10:55:38 PM UTC 24 |
Oct 02 10:55:40 PM UTC 24 |
48444218 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_disable_rom_integrity_check.1806978197 |
|
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Oct 02 10:55:38 PM UTC 24 |
Oct 02 10:55:40 PM UTC 24 |
61902138 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.590689588 |
|
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Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
71701085 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.3464880308 |
|
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Oct 02 10:55:38 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
29871694 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset.1987218304 |
|
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Oct 02 10:55:38 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
125806369 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2719543054 |
|
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Oct 02 10:55:31 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
1151959190 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset_invalid.4044976784 |
|
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Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
232881701 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_smoke.166284774 |
|
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Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
58306971 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_disable_rom_integrity_check.489266839 |
|
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Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
98824777 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_wakeup_race.2676554204 |
|
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Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
127687190 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.1429633898 |
|
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Oct 02 10:55:38 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
126122499 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_aborted_low_power.3552338867 |
|
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Oct 02 10:55:39 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
43205729 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset_invalid.2236306994 |
|
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Oct 02 10:55:38 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
108566302 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup_reset.945264139 |
|
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Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
128961856 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_aborted_low_power.1529554906 |
|
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Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
24671947 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup_reset.3898570956 |
|
|
Oct 02 10:55:39 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
196975347 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup.1614735220 |
|
|
Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
194094147 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3167584524 |
|
|
Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
59073282 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.4100895062 |
|
|
Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
76260216 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_escalation_timeout.1665614363 |
|
|
Oct 02 10:55:37 PM UTC 24 |
Oct 02 10:55:41 PM UTC 24 |
205027873 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.702293836 |
|
|
Oct 02 10:55:40 PM UTC 24 |
Oct 02 10:55:42 PM UTC 24 |
32445063 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2411694770 |
|
|
Oct 02 10:55:40 PM UTC 24 |
Oct 02 10:55:42 PM UTC 24 |
93384397 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_global_esc.2200237898 |
|
|
Oct 02 10:55:40 PM UTC 24 |
Oct 02 10:55:42 PM UTC 24 |
55107780 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_glitch.4169763262 |
|
|
Oct 02 10:55:40 PM UTC 24 |
Oct 02 10:55:42 PM UTC 24 |
38443218 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_escalation_timeout.3825157064 |
|
|
Oct 02 10:55:40 PM UTC 24 |
Oct 02 10:55:42 PM UTC 24 |
388460765 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.1451963682 |
|
|
Oct 02 10:55:40 PM UTC 24 |
Oct 02 10:55:42 PM UTC 24 |
238879924 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.939427394 |
|
|
Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:43 PM UTC 24 |
922586670 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2390067723 |
|
|
Oct 02 10:55:40 PM UTC 24 |
Oct 02 10:55:43 PM UTC 24 |
1602757837 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset.1308763755 |
|
|
Oct 02 10:55:31 PM UTC 24 |
Oct 02 10:55:43 PM UTC 24 |
45130857 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.1507520855 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
78801059 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2219605512 |
|
|
Oct 02 10:55:44 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
822945232 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2183518507 |
|
|
Oct 02 10:55:31 PM UTC 24 |
Oct 02 10:55:43 PM UTC 24 |
36591626 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup.3489898993 |
|
|
Oct 02 10:55:31 PM UTC 24 |
Oct 02 10:55:43 PM UTC 24 |
59129538 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1170297982 |
|
|
Oct 02 10:55:40 PM UTC 24 |
Oct 02 10:55:43 PM UTC 24 |
965210081 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all_with_rand_reset.2268514278 |
|
|
Oct 02 10:55:27 PM UTC 24 |
Oct 02 10:55:43 PM UTC 24 |
6779700721 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.2910982623 |
|
|
Oct 02 10:55:31 PM UTC 24 |
Oct 02 10:55:43 PM UTC 24 |
63659910 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.4255713407 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
113458665 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_wakeup_race.2500975919 |
|
|
Oct 02 10:55:31 PM UTC 24 |
Oct 02 10:55:43 PM UTC 24 |
774224887 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_disable_rom_integrity_check.30694303 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
74322485 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.1643368923 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
168053963 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.234130348 |
|
|
Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
723972065 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.2454533027 |
|
|
Oct 02 10:55:31 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
87344923 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.3163759035 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
33125108 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup_reset.971772294 |
|
|
Oct 02 10:55:31 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
181741228 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.3988350061 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
128725765 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.1308287576 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
39551813 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.3442942678 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
30665715 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.2011105192 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
190480587 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.566267239 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
84936752 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.2214114003 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
47831815 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.3971765921 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
31157043 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2857889352 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
338018747 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.2964046021 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
139044746 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.380529023 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
45431025 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.3776635847 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
65301581 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.4268003462 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:44 PM UTC 24 |
403932351 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.4188539862 |
|
|
Oct 02 10:55:38 PM UTC 24 |
Oct 02 10:55:45 PM UTC 24 |
1922878007 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3201874975 |
|
|
Oct 02 10:55:31 PM UTC 24 |
Oct 02 10:55:45 PM UTC 24 |
1096458080 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.736264552 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:45 PM UTC 24 |
1936509660 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.1853497234 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:45 PM UTC 24 |
4202281123 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1525383832 |
|
|
Oct 02 10:55:44 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
745220186 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.4043370181 |
|
|
Oct 02 10:55:43 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
1328297889 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.950299286 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
77485989 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2758075275 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:45 PM UTC 24 |
1090311333 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.798644971 |
|
|
Oct 02 10:55:43 PM UTC 24 |
Oct 02 10:55:45 PM UTC 24 |
48474827 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.3547182174 |
|
|
Oct 02 10:55:43 PM UTC 24 |
Oct 02 10:55:45 PM UTC 24 |
32895652 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.192131710 |
|
|
Oct 02 10:55:42 PM UTC 24 |
Oct 02 10:55:46 PM UTC 24 |
143745768 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.3811625005 |
|
|
Oct 02 10:55:44 PM UTC 24 |
Oct 02 10:55:46 PM UTC 24 |
161267567 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.1667496955 |
|
|
Oct 02 10:55:44 PM UTC 24 |
Oct 02 10:55:46 PM UTC 24 |
26447116 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.1366780665 |
|
|
Oct 02 10:55:44 PM UTC 24 |
Oct 02 10:55:46 PM UTC 24 |
40914818 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.2601763259 |
|
|
Oct 02 10:55:44 PM UTC 24 |
Oct 02 10:55:46 PM UTC 24 |
35117252 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.2206107599 |
|
|
Oct 02 10:55:44 PM UTC 24 |
Oct 02 10:55:46 PM UTC 24 |
69281835 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.2225967772 |
|
|
Oct 02 10:55:44 PM UTC 24 |
Oct 02 10:55:46 PM UTC 24 |
511946444 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.1127722540 |
|
|
Oct 02 10:55:44 PM UTC 24 |
Oct 02 10:55:46 PM UTC 24 |
94541385 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.2886162239 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
239151529 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3954190662 |
|
|
Oct 02 10:55:44 PM UTC 24 |
Oct 02 10:55:46 PM UTC 24 |
52122737 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.2811458323 |
|
|
Oct 02 10:55:44 PM UTC 24 |
Oct 02 10:55:46 PM UTC 24 |
112147698 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.3695681300 |
|
|
Oct 02 10:55:44 PM UTC 24 |
Oct 02 10:55:46 PM UTC 24 |
86451066 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all.823590234 |
|
|
Oct 02 10:55:36 PM UTC 24 |
Oct 02 10:55:46 PM UTC 24 |
1922337971 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.3026642485 |
|
|
Oct 02 10:55:44 PM UTC 24 |
Oct 02 10:55:46 PM UTC 24 |
121634010 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.4065881408 |
|
|
Oct 02 10:55:44 PM UTC 24 |
Oct 02 10:55:47 PM UTC 24 |
312743289 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.1433869499 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:47 PM UTC 24 |
62958997 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.3897613770 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
126838362 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.3387166481 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
89833531 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.2640000609 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
23590327 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.3187333782 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
39002216 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.2461492583 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
42049807 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.1338076431 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
64050494 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.771389134 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:48 PM UTC 24 |
295773683 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1212994925 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:49 PM UTC 24 |
1001286166 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.3849295513 |
|
|
Oct 02 10:55:52 PM UTC 24 |
Oct 02 10:56:21 PM UTC 24 |
125627767 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.135474449 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:49 PM UTC 24 |
1122209786 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.3543379200 |
|
|
Oct 02 10:55:47 PM UTC 24 |
Oct 02 10:55:50 PM UTC 24 |
54255287 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.4190595285 |
|
|
Oct 02 10:55:47 PM UTC 24 |
Oct 02 10:55:50 PM UTC 24 |
184089675 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.1810311455 |
|
|
Oct 02 10:55:48 PM UTC 24 |
Oct 02 10:55:50 PM UTC 24 |
56060173 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.1419210284 |
|
|
Oct 02 10:55:52 PM UTC 24 |
Oct 02 10:56:21 PM UTC 24 |
508724404 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.2822748228 |
|
|
Oct 02 10:55:48 PM UTC 24 |
Oct 02 10:55:50 PM UTC 24 |
399963213 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.3468408694 |
|
|
Oct 02 10:55:48 PM UTC 24 |
Oct 02 10:55:50 PM UTC 24 |
67376301 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.4021678788 |
|
|
Oct 02 10:55:47 PM UTC 24 |
Oct 02 10:55:50 PM UTC 24 |
253171723 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.2184464270 |
|
|
Oct 02 10:55:48 PM UTC 24 |
Oct 02 10:55:50 PM UTC 24 |
20966635 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.3288498717 |
|
|
Oct 02 10:55:48 PM UTC 24 |
Oct 02 10:55:50 PM UTC 24 |
61142324 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.1059644658 |
|
|
Oct 02 10:55:48 PM UTC 24 |
Oct 02 10:55:50 PM UTC 24 |
110508223 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.276544350 |
|
|
Oct 02 10:55:46 PM UTC 24 |
Oct 02 10:55:50 PM UTC 24 |
1790048207 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.1825375895 |
|
|
Oct 02 10:55:49 PM UTC 24 |
Oct 02 10:55:50 PM UTC 24 |
59623387 ps |