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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.96 98.21 96.58 99.62 96.00 96.32 100.00 99.02


Total test records in report: 995
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T805 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.3785619929 Oct 02 10:55:49 PM UTC 24 Oct 02 10:55:50 PM UTC 24 22736704 ps
T806 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.3400239250 Oct 02 10:55:49 PM UTC 24 Oct 02 10:55:51 PM UTC 24 480572378 ps
T807 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.2453816219 Oct 02 10:55:48 PM UTC 24 Oct 02 10:55:51 PM UTC 24 38494021 ps
T808 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.449035252 Oct 02 10:55:49 PM UTC 24 Oct 02 10:55:51 PM UTC 24 291764822 ps
T809 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.2047575888 Oct 02 10:55:48 PM UTC 24 Oct 02 10:55:51 PM UTC 24 68274244 ps
T810 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all_with_rand_reset.494532970 Oct 02 10:55:42 PM UTC 24 Oct 02 10:55:51 PM UTC 24 3729130941 ps
T811 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.4039382075 Oct 02 10:55:48 PM UTC 24 Oct 02 10:55:51 PM UTC 24 244533329 ps
T812 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.1831527802 Oct 02 10:55:48 PM UTC 24 Oct 02 10:55:51 PM UTC 24 335403257 ps
T813 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.4191377889 Oct 02 10:55:46 PM UTC 24 Oct 02 10:55:51 PM UTC 24 146669139 ps
T814 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.2881778266 Oct 02 10:55:47 PM UTC 24 Oct 02 10:55:51 PM UTC 24 74692649 ps
T815 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.1168257266 Oct 02 10:55:47 PM UTC 24 Oct 02 10:55:51 PM UTC 24 32560947 ps
T816 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.289020608 Oct 02 10:55:50 PM UTC 24 Oct 02 10:55:52 PM UTC 24 83572932 ps
T817 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.3160866714 Oct 02 10:55:50 PM UTC 24 Oct 02 10:55:52 PM UTC 24 63128604 ps
T818 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.3219117663 Oct 02 10:55:50 PM UTC 24 Oct 02 10:55:52 PM UTC 24 28963335 ps
T819 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.2314197283 Oct 02 10:55:47 PM UTC 24 Oct 02 10:55:52 PM UTC 24 338089874 ps
T820 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.2907887726 Oct 02 10:55:50 PM UTC 24 Oct 02 10:55:52 PM UTC 24 192847145 ps
T821 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2248989817 Oct 02 10:55:47 PM UTC 24 Oct 02 10:55:52 PM UTC 24 835847915 ps
T822 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.1913650341 Oct 02 10:55:42 PM UTC 24 Oct 02 10:55:52 PM UTC 24 3770539066 ps
T823 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.3126816729 Oct 02 10:55:48 PM UTC 24 Oct 02 10:55:53 PM UTC 24 4813739452 ps
T824 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2284384779 Oct 02 10:55:48 PM UTC 24 Oct 02 10:55:53 PM UTC 24 1011100555 ps
T825 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.694981147 Oct 02 10:55:50 PM UTC 24 Oct 02 10:55:53 PM UTC 24 1039680089 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.4249297142 Oct 02 10:55:36 PM UTC 24 Oct 02 10:55:54 PM UTC 24 11694491879 ps
T826 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.211070069 Oct 02 10:55:52 PM UTC 24 Oct 02 10:56:21 PM UTC 24 86857186 ps
T827 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3277911351 Oct 02 10:55:50 PM UTC 24 Oct 02 10:55:54 PM UTC 24 921798795 ps
T828 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.1448806633 Oct 02 10:55:50 PM UTC 24 Oct 02 10:55:55 PM UTC 24 51810922 ps
T829 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.2381880465 Oct 02 10:55:50 PM UTC 24 Oct 02 10:55:55 PM UTC 24 204060132 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all_with_rand_reset.125730377 Oct 02 10:55:31 PM UTC 24 Oct 02 10:55:56 PM UTC 24 3883743195 ps
T830 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.577061764 Oct 02 10:55:47 PM UTC 24 Oct 02 10:55:58 PM UTC 24 1998327474 ps
T831 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.3402495825 Oct 02 10:55:52 PM UTC 24 Oct 02 10:55:58 PM UTC 24 2106247494 ps
T832 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.2744279956 Oct 02 10:55:44 PM UTC 24 Oct 02 10:55:58 PM UTC 24 4390437936 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.3439057867 Oct 02 10:55:38 PM UTC 24 Oct 02 10:55:59 PM UTC 24 6280661866 ps
T833 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.1026182444 Oct 02 10:55:46 PM UTC 24 Oct 02 10:56:02 PM UTC 24 10378438817 ps
T834 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2144712912 Oct 02 10:55:52 PM UTC 24 Oct 02 10:56:05 PM UTC 24 130343545 ps
T835 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.3665452174 Oct 02 10:55:55 PM UTC 24 Oct 02 10:56:05 PM UTC 24 4962783858 ps
T836 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.1926080804 Oct 02 10:55:33 PM UTC 24 Oct 02 10:56:05 PM UTC 24 10636448076 ps
T837 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.3915736425 Oct 02 10:55:52 PM UTC 24 Oct 02 10:56:06 PM UTC 24 286412586 ps
T838 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.2080410339 Oct 02 10:55:52 PM UTC 24 Oct 02 10:56:08 PM UTC 24 3230046345 ps
T839 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.286663522 Oct 02 10:55:55 PM UTC 24 Oct 02 10:56:10 PM UTC 24 40762700 ps
T840 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.2837304146 Oct 02 10:55:59 PM UTC 24 Oct 02 10:56:10 PM UTC 24 17296025 ps
T841 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.3690235475 Oct 02 10:55:55 PM UTC 24 Oct 02 10:56:10 PM UTC 24 88632132 ps
T842 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.1528627644 Oct 02 10:56:08 PM UTC 24 Oct 02 10:56:10 PM UTC 24 83579500 ps
T843 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.3118727218 Oct 02 10:55:59 PM UTC 24 Oct 02 10:56:10 PM UTC 24 96516266 ps
T844 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.3833887355 Oct 02 10:55:55 PM UTC 24 Oct 02 10:56:16 PM UTC 24 2318994482 ps
T845 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.1872362028 Oct 02 10:56:12 PM UTC 24 Oct 02 10:56:20 PM UTC 24 30098129 ps
T846 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.3904438005 Oct 02 10:56:11 PM UTC 24 Oct 02 10:56:20 PM UTC 24 159647029 ps
T847 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.3722272915 Oct 02 10:56:18 PM UTC 24 Oct 02 10:56:20 PM UTC 24 80159721 ps
T848 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.2203957956 Oct 02 10:56:16 PM UTC 24 Oct 02 10:56:21 PM UTC 24 260930798 ps
T849 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.2000695262 Oct 02 10:55:52 PM UTC 24 Oct 02 10:56:21 PM UTC 24 30199607 ps
T850 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.1062863630 Oct 02 10:55:52 PM UTC 24 Oct 02 10:56:21 PM UTC 24 17767912 ps
T851 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.2658032275 Oct 02 10:56:06 PM UTC 24 Oct 02 10:56:21 PM UTC 24 29484511 ps
T852 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.1959326650 Oct 02 10:55:52 PM UTC 24 Oct 02 10:56:21 PM UTC 24 175554158 ps
T853 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.3148709642 Oct 02 10:56:06 PM UTC 24 Oct 02 10:56:21 PM UTC 24 37135811 ps
T854 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3738945141 Oct 02 10:55:52 PM UTC 24 Oct 02 10:56:22 PM UTC 24 2068571440 ps
T855 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.1588252063 Oct 02 10:56:11 PM UTC 24 Oct 02 10:56:23 PM UTC 24 3559654783 ps
T856 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.2877608433 Oct 02 10:56:22 PM UTC 24 Oct 02 10:56:24 PM UTC 24 51514218 ps
T857 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.693867465 Oct 02 10:56:21 PM UTC 24 Oct 02 10:56:24 PM UTC 24 968653156 ps
T858 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.716923882 Oct 02 10:56:22 PM UTC 24 Oct 02 10:56:25 PM UTC 24 111113288 ps
T859 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.792982126 Oct 02 10:56:21 PM UTC 24 Oct 02 10:56:26 PM UTC 24 495613767 ps
T860 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4065569571 Oct 02 10:56:00 PM UTC 24 Oct 02 10:56:26 PM UTC 24 1359083211 ps
T861 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4054826136 Oct 02 10:56:26 PM UTC 24 Oct 02 10:56:28 PM UTC 24 1069623369 ps
T862 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.2548052897 Oct 02 10:56:11 PM UTC 24 Oct 02 10:56:30 PM UTC 24 5778161232 ps
T863 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2837351511 Oct 02 10:56:26 PM UTC 24 Oct 02 10:56:36 PM UTC 24 1064554520 ps
T864 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.2683487053 Oct 02 10:56:32 PM UTC 24 Oct 02 10:56:39 PM UTC 24 1109960782 ps
T865 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.306810649 Oct 02 10:56:26 PM UTC 24 Oct 02 10:56:40 PM UTC 24 44104388 ps
T866 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.2889023076 Oct 02 10:56:26 PM UTC 24 Oct 02 10:56:40 PM UTC 24 31041499 ps
T867 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.1179649642 Oct 02 10:56:26 PM UTC 24 Oct 02 10:56:40 PM UTC 24 38051475 ps
T868 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.2404051031 Oct 02 10:56:26 PM UTC 24 Oct 02 10:56:40 PM UTC 24 33313450 ps
T869 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.2528857678 Oct 02 10:56:26 PM UTC 24 Oct 02 10:56:40 PM UTC 24 66666466 ps
T870 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.4158753828 Oct 02 10:56:26 PM UTC 24 Oct 02 10:56:40 PM UTC 24 174167382 ps
T871 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.2018204949 Oct 02 10:56:26 PM UTC 24 Oct 02 10:56:41 PM UTC 24 180812459 ps
T872 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.819420706 Oct 02 10:56:29 PM UTC 24 Oct 02 10:56:41 PM UTC 24 565979305 ps
T873 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.3142837711 Oct 02 10:56:22 PM UTC 24 Oct 02 10:56:41 PM UTC 24 55506432 ps
T874 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.133957847 Oct 02 10:56:32 PM UTC 24 Oct 02 10:56:41 PM UTC 24 2076573872 ps
T875 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2460918581 Oct 02 10:56:22 PM UTC 24 Oct 02 10:56:41 PM UTC 24 29276815 ps
T876 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1436744932 Oct 02 10:56:22 PM UTC 24 Oct 02 10:56:41 PM UTC 24 50825298 ps
T877 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.3440270063 Oct 02 10:56:22 PM UTC 24 Oct 02 10:56:41 PM UTC 24 160952566 ps
T878 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3839578581 Oct 02 10:56:22 PM UTC 24 Oct 02 10:56:42 PM UTC 24 1074594859 ps
T879 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.1240390037 Oct 02 10:56:22 PM UTC 24 Oct 02 10:56:51 PM UTC 24 110430032 ps
T880 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.2294088909 Oct 02 10:56:22 PM UTC 24 Oct 02 10:56:51 PM UTC 24 64376763 ps
T881 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.774656634 Oct 02 10:56:32 PM UTC 24 Oct 02 10:56:51 PM UTC 24 118485831 ps
T882 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.1551546481 Oct 02 10:56:30 PM UTC 24 Oct 02 10:56:55 PM UTC 24 50280740 ps
T883 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1521402645 Oct 02 10:56:00 PM UTC 24 Oct 02 10:56:56 PM UTC 24 1074192265 ps
T884 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.1556954686 Oct 02 10:56:31 PM UTC 24 Oct 02 10:57:10 PM UTC 24 58065107 ps
T885 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.947947215 Oct 02 10:56:24 PM UTC 24 Oct 02 10:57:13 PM UTC 24 35642212 ps
T886 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.539858669 Oct 02 10:56:24 PM UTC 24 Oct 02 10:57:14 PM UTC 24 801903525 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.2441228446 Oct 02 10:56:35 PM UTC 24 Oct 02 10:56:40 PM UTC 24 38824100 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.952030873 Oct 02 10:56:35 PM UTC 24 Oct 02 10:56:40 PM UTC 24 55486896 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.3014847014 Oct 02 10:56:35 PM UTC 24 Oct 02 10:56:40 PM UTC 24 21104341 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2471327892 Oct 02 10:56:36 PM UTC 24 Oct 02 10:56:40 PM UTC 24 90268638 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3923465719 Oct 02 10:56:35 PM UTC 24 Oct 02 10:56:41 PM UTC 24 112373838 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3169745337 Oct 02 10:56:35 PM UTC 24 Oct 02 10:56:41 PM UTC 24 402895319 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1187445205 Oct 02 10:56:36 PM UTC 24 Oct 02 10:56:43 PM UTC 24 962343725 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2864623015 Oct 02 10:56:42 PM UTC 24 Oct 02 10:56:45 PM UTC 24 25301737 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.1862568257 Oct 02 10:56:42 PM UTC 24 Oct 02 10:56:45 PM UTC 24 49262540 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.4010940479 Oct 02 10:56:40 PM UTC 24 Oct 02 10:56:45 PM UTC 24 80609957 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.831395790 Oct 02 10:56:42 PM UTC 24 Oct 02 10:56:45 PM UTC 24 17323730 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2530302714 Oct 02 10:56:42 PM UTC 24 Oct 02 10:56:46 PM UTC 24 363502819 ps
T887 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3634291583 Oct 02 10:56:41 PM UTC 24 Oct 02 10:56:50 PM UTC 24 79242943 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.3137261562 Oct 02 10:56:41 PM UTC 24 Oct 02 10:56:50 PM UTC 24 52936036 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.2666998109 Oct 02 10:56:46 PM UTC 24 Oct 02 10:56:51 PM UTC 24 19561742 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3003450492 Oct 02 10:56:46 PM UTC 24 Oct 02 10:56:51 PM UTC 24 118474808 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.3249588365 Oct 02 10:56:46 PM UTC 24 Oct 02 10:56:51 PM UTC 24 61657439 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.424863411 Oct 02 10:56:46 PM UTC 24 Oct 02 10:56:51 PM UTC 24 146137216 ps
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T58 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2759927167 Oct 02 10:56:46 PM UTC 24 Oct 02 10:56:52 PM UTC 24 340422261 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.3352973078 Oct 02 10:56:46 PM UTC 24 Oct 02 10:56:52 PM UTC 24 48485603 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2223590619 Oct 02 10:56:42 PM UTC 24 Oct 02 10:56:55 PM UTC 24 221784950 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.365887780 Oct 02 10:56:43 PM UTC 24 Oct 02 10:56:55 PM UTC 24 55485109 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1805580989 Oct 02 10:56:43 PM UTC 24 Oct 02 10:56:56 PM UTC 24 60546914 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.234397203 Oct 02 10:56:43 PM UTC 24 Oct 02 10:56:57 PM UTC 24 376128592 ps
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T164 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.2088243015 Oct 02 10:56:56 PM UTC 24 Oct 02 10:57:05 PM UTC 24 21856591 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.504770661 Oct 02 10:56:56 PM UTC 24 Oct 02 10:57:05 PM UTC 24 22206033 ps
T890 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2475105502 Oct 02 10:56:56 PM UTC 24 Oct 02 10:57:05 PM UTC 24 51119914 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.1695620891 Oct 02 10:56:53 PM UTC 24 Oct 02 10:57:13 PM UTC 24 47891885 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.353075405 Oct 02 10:56:56 PM UTC 24 Oct 02 10:57:06 PM UTC 24 108370567 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.2600636133 Oct 02 10:56:41 PM UTC 24 Oct 02 10:57:06 PM UTC 24 30942624 ps
T891 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1856050492 Oct 02 10:56:41 PM UTC 24 Oct 02 10:57:06 PM UTC 24 237579437 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2584430397 Oct 02 10:56:53 PM UTC 24 Oct 02 10:57:06 PM UTC 24 105163963 ps
T892 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.413081148 Oct 02 10:56:56 PM UTC 24 Oct 02 10:57:06 PM UTC 24 100376866 ps
T893 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.4133643066 Oct 02 10:57:06 PM UTC 24 Oct 02 10:57:09 PM UTC 24 635633259 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3286853573 Oct 02 10:57:07 PM UTC 24 Oct 02 10:57:09 PM UTC 24 19898893 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.984975855 Oct 02 10:57:07 PM UTC 24 Oct 02 10:57:10 PM UTC 24 48379647 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.1237702311 Oct 02 10:57:07 PM UTC 24 Oct 02 10:57:10 PM UTC 24 53760776 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.2832256130 Oct 02 10:56:55 PM UTC 24 Oct 02 10:57:10 PM UTC 24 37678339 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.607575804 Oct 02 10:56:55 PM UTC 24 Oct 02 10:57:10 PM UTC 24 47950266 ps
T894 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2601606605 Oct 02 10:56:41 PM UTC 24 Oct 02 10:57:10 PM UTC 24 51474737 ps
T895 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.1244210272 Oct 02 10:56:52 PM UTC 24 Oct 02 10:57:13 PM UTC 24 136922370 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.2381691456 Oct 02 10:56:51 PM UTC 24 Oct 02 10:57:10 PM UTC 24 41539576 ps
T896 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3193164608 Oct 02 10:56:55 PM UTC 24 Oct 02 10:57:10 PM UTC 24 42932723 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3405744507 Oct 02 10:56:51 PM UTC 24 Oct 02 10:57:10 PM UTC 24 50581533 ps
T897 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.3362994336 Oct 02 10:56:59 PM UTC 24 Oct 02 10:57:10 PM UTC 24 51186435 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.1014741160 Oct 02 10:56:51 PM UTC 24 Oct 02 10:57:10 PM UTC 24 45049616 ps
T898 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3898866927 Oct 02 10:56:51 PM UTC 24 Oct 02 10:57:10 PM UTC 24 22772529 ps
T899 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.3738773479 Oct 02 10:56:57 PM UTC 24 Oct 02 10:57:10 PM UTC 24 33385883 ps
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T116 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.1802701519 Oct 02 10:56:52 PM UTC 24 Oct 02 10:57:10 PM UTC 24 21101595 ps
T901 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1673928923 Oct 02 10:56:52 PM UTC 24 Oct 02 10:57:11 PM UTC 24 58130551 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.3464614528 Oct 02 10:56:52 PM UTC 24 Oct 02 10:57:11 PM UTC 24 24027032 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.3650484811 Oct 02 10:57:06 PM UTC 24 Oct 02 10:57:11 PM UTC 24 49635319 ps
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T117 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1205175135 Oct 02 10:56:41 PM UTC 24 Oct 02 10:57:13 PM UTC 24 49823558 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.3576404139 Oct 02 10:56:55 PM UTC 24 Oct 02 10:57:11 PM UTC 24 337316893 ps
T903 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.1055631580 Oct 02 10:57:06 PM UTC 24 Oct 02 10:57:11 PM UTC 24 19626777 ps
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T905 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2740610609 Oct 02 10:57:06 PM UTC 24 Oct 02 10:57:11 PM UTC 24 160396839 ps
T906 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.544417674 Oct 02 10:56:52 PM UTC 24 Oct 02 10:57:11 PM UTC 24 69208580 ps
T907 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.3658082863 Oct 02 10:57:09 PM UTC 24 Oct 02 10:57:11 PM UTC 24 52276900 ps
T908 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.3724590044 Oct 02 10:56:52 PM UTC 24 Oct 02 10:57:11 PM UTC 24 29065969 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3946988414 Oct 02 10:56:52 PM UTC 24 Oct 02 10:57:11 PM UTC 24 180890004 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.528494214 Oct 02 10:57:06 PM UTC 24 Oct 02 10:57:11 PM UTC 24 179985958 ps
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T70 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1902128327 Oct 02 10:57:06 PM UTC 24 Oct 02 10:57:12 PM UTC 24 194265450 ps
T910 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.3318748532 Oct 02 10:57:10 PM UTC 24 Oct 02 10:57:12 PM UTC 24 28454155 ps
T911 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.353004130 Oct 02 10:57:07 PM UTC 24 Oct 02 10:57:12 PM UTC 24 103452600 ps
T912 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.4113002315 Oct 02 10:57:10 PM UTC 24 Oct 02 10:57:12 PM UTC 24 47466005 ps
T913 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.678024186 Oct 02 10:57:10 PM UTC 24 Oct 02 10:57:12 PM UTC 24 50258839 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.3161438217 Oct 02 10:57:11 PM UTC 24 Oct 02 10:57:12 PM UTC 24 38849835 ps
T914 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.116961333 Oct 02 10:57:06 PM UTC 24 Oct 02 10:57:12 PM UTC 24 190936372 ps
T119 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.3562448205 Oct 02 10:56:51 PM UTC 24 Oct 02 10:57:12 PM UTC 24 161288986 ps
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T71 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.2182657604 Oct 02 10:57:10 PM UTC 24 Oct 02 10:57:13 PM UTC 24 213266040 ps
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T917 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.1088930108 Oct 02 10:57:07 PM UTC 24 Oct 02 10:57:13 PM UTC 24 262960791 ps
T918 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.3561075043 Oct 02 10:56:41 PM UTC 24 Oct 02 10:57:13 PM UTC 24 31004690 ps
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T920 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.2502990793 Oct 02 10:57:10 PM UTC 24 Oct 02 10:57:13 PM UTC 24 73284188 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2740977885 Oct 02 10:56:53 PM UTC 24 Oct 02 10:57:13 PM UTC 24 267681756 ps
T921 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.2821602422 Oct 02 10:56:53 PM UTC 24 Oct 02 10:57:14 PM UTC 24 75496667 ps
T922 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.1285827051 Oct 02 10:56:45 PM UTC 24 Oct 02 10:57:14 PM UTC 24 78448602 ps
T923 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.298350680 Oct 02 10:57:12 PM UTC 24 Oct 02 10:57:14 PM UTC 24 40186261 ps
T924 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.4233130043 Oct 02 10:57:12 PM UTC 24 Oct 02 10:57:14 PM UTC 24 22238143 ps
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T926 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.404518238 Oct 02 10:57:12 PM UTC 24 Oct 02 10:57:14 PM UTC 24 17945433 ps
T927 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.2619045558 Oct 02 10:57:26 PM UTC 24 Oct 02 10:57:28 PM UTC 24 19447229 ps
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T930 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.2456815147 Oct 02 10:57:12 PM UTC 24 Oct 02 10:57:14 PM UTC 24 318942128 ps
T931 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.954298080 Oct 02 10:57:12 PM UTC 24 Oct 02 10:57:14 PM UTC 24 20344069 ps
T932 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.4167703679 Oct 02 10:57:12 PM UTC 24 Oct 02 10:57:14 PM UTC 24 129346704 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.4235285188 Oct 02 10:57:12 PM UTC 24 Oct 02 10:57:14 PM UTC 24 155499280 ps
T933 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.2316594752 Oct 02 10:57:13 PM UTC 24 Oct 02 10:57:14 PM UTC 24 99217765 ps
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T937 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.379213700 Oct 02 10:57:13 PM UTC 24 Oct 02 10:57:15 PM UTC 24 90733941 ps
T938 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.737028914 Oct 02 10:57:13 PM UTC 24 Oct 02 10:57:15 PM UTC 24 18468351 ps
T939 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1488938247 Oct 02 10:57:12 PM UTC 24 Oct 02 10:57:15 PM UTC 24 41735575 ps
T940 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.1239229959 Oct 02 10:57:12 PM UTC 24 Oct 02 10:57:15 PM UTC 24 41553319 ps
T941 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2578732777 Oct 02 10:57:13 PM UTC 24 Oct 02 10:57:15 PM UTC 24 455551001 ps
T942 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2836622102 Oct 02 10:57:13 PM UTC 24 Oct 02 10:57:15 PM UTC 24 284165137 ps
T943 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3259719893 Oct 02 10:57:12 PM UTC 24 Oct 02 10:57:15 PM UTC 24 307363877 ps
T944 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1496083336 Oct 02 10:57:12 PM UTC 24 Oct 02 10:57:15 PM UTC 24 158015924 ps
T945 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1311947417 Oct 02 10:57:13 PM UTC 24 Oct 02 10:57:15 PM UTC 24 63158614 ps
T946 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.1254985059 Oct 02 10:57:13 PM UTC 24 Oct 02 10:57:15 PM UTC 24 124590392 ps
T947 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1127023402 Oct 02 10:57:13 PM UTC 24 Oct 02 10:57:15 PM UTC 24 330259720 ps
T948 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.4129449682 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:16 PM UTC 24 27734048 ps
T949 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.116928763 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:16 PM UTC 24 68399395 ps
T950 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.2540130837 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:16 PM UTC 24 46152474 ps
T951 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.3443925389 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 37206705 ps
T952 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.4157644633 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 31305744 ps
T953 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3629487669 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 68157834 ps
T954 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2061315062 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 72164312 ps
T955 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3789054846 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 42485286 ps
T956 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.3545871517 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 44559256 ps
T957 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.248812247 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 39476049 ps
T958 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.4170012202 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 47999720 ps
T959 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.1135959559 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 101846283 ps
T960 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.3998476305 Oct 02 10:57:26 PM UTC 24 Oct 02 10:57:28 PM UTC 24 72617206 ps
T961 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.2805177810 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 49815665 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1951343929 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 206551209 ps
T962 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3501289131 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 21464169 ps
T963 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.531935548 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 18192972 ps
T964 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1733111801 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 134263646 ps
T965 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.2128218172 Oct 02 10:57:26 PM UTC 24 Oct 02 10:57:28 PM UTC 24 23594642 ps
T966 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.703139087 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 21227520 ps
T967 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.216986711 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 34717415 ps
T968 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.385692408 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 26754182 ps
T969 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.1794331352 Oct 02 10:57:16 PM UTC 24 Oct 02 10:57:17 PM UTC 24 17173885 ps
T970 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.2163886717 Oct 02 10:57:26 PM UTC 24 Oct 02 10:57:28 PM UTC 24 24734492 ps
T971 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.3036626511 Oct 02 10:57:16 PM UTC 24 Oct 02 10:57:17 PM UTC 24 20586546 ps
T972 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.3754442837 Oct 02 10:57:16 PM UTC 24 Oct 02 10:57:17 PM UTC 24 21741182 ps
T973 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.552402256 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 95879702 ps
T974 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.3698058955 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:17 PM UTC 24 31970117 ps
T975 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.3002052715 Oct 02 10:57:16 PM UTC 24 Oct 02 10:57:17 PM UTC 24 33344652 ps
T976 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.819530636 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:18 PM UTC 24 41467456 ps
T977 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.531436104 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:18 PM UTC 24 422744861 ps
T978 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.4284928245 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:18 PM UTC 24 52235296 ps
T979 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3713777098 Oct 02 10:57:15 PM UTC 24 Oct 02 10:57:18 PM UTC 24 451364932 ps
T980 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.1929974017 Oct 02 10:57:16 PM UTC 24 Oct 02 10:57:20 PM UTC 24 26742505 ps
T981 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.1113042933 Oct 02 10:57:16 PM UTC 24 Oct 02 10:57:20 PM UTC 24 18265187 ps
T982 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.571623975 Oct 02 10:57:16 PM UTC 24 Oct 02 10:57:20 PM UTC 24 33730660 ps
T983 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.778078468 Oct 02 10:57:16 PM UTC 24 Oct 02 10:57:20 PM UTC 24 16212806 ps
T984 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.1443706648 Oct 02 10:57:16 PM UTC 24 Oct 02 10:57:20 PM UTC 24 85186456 ps
T985 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.1623596335 Oct 02 10:57:16 PM UTC 24 Oct 02 10:57:21 PM UTC 24 22513582 ps
T986 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.4293799829 Oct 02 10:57:16 PM UTC 24 Oct 02 10:57:21 PM UTC 24 34496808 ps
T987 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.2388103795 Oct 02 10:57:26 PM UTC 24 Oct 02 10:57:28 PM UTC 24 21096882 ps
T988 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.1570036626 Oct 02 10:57:26 PM UTC 24 Oct 02 10:57:28 PM UTC 24 17481571 ps
T989 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.3092332282 Oct 02 10:57:26 PM UTC 24 Oct 02 10:57:28 PM UTC 24 34289250 ps
T990 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.669459243 Oct 02 10:57:26 PM UTC 24 Oct 02 10:57:28 PM UTC 24 29405438 ps
T991 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.1686338430 Oct 02 10:57:26 PM UTC 24 Oct 02 10:57:28 PM UTC 24 20428694 ps
T992 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.326195322 Oct 02 10:57:26 PM UTC 24 Oct 02 10:57:28 PM UTC 24 21933080 ps
T993 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.512632010 Oct 02 10:57:26 PM UTC 24 Oct 02 10:57:28 PM UTC 24 59951658 ps
T994 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.3101405776 Oct 02 10:57:26 PM UTC 24 Oct 02 10:57:28 PM UTC 24 19863465 ps
T995 /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.905997308 Oct 02 10:57:26 PM UTC 24 Oct 02 10:57:28 PM UTC 24 48851654 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.3395006343
Short name T5
Test name
Test status
Simulation time 237700568 ps
CPU time 1.36 seconds
Started Oct 02 10:52:59 PM UTC 24
Finished Oct 02 10:53:01 PM UTC 24
Peak memory 209468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395006343 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.3395006343
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.779663077
Short name T28
Test name
Test status
Simulation time 98102340 ps
CPU time 1.55 seconds
Started Oct 02 10:53:02 PM UTC 24
Finished Oct 02 10:53:04 PM UTC 24
Peak memory 220240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779663077 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.779663077
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2319660935
Short name T14
Test name
Test status
Simulation time 845159389 ps
CPU time 3.52 seconds
Started Oct 02 10:52:59 PM UTC 24
Finished Oct 02 10:53:04 PM UTC 24
Peak memory 211384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319660935 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.2319660935
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.111550184
Short name T16
Test name
Test status
Simulation time 638062217 ps
CPU time 2.99 seconds
Started Oct 02 10:53:02 PM UTC 24
Finished Oct 02 10:53:06 PM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111550184 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.111550184
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.1630853335
Short name T21
Test name
Test status
Simulation time 851767634 ps
CPU time 1.79 seconds
Started Oct 02 10:53:05 PM UTC 24
Finished Oct 02 10:53:08 PM UTC 24
Peak memory 237576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630853335 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.1630853335
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.1091558219
Short name T48
Test name
Test status
Simulation time 4022866685 ps
CPU time 11.66 seconds
Started Oct 02 10:53:22 PM UTC 24
Finished Oct 02 10:53:34 PM UTC 24
Peak memory 211564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1091558219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr
_stress_all_with_rand_reset.1091558219
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3169745337
Short name T50
Test name
Test status
Simulation time 402895319 ps
CPU time 1.49 seconds
Started Oct 02 10:56:35 PM UTC 24
Finished Oct 02 10:56:41 PM UTC 24
Peak memory 209496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169745337 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.3169745337
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.1690053217
Short name T43
Test name
Test status
Simulation time 53514368 ps
CPU time 0.78 seconds
Started Oct 02 10:53:37 PM UTC 24
Finished Oct 02 10:53:39 PM UTC 24
Peak memory 210164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690053217 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invalid.1690053217
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.3613954945
Short name T10
Test name
Test status
Simulation time 406913455 ps
CPU time 1.39 seconds
Started Oct 02 10:53:01 PM UTC 24
Finished Oct 02 10:53:03 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613954945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3613954945
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.1862568257
Short name T163
Test name
Test status
Simulation time 49262540 ps
CPU time 0.53 seconds
Started Oct 02 10:56:42 PM UTC 24
Finished Oct 02 10:56:45 PM UTC 24
Peak memory 206484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862568257 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.1862568257
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3923465719
Short name T47
Test name
Test status
Simulation time 112373838 ps
CPU time 1.49 seconds
Started Oct 02 10:56:35 PM UTC 24
Finished Oct 02 10:56:41 PM UTC 24
Peak memory 208996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923465719 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3923465719
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.3014847014
Short name T55
Test name
Test status
Simulation time 21104341 ps
CPU time 0.61 seconds
Started Oct 02 10:56:35 PM UTC 24
Finished Oct 02 10:56:40 PM UTC 24
Peak memory 208384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014847014 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.3014847014
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2050967177
Short name T77
Test name
Test status
Simulation time 1114239614 ps
CPU time 2.26 seconds
Started Oct 02 10:53:10 PM UTC 24
Finished Oct 02 10:53:13 PM UTC 24
Peak memory 211512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050967177 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.2050967177
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.3685861061
Short name T59
Test name
Test status
Simulation time 422035323 ps
CPU time 1.36 seconds
Started Oct 02 10:53:05 PM UTC 24
Finished Oct 02 10:53:07 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685861061 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_ctrl_config_regwen.3685861061
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.1998699358
Short name T150
Test name
Test status
Simulation time 55833779 ps
CPU time 1.25 seconds
Started Oct 02 10:53:08 PM UTC 24
Finished Oct 02 10:53:11 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998699358 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disable_rom_integrity_check.1998699358
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2740977885
Short name T161
Test name
Test status
Simulation time 267681756 ps
CPU time 1.43 seconds
Started Oct 02 10:56:53 PM UTC 24
Finished Oct 02 10:57:13 PM UTC 24
Peak memory 209820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740977885 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err.2740977885
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.2832256130
Short name T166
Test name
Test status
Simulation time 37678339 ps
CPU time 0.57 seconds
Started Oct 02 10:56:55 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 207020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832256130 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.2832256130
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.3244140634
Short name T177
Test name
Test status
Simulation time 89345865 ps
CPU time 0.75 seconds
Started Oct 02 10:53:34 PM UTC 24
Finished Oct 02 10:53:36 PM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244140634 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disable_rom_integrity_check.3244140634
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2471327892
Short name T63
Test name
Test status
Simulation time 90268638 ps
CPU time 0.75 seconds
Started Oct 02 10:56:36 PM UTC 24
Finished Oct 02 10:56:40 PM UTC 24
Peak memory 209592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471327892 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.2471327892
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.2182657604
Short name T71
Test name
Test status
Simulation time 213266040 ps
CPU time 1.09 seconds
Started Oct 02 10:57:10 PM UTC 24
Finished Oct 02 10:57:13 PM UTC 24
Peak memory 211180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182657604 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err.2182657604
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.3415003462
Short name T23
Test name
Test status
Simulation time 6161171365 ps
CPU time 14.94 seconds
Started Oct 02 10:53:02 PM UTC 24
Finished Oct 02 10:53:18 PM UTC 24
Peak memory 211892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3415003462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr
_stress_all_with_rand_reset.3415003462
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.1099363456
Short name T179
Test name
Test status
Simulation time 85480092 ps
CPU time 0.73 seconds
Started Oct 02 10:53:36 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 208860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099363456 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disable_rom_integrity_check.1099363456
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_disable_rom_integrity_check.30694303
Short name T174
Test name
Test status
Simulation time 74322485 ps
CPU time 0.69 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 208624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30694303 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disable_rom_integrity_check.30694303
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.4281504536
Short name T17
Test name
Test status
Simulation time 71049136 ps
CPU time 0.9 seconds
Started Oct 02 10:53:02 PM UTC 24
Finished Oct 02 10:53:04 PM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281504536 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.4281504536
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1187445205
Short name T62
Test name
Test status
Simulation time 962343725 ps
CPU time 2.96 seconds
Started Oct 02 10:56:36 PM UTC 24
Finished Oct 02 10:56:43 PM UTC 24
Peak memory 211100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187445205 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.1187445205
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.952030873
Short name T53
Test name
Test status
Simulation time 55486896 ps
CPU time 0.58 seconds
Started Oct 02 10:56:35 PM UTC 24
Finished Oct 02 10:56:40 PM UTC 24
Peak memory 208412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952030873 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.952030873
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.4010940479
Short name T66
Test name
Test status
Simulation time 80609957 ps
CPU time 1.45 seconds
Started Oct 02 10:56:40 PM UTC 24
Finished Oct 02 10:56:45 PM UTC 24
Peak memory 211180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4010940479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_w
ith_rand_reset.4010940479
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.2441228446
Short name T52
Test name
Test status
Simulation time 38824100 ps
CPU time 0.56 seconds
Started Oct 02 10:56:35 PM UTC 24
Finished Oct 02 10:56:40 PM UTC 24
Peak memory 208116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441228446 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.2441228446
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1856050492
Short name T891
Test name
Test status
Simulation time 237579437 ps
CPU time 0.67 seconds
Started Oct 02 10:56:41 PM UTC 24
Finished Oct 02 10:57:06 PM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856050492 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1856050492
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.1983876130
Short name T928
Test name
Test status
Simulation time 1323543431 ps
CPU time 1.77 seconds
Started Oct 02 10:56:41 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 211152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983876130 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.1983876130
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1205175135
Short name T117
Test name
Test status
Simulation time 49823558 ps
CPU time 0.62 seconds
Started Oct 02 10:56:41 PM UTC 24
Finished Oct 02 10:57:13 PM UTC 24
Peak memory 208596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205175135 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.1205175135
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3634291583
Short name T887
Test name
Test status
Simulation time 79242943 ps
CPU time 0.74 seconds
Started Oct 02 10:56:41 PM UTC 24
Finished Oct 02 10:56:50 PM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3634291583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_w
ith_rand_reset.3634291583
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.2600636133
Short name T113
Test name
Test status
Simulation time 30942624 ps
CPU time 0.59 seconds
Started Oct 02 10:56:41 PM UTC 24
Finished Oct 02 10:57:06 PM UTC 24
Peak memory 208040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600636133 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.2600636133
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.3561075043
Short name T918
Test name
Test status
Simulation time 31004690 ps
CPU time 0.59 seconds
Started Oct 02 10:56:41 PM UTC 24
Finished Oct 02 10:57:13 PM UTC 24
Peak memory 206960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561075043 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.3561075043
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2601606605
Short name T894
Test name
Test status
Simulation time 51474737 ps
CPU time 0.66 seconds
Started Oct 02 10:56:41 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 209036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601606605 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_same_csr_outstanding.2601606605
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.353004130
Short name T911
Test name
Test status
Simulation time 103452600 ps
CPU time 0.8 seconds
Started Oct 02 10:57:07 PM UTC 24
Finished Oct 02 10:57:12 PM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=353004130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_w
ith_rand_reset.353004130
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.984975855
Short name T125
Test name
Test status
Simulation time 48379647 ps
CPU time 0.56 seconds
Started Oct 02 10:57:07 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984975855 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.984975855
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.1237702311
Short name T165
Test name
Test status
Simulation time 53760776 ps
CPU time 0.57 seconds
Started Oct 02 10:57:07 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237702311 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.1237702311
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3286853573
Short name T124
Test name
Test status
Simulation time 19898893 ps
CPU time 0.63 seconds
Started Oct 02 10:57:07 PM UTC 24
Finished Oct 02 10:57:09 PM UTC 24
Peak memory 209620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286853573 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_same_csr_outstanding.3286853573
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.4133643066
Short name T893
Test name
Test status
Simulation time 635633259 ps
CPU time 1.85 seconds
Started Oct 02 10:57:06 PM UTC 24
Finished Oct 02 10:57:09 PM UTC 24
Peak memory 211172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133643066 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.4133643066
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1902128327
Short name T70
Test name
Test status
Simulation time 194265450 ps
CPU time 1.53 seconds
Started Oct 02 10:57:06 PM UTC 24
Finished Oct 02 10:57:12 PM UTC 24
Peak memory 211148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902128327 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err.1902128327
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.4113002315
Short name T912
Test name
Test status
Simulation time 47466005 ps
CPU time 0.69 seconds
Started Oct 02 10:57:10 PM UTC 24
Finished Oct 02 10:57:12 PM UTC 24
Peak memory 209888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4113002315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_
with_rand_reset.4113002315
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.3318748532
Short name T910
Test name
Test status
Simulation time 28454155 ps
CPU time 0.62 seconds
Started Oct 02 10:57:10 PM UTC 24
Finished Oct 02 10:57:12 PM UTC 24
Peak memory 208768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318748532 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3318748532
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.3658082863
Short name T907
Test name
Test status
Simulation time 52276900 ps
CPU time 0.56 seconds
Started Oct 02 10:57:09 PM UTC 24
Finished Oct 02 10:57:11 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658082863 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.3658082863
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.962975182
Short name T915
Test name
Test status
Simulation time 26558024 ps
CPU time 0.79 seconds
Started Oct 02 10:57:10 PM UTC 24
Finished Oct 02 10:57:12 PM UTC 24
Peak memory 209092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962975182 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_same_csr_outstanding.962975182
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.1088930108
Short name T917
Test name
Test status
Simulation time 262960791 ps
CPU time 1.5 seconds
Started Oct 02 10:57:07 PM UTC 24
Finished Oct 02 10:57:13 PM UTC 24
Peak memory 211172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088930108 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.1088930108
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2381306369
Short name T909
Test name
Test status
Simulation time 974650486 ps
CPU time 1.36 seconds
Started Oct 02 10:57:09 PM UTC 24
Finished Oct 02 10:57:12 PM UTC 24
Peak memory 211220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381306369 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_err.2381306369
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.298350680
Short name T923
Test name
Test status
Simulation time 40186261 ps
CPU time 0.69 seconds
Started Oct 02 10:57:12 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=298350680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_w
ith_rand_reset.298350680
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.3161438217
Short name T118
Test name
Test status
Simulation time 38849835 ps
CPU time 0.62 seconds
Started Oct 02 10:57:11 PM UTC 24
Finished Oct 02 10:57:12 PM UTC 24
Peak memory 208504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161438217 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.3161438217
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.678024186
Short name T913
Test name
Test status
Simulation time 50258839 ps
CPU time 0.61 seconds
Started Oct 02 10:57:10 PM UTC 24
Finished Oct 02 10:57:12 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678024186 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.678024186
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.1948395574
Short name T925
Test name
Test status
Simulation time 30601925 ps
CPU time 0.76 seconds
Started Oct 02 10:57:12 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 209100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948395574 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_same_csr_outstanding.1948395574
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.2502990793
Short name T920
Test name
Test status
Simulation time 73284188 ps
CPU time 2.08 seconds
Started Oct 02 10:57:10 PM UTC 24
Finished Oct 02 10:57:13 PM UTC 24
Peak memory 211180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502990793 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.2502990793
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.2456815147
Short name T930
Test name
Test status
Simulation time 318942128 ps
CPU time 0.84 seconds
Started Oct 02 10:57:12 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 209828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2456815147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_
with_rand_reset.2456815147
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.404518238
Short name T926
Test name
Test status
Simulation time 17945433 ps
CPU time 0.61 seconds
Started Oct 02 10:57:12 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404518238 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.404518238
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.4233130043
Short name T924
Test name
Test status
Simulation time 22238143 ps
CPU time 0.59 seconds
Started Oct 02 10:57:12 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233130043 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.4233130043
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.697671183
Short name T929
Test name
Test status
Simulation time 65210483 ps
CPU time 0.82 seconds
Started Oct 02 10:57:12 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697671183 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_same_csr_outstanding.697671183
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.1239229959
Short name T940
Test name
Test status
Simulation time 41553319 ps
CPU time 1.62 seconds
Started Oct 02 10:57:12 PM UTC 24
Finished Oct 02 10:57:15 PM UTC 24
Peak memory 211180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239229959 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.1239229959
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.4167703679
Short name T932
Test name
Test status
Simulation time 129346704 ps
CPU time 1.02 seconds
Started Oct 02 10:57:12 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 211136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167703679 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_err.4167703679
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1488938247
Short name T939
Test name
Test status
Simulation time 41735575 ps
CPU time 1.1 seconds
Started Oct 02 10:57:12 PM UTC 24
Finished Oct 02 10:57:15 PM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1488938247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_
with_rand_reset.1488938247
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.4235285188
Short name T120
Test name
Test status
Simulation time 155499280 ps
CPU time 0.63 seconds
Started Oct 02 10:57:12 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 208444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235285188 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.4235285188
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.954298080
Short name T931
Test name
Test status
Simulation time 20344069 ps
CPU time 0.6 seconds
Started Oct 02 10:57:12 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 206724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954298080 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.954298080
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2231007963
Short name T934
Test name
Test status
Simulation time 31571781 ps
CPU time 0.8 seconds
Started Oct 02 10:57:12 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231007963 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_same_csr_outstanding.2231007963
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1496083336
Short name T944
Test name
Test status
Simulation time 158015924 ps
CPU time 1.69 seconds
Started Oct 02 10:57:12 PM UTC 24
Finished Oct 02 10:57:15 PM UTC 24
Peak memory 210976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496083336 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.1496083336
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3259719893
Short name T943
Test name
Test status
Simulation time 307363877 ps
CPU time 1.62 seconds
Started Oct 02 10:57:12 PM UTC 24
Finished Oct 02 10:57:15 PM UTC 24
Peak memory 211420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259719893 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err.3259719893
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2836622102
Short name T942
Test name
Test status
Simulation time 284165137 ps
CPU time 1.19 seconds
Started Oct 02 10:57:13 PM UTC 24
Finished Oct 02 10:57:15 PM UTC 24
Peak memory 211192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2836622102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_
with_rand_reset.2836622102
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.1910523144
Short name T935
Test name
Test status
Simulation time 23614189 ps
CPU time 0.65 seconds
Started Oct 02 10:57:13 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 208504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910523144 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.1910523144
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.2316594752
Short name T933
Test name
Test status
Simulation time 99217765 ps
CPU time 0.58 seconds
Started Oct 02 10:57:13 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316594752 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.2316594752
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.3607853329
Short name T936
Test name
Test status
Simulation time 18982330 ps
CPU time 0.66 seconds
Started Oct 02 10:57:13 PM UTC 24
Finished Oct 02 10:57:15 PM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607853329 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_same_csr_outstanding.3607853329
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.1254985059
Short name T946
Test name
Test status
Simulation time 124590392 ps
CPU time 1.54 seconds
Started Oct 02 10:57:13 PM UTC 24
Finished Oct 02 10:57:15 PM UTC 24
Peak memory 211004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254985059 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.1254985059
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2578732777
Short name T941
Test name
Test status
Simulation time 455551001 ps
CPU time 1.04 seconds
Started Oct 02 10:57:13 PM UTC 24
Finished Oct 02 10:57:15 PM UTC 24
Peak memory 211188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578732777 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_err.2578732777
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2061315062
Short name T954
Test name
Test status
Simulation time 72164312 ps
CPU time 0.85 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 211232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2061315062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_
with_rand_reset.2061315062
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.737028914
Short name T938
Test name
Test status
Simulation time 18468351 ps
CPU time 0.58 seconds
Started Oct 02 10:57:13 PM UTC 24
Finished Oct 02 10:57:15 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737028914 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.737028914
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.379213700
Short name T937
Test name
Test status
Simulation time 90733941 ps
CPU time 0.53 seconds
Started Oct 02 10:57:13 PM UTC 24
Finished Oct 02 10:57:15 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379213700 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.379213700
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.4129449682
Short name T948
Test name
Test status
Simulation time 27734048 ps
CPU time 0.66 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:16 PM UTC 24
Peak memory 209892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129449682 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_same_csr_outstanding.4129449682
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1311947417
Short name T945
Test name
Test status
Simulation time 63158614 ps
CPU time 1.31 seconds
Started Oct 02 10:57:13 PM UTC 24
Finished Oct 02 10:57:15 PM UTC 24
Peak memory 210084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311947417 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.1311947417
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1127023402
Short name T947
Test name
Test status
Simulation time 330259720 ps
CPU time 1.44 seconds
Started Oct 02 10:57:13 PM UTC 24
Finished Oct 02 10:57:15 PM UTC 24
Peak memory 210740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127023402 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err.1127023402
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3629487669
Short name T953
Test name
Test status
Simulation time 68157834 ps
CPU time 0.66 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 209828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3629487669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_
with_rand_reset.3629487669
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.2540130837
Short name T950
Test name
Test status
Simulation time 46152474 ps
CPU time 0.59 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:16 PM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540130837 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.2540130837
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.116928763
Short name T949
Test name
Test status
Simulation time 68399395 ps
CPU time 0.55 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:16 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116928763 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.116928763
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3789054846
Short name T955
Test name
Test status
Simulation time 42485286 ps
CPU time 0.82 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789054846 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_same_csr_outstanding.3789054846
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.531436104
Short name T977
Test name
Test status
Simulation time 422744861 ps
CPU time 2.33 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:18 PM UTC 24
Peak memory 211116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531436104 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.531436104
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.1135959559
Short name T959
Test name
Test status
Simulation time 101846283 ps
CPU time 1.03 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 211188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135959559 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err.1135959559
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1733111801
Short name T964
Test name
Test status
Simulation time 134263646 ps
CPU time 0.87 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 211232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1733111801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_
with_rand_reset.1733111801
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.3443925389
Short name T951
Test name
Test status
Simulation time 37206705 ps
CPU time 0.61 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 206956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443925389 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.3443925389
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.4157644633
Short name T952
Test name
Test status
Simulation time 31305744 ps
CPU time 0.55 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157644633 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.4157644633
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.4170012202
Short name T958
Test name
Test status
Simulation time 47999720 ps
CPU time 0.71 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 209092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170012202 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_same_csr_outstanding.4170012202
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.552402256
Short name T973
Test name
Test status
Simulation time 95879702 ps
CPU time 1.19 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 211120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552402256 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.552402256
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1951343929
Short name T162
Test name
Test status
Simulation time 206551209 ps
CPU time 1.02 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 211180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951343929 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err.1951343929
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.819530636
Short name T976
Test name
Test status
Simulation time 41467456 ps
CPU time 1.06 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:18 PM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=819530636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_w
ith_rand_reset.819530636
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.2805177810
Short name T961
Test name
Test status
Simulation time 49815665 ps
CPU time 0.62 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 206956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805177810 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.2805177810
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.3545871517
Short name T956
Test name
Test status
Simulation time 44559256 ps
CPU time 0.56 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 207056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545871517 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.3545871517
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3501289131
Short name T962
Test name
Test status
Simulation time 21464169 ps
CPU time 0.68 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501289131 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_same_csr_outstanding.3501289131
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.4284928245
Short name T978
Test name
Test status
Simulation time 52235296 ps
CPU time 2.12 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:18 PM UTC 24
Peak memory 211100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284928245 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.4284928245
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3713777098
Short name T979
Test name
Test status
Simulation time 451364932 ps
CPU time 2.08 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:18 PM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713777098 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err.3713777098
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2223590619
Short name T171
Test name
Test status
Simulation time 221784950 ps
CPU time 0.68 seconds
Started Oct 02 10:56:42 PM UTC 24
Finished Oct 02 10:56:55 PM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223590619 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.2223590619
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2101285069
Short name T889
Test name
Test status
Simulation time 305074209 ps
CPU time 3.05 seconds
Started Oct 02 10:56:42 PM UTC 24
Finished Oct 02 10:56:58 PM UTC 24
Peak memory 211144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101285069 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.2101285069
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2864623015
Short name T68
Test name
Test status
Simulation time 25301737 ps
CPU time 0.58 seconds
Started Oct 02 10:56:42 PM UTC 24
Finished Oct 02 10:56:45 PM UTC 24
Peak memory 207012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864623015 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.2864623015
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1805580989
Short name T65
Test name
Test status
Simulation time 60546914 ps
CPU time 1.22 seconds
Started Oct 02 10:56:43 PM UTC 24
Finished Oct 02 10:56:56 PM UTC 24
Peak memory 211180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1805580989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_w
ith_rand_reset.1805580989
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.831395790
Short name T110
Test name
Test status
Simulation time 17323730 ps
CPU time 0.6 seconds
Started Oct 02 10:56:42 PM UTC 24
Finished Oct 02 10:56:45 PM UTC 24
Peak memory 208172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831395790 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.831395790
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.365887780
Short name T122
Test name
Test status
Simulation time 55485109 ps
CPU time 0.68 seconds
Started Oct 02 10:56:43 PM UTC 24
Finished Oct 02 10:56:55 PM UTC 24
Peak memory 209340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365887780 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_same_csr_outstanding.365887780
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.3137261562
Short name T67
Test name
Test status
Simulation time 52936036 ps
CPU time 1.28 seconds
Started Oct 02 10:56:41 PM UTC 24
Finished Oct 02 10:56:50 PM UTC 24
Peak memory 211152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137261562 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.3137261562
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2530302714
Short name T57
Test name
Test status
Simulation time 363502819 ps
CPU time 0.97 seconds
Started Oct 02 10:56:42 PM UTC 24
Finished Oct 02 10:56:46 PM UTC 24
Peak memory 210896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530302714 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.2530302714
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.248812247
Short name T957
Test name
Test status
Simulation time 39476049 ps
CPU time 0.56 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248812247 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.248812247
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/20.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.531935548
Short name T963
Test name
Test status
Simulation time 18192972 ps
CPU time 0.6 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531935548 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.531935548
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/21.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.703139087
Short name T966
Test name
Test status
Simulation time 21227520 ps
CPU time 0.59 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703139087 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.703139087
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/22.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.385692408
Short name T968
Test name
Test status
Simulation time 26754182 ps
CPU time 0.57 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 206996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385692408 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.385692408
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.216986711
Short name T967
Test name
Test status
Simulation time 34717415 ps
CPU time 0.56 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216986711 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.216986711
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/24.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.3698058955
Short name T974
Test name
Test status
Simulation time 31970117 ps
CPU time 0.6 seconds
Started Oct 02 10:57:15 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698058955 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.3698058955
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.1794331352
Short name T969
Test name
Test status
Simulation time 17173885 ps
CPU time 0.58 seconds
Started Oct 02 10:57:16 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 207044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794331352 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.1794331352
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.3754442837
Short name T972
Test name
Test status
Simulation time 21741182 ps
CPU time 0.57 seconds
Started Oct 02 10:57:16 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 207052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754442837 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.3754442837
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.3036626511
Short name T971
Test name
Test status
Simulation time 20586546 ps
CPU time 0.56 seconds
Started Oct 02 10:57:16 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036626511 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.3036626511
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.571623975
Short name T982
Test name
Test status
Simulation time 33730660 ps
CPU time 0.55 seconds
Started Oct 02 10:57:16 PM UTC 24
Finished Oct 02 10:57:20 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571623975 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.571623975
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3003450492
Short name T170
Test name
Test status
Simulation time 118474808 ps
CPU time 0.69 seconds
Started Oct 02 10:56:46 PM UTC 24
Finished Oct 02 10:56:51 PM UTC 24
Peak memory 208968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003450492 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.3003450492
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2254168975
Short name T888
Test name
Test status
Simulation time 130553941 ps
CPU time 1.71 seconds
Started Oct 02 10:56:46 PM UTC 24
Finished Oct 02 10:56:52 PM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254168975 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.2254168975
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.1285827051
Short name T922
Test name
Test status
Simulation time 78448602 ps
CPU time 0.66 seconds
Started Oct 02 10:56:45 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 208596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285827051 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.1285827051
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.3249588365
Short name T172
Test name
Test status
Simulation time 61657439 ps
CPU time 0.64 seconds
Started Oct 02 10:56:46 PM UTC 24
Finished Oct 02 10:56:51 PM UTC 24
Peak memory 210004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3249588365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_w
ith_rand_reset.3249588365
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.2666998109
Short name T111
Test name
Test status
Simulation time 19561742 ps
CPU time 0.62 seconds
Started Oct 02 10:56:46 PM UTC 24
Finished Oct 02 10:56:51 PM UTC 24
Peak memory 208444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666998109 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.2666998109
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.424863411
Short name T121
Test name
Test status
Simulation time 146137216 ps
CPU time 0.8 seconds
Started Oct 02 10:56:46 PM UTC 24
Finished Oct 02 10:56:51 PM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424863411 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_same_csr_outstanding.424863411
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.234397203
Short name T75
Test name
Test status
Simulation time 376128592 ps
CPU time 1.89 seconds
Started Oct 02 10:56:43 PM UTC 24
Finished Oct 02 10:56:57 PM UTC 24
Peak memory 211180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234397203 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.234397203
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.3002052715
Short name T975
Test name
Test status
Simulation time 33344652 ps
CPU time 0.54 seconds
Started Oct 02 10:57:16 PM UTC 24
Finished Oct 02 10:57:17 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002052715 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.3002052715
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.1929974017
Short name T980
Test name
Test status
Simulation time 26742505 ps
CPU time 0.53 seconds
Started Oct 02 10:57:16 PM UTC 24
Finished Oct 02 10:57:20 PM UTC 24
Peak memory 206640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929974017 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.1929974017
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.1113042933
Short name T981
Test name
Test status
Simulation time 18265187 ps
CPU time 0.59 seconds
Started Oct 02 10:57:16 PM UTC 24
Finished Oct 02 10:57:20 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113042933 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.1113042933
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.1443706648
Short name T984
Test name
Test status
Simulation time 85186456 ps
CPU time 0.55 seconds
Started Oct 02 10:57:16 PM UTC 24
Finished Oct 02 10:57:20 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443706648 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.1443706648
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.1623596335
Short name T985
Test name
Test status
Simulation time 22513582 ps
CPU time 0.61 seconds
Started Oct 02 10:57:16 PM UTC 24
Finished Oct 02 10:57:21 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623596335 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.1623596335
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.778078468
Short name T983
Test name
Test status
Simulation time 16212806 ps
CPU time 0.54 seconds
Started Oct 02 10:57:16 PM UTC 24
Finished Oct 02 10:57:20 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778078468 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.778078468
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.4293799829
Short name T986
Test name
Test status
Simulation time 34496808 ps
CPU time 0.54 seconds
Started Oct 02 10:57:16 PM UTC 24
Finished Oct 02 10:57:21 PM UTC 24
Peak memory 206952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293799829 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.4293799829
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.2388103795
Short name T987
Test name
Test status
Simulation time 21096882 ps
CPU time 0.57 seconds
Started Oct 02 10:57:26 PM UTC 24
Finished Oct 02 10:57:28 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388103795 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.2388103795
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.1686338430
Short name T991
Test name
Test status
Simulation time 20428694 ps
CPU time 0.57 seconds
Started Oct 02 10:57:26 PM UTC 24
Finished Oct 02 10:57:28 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686338430 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.1686338430
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.512632010
Short name T993
Test name
Test status
Simulation time 59951658 ps
CPU time 0.55 seconds
Started Oct 02 10:57:26 PM UTC 24
Finished Oct 02 10:57:28 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512632010 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.512632010
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3898866927
Short name T898
Test name
Test status
Simulation time 22772529 ps
CPU time 0.72 seconds
Started Oct 02 10:56:51 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 209712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898866927 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.3898866927
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.3562448205
Short name T119
Test name
Test status
Simulation time 161288986 ps
CPU time 2.59 seconds
Started Oct 02 10:56:51 PM UTC 24
Finished Oct 02 10:57:12 PM UTC 24
Peak memory 211092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562448205 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.3562448205
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3405744507
Short name T114
Test name
Test status
Simulation time 50581533 ps
CPU time 0.6 seconds
Started Oct 02 10:56:51 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 206596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405744507 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.3405744507
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1673928923
Short name T901
Test name
Test status
Simulation time 58130551 ps
CPU time 0.74 seconds
Started Oct 02 10:56:52 PM UTC 24
Finished Oct 02 10:57:11 PM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1673928923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_w
ith_rand_reset.1673928923
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.1014741160
Short name T115
Test name
Test status
Simulation time 45049616 ps
CPU time 0.58 seconds
Started Oct 02 10:56:51 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 208444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014741160 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.1014741160
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.2381691456
Short name T167
Test name
Test status
Simulation time 41539576 ps
CPU time 0.53 seconds
Started Oct 02 10:56:51 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 206960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381691456 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.2381691456
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2195245190
Short name T900
Test name
Test status
Simulation time 74624605 ps
CPU time 0.68 seconds
Started Oct 02 10:56:51 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 209096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195245190 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_same_csr_outstanding.2195245190
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.3352973078
Short name T64
Test name
Test status
Simulation time 48485603 ps
CPU time 2.1 seconds
Started Oct 02 10:56:46 PM UTC 24
Finished Oct 02 10:56:52 PM UTC 24
Peak memory 211136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352973078 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.3352973078
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2759927167
Short name T58
Test name
Test status
Simulation time 340422261 ps
CPU time 1.48 seconds
Started Oct 02 10:56:46 PM UTC 24
Finished Oct 02 10:56:52 PM UTC 24
Peak memory 211112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759927167 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.2759927167
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.669459243
Short name T990
Test name
Test status
Simulation time 29405438 ps
CPU time 0.55 seconds
Started Oct 02 10:57:26 PM UTC 24
Finished Oct 02 10:57:28 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669459243 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.669459243
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.3101405776
Short name T994
Test name
Test status
Simulation time 19863465 ps
CPU time 0.56 seconds
Started Oct 02 10:57:26 PM UTC 24
Finished Oct 02 10:57:28 PM UTC 24
Peak memory 206892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101405776 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.3101405776
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.1570036626
Short name T988
Test name
Test status
Simulation time 17481571 ps
CPU time 0.59 seconds
Started Oct 02 10:57:26 PM UTC 24
Finished Oct 02 10:57:28 PM UTC 24
Peak memory 206816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570036626 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.1570036626
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.2128218172
Short name T965
Test name
Test status
Simulation time 23594642 ps
CPU time 0.56 seconds
Started Oct 02 10:57:26 PM UTC 24
Finished Oct 02 10:57:28 PM UTC 24
Peak memory 206884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128218172 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2128218172
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.2163886717
Short name T970
Test name
Test status
Simulation time 24734492 ps
CPU time 0.56 seconds
Started Oct 02 10:57:26 PM UTC 24
Finished Oct 02 10:57:28 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163886717 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.2163886717
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.905997308
Short name T995
Test name
Test status
Simulation time 48851654 ps
CPU time 0.54 seconds
Started Oct 02 10:57:26 PM UTC 24
Finished Oct 02 10:57:28 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905997308 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.905997308
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/45.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.3092332282
Short name T989
Test name
Test status
Simulation time 34289250 ps
CPU time 0.57 seconds
Started Oct 02 10:57:26 PM UTC 24
Finished Oct 02 10:57:28 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092332282 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.3092332282
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/46.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.2619045558
Short name T927
Test name
Test status
Simulation time 19447229 ps
CPU time 0.58 seconds
Started Oct 02 10:57:26 PM UTC 24
Finished Oct 02 10:57:28 PM UTC 24
Peak memory 206980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619045558 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.2619045558
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/47.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.3998476305
Short name T960
Test name
Test status
Simulation time 72617206 ps
CPU time 0.57 seconds
Started Oct 02 10:57:26 PM UTC 24
Finished Oct 02 10:57:28 PM UTC 24
Peak memory 207068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998476305 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.3998476305
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.326195322
Short name T992
Test name
Test status
Simulation time 21933080 ps
CPU time 0.6 seconds
Started Oct 02 10:57:26 PM UTC 24
Finished Oct 02 10:57:28 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326195322 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.326195322
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.544417674
Short name T906
Test name
Test status
Simulation time 69208580 ps
CPU time 0.86 seconds
Started Oct 02 10:56:52 PM UTC 24
Finished Oct 02 10:57:11 PM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=544417674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_wi
th_rand_reset.544417674
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.1802701519
Short name T116
Test name
Test status
Simulation time 21101595 ps
CPU time 0.63 seconds
Started Oct 02 10:56:52 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 208360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802701519 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.1802701519
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.3464614528
Short name T168
Test name
Test status
Simulation time 24027032 ps
CPU time 0.58 seconds
Started Oct 02 10:56:52 PM UTC 24
Finished Oct 02 10:57:11 PM UTC 24
Peak memory 206920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464614528 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.3464614528
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1441621405
Short name T904
Test name
Test status
Simulation time 74924420 ps
CPU time 0.69 seconds
Started Oct 02 10:56:52 PM UTC 24
Finished Oct 02 10:57:11 PM UTC 24
Peak memory 210308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441621405 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_same_csr_outstanding.1441621405
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.3724590044
Short name T908
Test name
Test status
Simulation time 29065969 ps
CPU time 1.2 seconds
Started Oct 02 10:56:52 PM UTC 24
Finished Oct 02 10:57:11 PM UTC 24
Peak memory 211232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724590044 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.3724590044
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3946988414
Short name T159
Test name
Test status
Simulation time 180890004 ps
CPU time 1.48 seconds
Started Oct 02 10:56:52 PM UTC 24
Finished Oct 02 10:57:11 PM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946988414 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err.3946988414
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2584430397
Short name T76
Test name
Test status
Simulation time 105163963 ps
CPU time 1.09 seconds
Started Oct 02 10:56:53 PM UTC 24
Finished Oct 02 10:57:06 PM UTC 24
Peak memory 211120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2584430397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_w
ith_rand_reset.2584430397
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.1695620891
Short name T123
Test name
Test status
Simulation time 47891885 ps
CPU time 0.67 seconds
Started Oct 02 10:56:53 PM UTC 24
Finished Oct 02 10:57:13 PM UTC 24
Peak memory 208444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695620891 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.1695620891
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.4212472771
Short name T916
Test name
Test status
Simulation time 20994895 ps
CPU time 0.6 seconds
Started Oct 02 10:56:53 PM UTC 24
Finished Oct 02 10:57:13 PM UTC 24
Peak memory 207020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212472771 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.4212472771
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1212338571
Short name T919
Test name
Test status
Simulation time 41287993 ps
CPU time 0.81 seconds
Started Oct 02 10:56:53 PM UTC 24
Finished Oct 02 10:57:13 PM UTC 24
Peak memory 209828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212338571 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_same_csr_outstanding.1212338571
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.1244210272
Short name T895
Test name
Test status
Simulation time 136922370 ps
CPU time 2.66 seconds
Started Oct 02 10:56:52 PM UTC 24
Finished Oct 02 10:57:13 PM UTC 24
Peak memory 211148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244210272 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.1244210272
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.2475105502
Short name T890
Test name
Test status
Simulation time 51119914 ps
CPU time 0.94 seconds
Started Oct 02 10:56:56 PM UTC 24
Finished Oct 02 10:57:05 PM UTC 24
Peak memory 210860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2475105502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_w
ith_rand_reset.2475105502
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.607575804
Short name T126
Test name
Test status
Simulation time 47950266 ps
CPU time 0.59 seconds
Started Oct 02 10:56:55 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 208172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607575804 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.607575804
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3193164608
Short name T896
Test name
Test status
Simulation time 42932723 ps
CPU time 0.79 seconds
Started Oct 02 10:56:55 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193164608 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_same_csr_outstanding.3193164608
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.2821602422
Short name T921
Test name
Test status
Simulation time 75496667 ps
CPU time 1.47 seconds
Started Oct 02 10:56:53 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 211184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821602422 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.2821602422
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.3576404139
Short name T69
Test name
Test status
Simulation time 337316893 ps
CPU time 1.32 seconds
Started Oct 02 10:56:55 PM UTC 24
Finished Oct 02 10:57:11 PM UTC 24
Peak memory 211144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576404139 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.3576404139
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.3362994336
Short name T897
Test name
Test status
Simulation time 51186435 ps
CPU time 0.64 seconds
Started Oct 02 10:56:59 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3362994336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_w
ith_rand_reset.3362994336
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.504770661
Short name T112
Test name
Test status
Simulation time 22206033 ps
CPU time 0.6 seconds
Started Oct 02 10:56:56 PM UTC 24
Finished Oct 02 10:57:05 PM UTC 24
Peak memory 208856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504770661 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.504770661
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.2088243015
Short name T164
Test name
Test status
Simulation time 21856591 ps
CPU time 0.53 seconds
Started Oct 02 10:56:56 PM UTC 24
Finished Oct 02 10:57:05 PM UTC 24
Peak memory 206960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088243015 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.2088243015
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.3738773479
Short name T899
Test name
Test status
Simulation time 33385883 ps
CPU time 0.78 seconds
Started Oct 02 10:56:57 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 209828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738773479 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_same_csr_outstanding.3738773479
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.413081148
Short name T892
Test name
Test status
Simulation time 100376866 ps
CPU time 2 seconds
Started Oct 02 10:56:56 PM UTC 24
Finished Oct 02 10:57:06 PM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413081148 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.413081148
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.353075405
Short name T158
Test name
Test status
Simulation time 108370567 ps
CPU time 1.03 seconds
Started Oct 02 10:56:56 PM UTC 24
Finished Oct 02 10:57:06 PM UTC 24
Peak memory 211140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353075405 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.353075405
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2740610609
Short name T905
Test name
Test status
Simulation time 160396839 ps
CPU time 0.79 seconds
Started Oct 02 10:57:06 PM UTC 24
Finished Oct 02 10:57:11 PM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2740610609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_w
ith_rand_reset.2740610609
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.1055631580
Short name T903
Test name
Test status
Simulation time 19626777 ps
CPU time 0.6 seconds
Started Oct 02 10:57:06 PM UTC 24
Finished Oct 02 10:57:11 PM UTC 24
Peak memory 207016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055631580 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.1055631580
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.3650484811
Short name T169
Test name
Test status
Simulation time 49635319 ps
CPU time 0.54 seconds
Started Oct 02 10:57:06 PM UTC 24
Finished Oct 02 10:57:11 PM UTC 24
Peak memory 206960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650484811 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.3650484811
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.1281906175
Short name T902
Test name
Test status
Simulation time 174122041 ps
CPU time 0.68 seconds
Started Oct 02 10:57:06 PM UTC 24
Finished Oct 02 10:57:11 PM UTC 24
Peak memory 209096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281906175 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_same_csr_outstanding.1281906175
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.116961333
Short name T914
Test name
Test status
Simulation time 190936372 ps
CPU time 2.2 seconds
Started Oct 02 10:57:06 PM UTC 24
Finished Oct 02 10:57:12 PM UTC 24
Peak memory 211140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116961333 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.116961333
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.528494214
Short name T160
Test name
Test status
Simulation time 179985958 ps
CPU time 1.46 seconds
Started Oct 02 10:57:06 PM UTC 24
Finished Oct 02 10:57:11 PM UTC 24
Peak memory 211244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528494214 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.528494214
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.3906741366
Short name T4
Test name
Test status
Simulation time 67511853 ps
CPU time 1.13 seconds
Started Oct 02 10:52:59 PM UTC 24
Finished Oct 02 10:53:01 PM UTC 24
Peak memory 210624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906741366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.3906741366
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.573123669
Short name T13
Test name
Test status
Simulation time 60592914 ps
CPU time 1.14 seconds
Started Oct 02 10:53:02 PM UTC 24
Finished Oct 02 10:53:04 PM UTC 24
Peak memory 209032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573123669 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disable_rom_integrity_check.573123669
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2474880173
Short name T7
Test name
Test status
Simulation time 30631871 ps
CPU time 0.98 seconds
Started Oct 02 10:53:00 PM UTC 24
Finished Oct 02 10:53:02 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474880173 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_malfunc.2474880173
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.3588422218
Short name T8
Test name
Test status
Simulation time 62075334 ps
CPU time 0.89 seconds
Started Oct 02 10:53:00 PM UTC 24
Finished Oct 02 10:53:02 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588422218 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3588422218
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.2614728574
Short name T6
Test name
Test status
Simulation time 229643459 ps
CPU time 1.84 seconds
Started Oct 02 10:52:59 PM UTC 24
Finished Oct 02 10:53:02 PM UTC 24
Peak memory 209472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614728574 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wakeup_race.2614728574
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.2924395545
Short name T2
Test name
Test status
Simulation time 99550312 ps
CPU time 1.02 seconds
Started Oct 02 10:52:58 PM UTC 24
Finished Oct 02 10:53:00 PM UTC 24
Peak memory 208640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924395545 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.2924395545
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.3962108035
Short name T20
Test name
Test status
Simulation time 491708480 ps
CPU time 1.69 seconds
Started Oct 02 10:53:02 PM UTC 24
Finished Oct 02 10:53:04 PM UTC 24
Peak memory 237592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962108035 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.3962108035
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.2783741474
Short name T26
Test name
Test status
Simulation time 305155171 ps
CPU time 1.57 seconds
Started Oct 02 10:53:00 PM UTC 24
Finished Oct 02 10:53:03 PM UTC 24
Peak memory 210628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783741474 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_ctrl_config_regwen.2783741474
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2382936772
Short name T31
Test name
Test status
Simulation time 849598745 ps
CPU time 3.48 seconds
Started Oct 02 10:53:00 PM UTC 24
Finished Oct 02 10:53:05 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382936772 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.2382936772
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2453906341
Short name T9
Test name
Test status
Simulation time 143619247 ps
CPU time 1.24 seconds
Started Oct 02 10:53:00 PM UTC 24
Finished Oct 02 10:53:03 PM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453906341 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2453906341
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.3449623123
Short name T1
Test name
Test status
Simulation time 62598169 ps
CPU time 0.98 seconds
Started Oct 02 10:52:58 PM UTC 24
Finished Oct 02 10:53:00 PM UTC 24
Peak memory 208872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449623123 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.3449623123
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.275901641
Short name T3
Test name
Test status
Simulation time 51971273 ps
CPU time 0.85 seconds
Started Oct 02 10:52:59 PM UTC 24
Finished Oct 02 10:53:01 PM UTC 24
Peak memory 208564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275901641 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.275901641
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.10456396
Short name T15
Test name
Test status
Simulation time 38074725 ps
CPU time 1.26 seconds
Started Oct 02 10:53:03 PM UTC 24
Finished Oct 02 10:53:06 PM UTC 24
Peak memory 210892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10456396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=
pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.10456396
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.1623585188
Short name T27
Test name
Test status
Simulation time 72381247 ps
CPU time 0.97 seconds
Started Oct 02 10:53:05 PM UTC 24
Finished Oct 02 10:53:07 PM UTC 24
Peak memory 208620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623585188 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disable_rom_integrity_check.1623585188
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.4277809280
Short name T11
Test name
Test status
Simulation time 29796381 ps
CPU time 0.69 seconds
Started Oct 02 10:53:05 PM UTC 24
Finished Oct 02 10:53:06 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277809280 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_malfunc.4277809280
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.3436319670
Short name T141
Test name
Test status
Simulation time 130222998 ps
CPU time 1.34 seconds
Started Oct 02 10:53:05 PM UTC 24
Finished Oct 02 10:53:07 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436319670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.3436319670
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.676244851
Short name T18
Test name
Test status
Simulation time 32992782 ps
CPU time 0.98 seconds
Started Oct 02 10:53:05 PM UTC 24
Finished Oct 02 10:53:07 PM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676244851 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.676244851
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.3814309912
Short name T36
Test name
Test status
Simulation time 29056296 ps
CPU time 0.85 seconds
Started Oct 02 10:53:05 PM UTC 24
Finished Oct 02 10:53:07 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814309912 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.3814309912
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.3827858067
Short name T34
Test name
Test status
Simulation time 244442403 ps
CPU time 1.37 seconds
Started Oct 02 10:53:03 PM UTC 24
Finished Oct 02 10:53:06 PM UTC 24
Peak memory 209472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827858067 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wakeup_race.3827858067
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.3125346627
Short name T33
Test name
Test status
Simulation time 60763121 ps
CPU time 1.31 seconds
Started Oct 02 10:53:03 PM UTC 24
Finished Oct 02 10:53:05 PM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125346627 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.3125346627
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.668241862
Short name T39
Test name
Test status
Simulation time 162991252 ps
CPU time 1.04 seconds
Started Oct 02 10:53:05 PM UTC 24
Finished Oct 02 10:53:07 PM UTC 24
Peak memory 220304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668241862 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.668241862
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3804075854
Short name T80
Test name
Test status
Simulation time 1338930400 ps
CPU time 3.29 seconds
Started Oct 02 10:53:03 PM UTC 24
Finished Oct 02 10:53:08 PM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804075854 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.3804075854
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3178387835
Short name T38
Test name
Test status
Simulation time 1124852384 ps
CPU time 2.41 seconds
Started Oct 02 10:53:03 PM UTC 24
Finished Oct 02 10:53:07 PM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178387835 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.3178387835
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.594058580
Short name T181
Test name
Test status
Simulation time 52918011 ps
CPU time 1.16 seconds
Started Oct 02 10:53:05 PM UTC 24
Finished Oct 02 10:53:07 PM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594058580 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_mubi.594058580
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.2512546066
Short name T40
Test name
Test status
Simulation time 55114215 ps
CPU time 0.67 seconds
Started Oct 02 10:53:02 PM UTC 24
Finished Oct 02 10:53:04 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512546066 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.2512546066
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.186317980
Short name T83
Test name
Test status
Simulation time 487240209 ps
CPU time 1.95 seconds
Started Oct 02 10:53:06 PM UTC 24
Finished Oct 02 10:53:09 PM UTC 24
Peak memory 209984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186317980 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.186317980
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.739816341
Short name T25
Test name
Test status
Simulation time 7123725564 ps
CPU time 11.44 seconds
Started Oct 02 10:53:06 PM UTC 24
Finished Oct 02 10:53:19 PM UTC 24
Peak memory 211632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=739816341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_
stress_all_with_rand_reset.739816341
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.3550154301
Short name T35
Test name
Test status
Simulation time 129940275 ps
CPU time 1.43 seconds
Started Oct 02 10:53:03 PM UTC 24
Finished Oct 02 10:53:06 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550154301 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.3550154301
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.727940349
Short name T32
Test name
Test status
Simulation time 60932050 ps
CPU time 1.04 seconds
Started Oct 02 10:53:03 PM UTC 24
Finished Oct 02 10:53:05 PM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727940349 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.727940349
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.1783486185
Short name T107
Test name
Test status
Simulation time 110177584 ps
CPU time 0.89 seconds
Started Oct 02 10:53:30 PM UTC 24
Finished Oct 02 10:53:32 PM UTC 24
Peak memory 210004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783486185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.1783486185
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.3488197135
Short name T176
Test name
Test status
Simulation time 160778281 ps
CPU time 0.85 seconds
Started Oct 02 10:53:32 PM UTC 24
Finished Oct 02 10:53:34 PM UTC 24
Peak memory 208620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488197135 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disable_rom_integrity_check.3488197135
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.3348268100
Short name T275
Test name
Test status
Simulation time 39353990 ps
CPU time 0.78 seconds
Started Oct 02 10:53:30 PM UTC 24
Finished Oct 02 10:53:32 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348268100 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_malfunc.3348268100
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.2756813474
Short name T286
Test name
Test status
Simulation time 201054941 ps
CPU time 1.09 seconds
Started Oct 02 10:53:32 PM UTC 24
Finished Oct 02 10:53:34 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756813474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.2756813474
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.1951987562
Short name T281
Test name
Test status
Simulation time 41655432 ps
CPU time 0.77 seconds
Started Oct 02 10:53:32 PM UTC 24
Finished Oct 02 10:53:34 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951987562 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.1951987562
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.3107864611
Short name T273
Test name
Test status
Simulation time 66489704 ps
CPU time 0.71 seconds
Started Oct 02 10:53:30 PM UTC 24
Finished Oct 02 10:53:32 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107864611 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.3107864611
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.3228773311
Short name T272
Test name
Test status
Simulation time 44672070 ps
CPU time 0.91 seconds
Started Oct 02 10:53:30 PM UTC 24
Finished Oct 02 10:53:32 PM UTC 24
Peak memory 208988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228773311 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wakeup_race.3228773311
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.929825459
Short name T270
Test name
Test status
Simulation time 35444985 ps
CPU time 0.84 seconds
Started Oct 02 10:53:30 PM UTC 24
Finished Oct 02 10:53:32 PM UTC 24
Peak memory 208640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929825459 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.929825459
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.2981580987
Short name T285
Test name
Test status
Simulation time 124237647 ps
CPU time 1 seconds
Started Oct 02 10:53:32 PM UTC 24
Finished Oct 02 10:53:34 PM UTC 24
Peak memory 220724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981580987 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.2981580987
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.2457298787
Short name T278
Test name
Test status
Simulation time 218979802 ps
CPU time 1.19 seconds
Started Oct 02 10:53:30 PM UTC 24
Finished Oct 02 10:53:33 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457298787 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_ctrl_config_regwen.2457298787
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2318506489
Short name T280
Test name
Test status
Simulation time 1549220997 ps
CPU time 2.22 seconds
Started Oct 02 10:53:30 PM UTC 24
Finished Oct 02 10:53:34 PM UTC 24
Peak memory 211504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318506489 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2318506489
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4207875385
Short name T282
Test name
Test status
Simulation time 993696267 ps
CPU time 2.32 seconds
Started Oct 02 10:53:30 PM UTC 24
Finished Oct 02 10:53:34 PM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207875385 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.4207875385
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2713251835
Short name T276
Test name
Test status
Simulation time 52478620 ps
CPU time 1.03 seconds
Started Oct 02 10:53:30 PM UTC 24
Finished Oct 02 10:53:32 PM UTC 24
Peak memory 209152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713251835 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2713251835
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.3329055736
Short name T271
Test name
Test status
Simulation time 37646930 ps
CPU time 0.83 seconds
Started Oct 02 10:53:30 PM UTC 24
Finished Oct 02 10:53:32 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329055736 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.3329055736
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.3106933555
Short name T109
Test name
Test status
Simulation time 1838640927 ps
CPU time 4.91 seconds
Started Oct 02 10:53:32 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 211412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106933555 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.3106933555
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.2029377770
Short name T130
Test name
Test status
Simulation time 4935845555 ps
CPU time 6.27 seconds
Started Oct 02 10:53:32 PM UTC 24
Finished Oct 02 10:53:39 PM UTC 24
Peak memory 211696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2029377770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmg
r_stress_all_with_rand_reset.2029377770
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.3303311951
Short name T274
Test name
Test status
Simulation time 137523508 ps
CPU time 1.06 seconds
Started Oct 02 10:53:30 PM UTC 24
Finished Oct 02 10:53:32 PM UTC 24
Peak memory 208356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303311951 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.3303311951
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.2434048472
Short name T277
Test name
Test status
Simulation time 294769000 ps
CPU time 1.42 seconds
Started Oct 02 10:53:30 PM UTC 24
Finished Oct 02 10:53:33 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434048472 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.2434048472
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/10.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.17494576
Short name T108
Test name
Test status
Simulation time 45541703 ps
CPU time 1.02 seconds
Started Oct 02 10:53:32 PM UTC 24
Finished Oct 02 10:53:35 PM UTC 24
Peak memory 210268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17494576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=
pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.17494576
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.994160257
Short name T292
Test name
Test status
Simulation time 38579390 ps
CPU time 0.76 seconds
Started Oct 02 10:53:34 PM UTC 24
Finished Oct 02 10:53:36 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994160257 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_malfunc.994160257
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.2353885146
Short name T297
Test name
Test status
Simulation time 114572945 ps
CPU time 1.22 seconds
Started Oct 02 10:53:34 PM UTC 24
Finished Oct 02 10:53:36 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353885146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.2353885146
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.624847731
Short name T295
Test name
Test status
Simulation time 66029440 ps
CPU time 0.74 seconds
Started Oct 02 10:53:34 PM UTC 24
Finished Oct 02 10:53:36 PM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624847731 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.624847731
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.1939720821
Short name T291
Test name
Test status
Simulation time 158308725 ps
CPU time 0.67 seconds
Started Oct 02 10:53:34 PM UTC 24
Finished Oct 02 10:53:35 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939720821 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.1939720821
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.2109385692
Short name T289
Test name
Test status
Simulation time 130852491 ps
CPU time 0.9 seconds
Started Oct 02 10:53:32 PM UTC 24
Finished Oct 02 10:53:34 PM UTC 24
Peak memory 208868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109385692 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_wakeup_race.2109385692
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.3025383193
Short name T287
Test name
Test status
Simulation time 49743814 ps
CPU time 0.74 seconds
Started Oct 02 10:53:32 PM UTC 24
Finished Oct 02 10:53:34 PM UTC 24
Peak memory 208352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025383193 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.3025383193
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.2851971940
Short name T299
Test name
Test status
Simulation time 161529583 ps
CPU time 1.09 seconds
Started Oct 02 10:53:34 PM UTC 24
Finished Oct 02 10:53:36 PM UTC 24
Peak memory 219976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851971940 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.2851971940
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.4208330494
Short name T294
Test name
Test status
Simulation time 85465680 ps
CPU time 0.88 seconds
Started Oct 02 10:53:34 PM UTC 24
Finished Oct 02 10:53:36 PM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208330494 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_ctrl_config_regwen.4208330494
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1730293633
Short name T298
Test name
Test status
Simulation time 1030764803 ps
CPU time 2.62 seconds
Started Oct 02 10:53:32 PM UTC 24
Finished Oct 02 10:53:36 PM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730293633 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1730293633
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3445067341
Short name T300
Test name
Test status
Simulation time 1756820811 ps
CPU time 1.99 seconds
Started Oct 02 10:53:34 PM UTC 24
Finished Oct 02 10:53:37 PM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445067341 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3445067341
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.3499241502
Short name T293
Test name
Test status
Simulation time 67967460 ps
CPU time 0.95 seconds
Started Oct 02 10:53:34 PM UTC 24
Finished Oct 02 10:53:36 PM UTC 24
Peak memory 209148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499241502 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_mubi.3499241502
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.2588377749
Short name T284
Test name
Test status
Simulation time 35308426 ps
CPU time 0.74 seconds
Started Oct 02 10:53:32 PM UTC 24
Finished Oct 02 10:53:34 PM UTC 24
Peak memory 208320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588377749 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.2588377749
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.3311023916
Short name T318
Test name
Test status
Simulation time 1545873862 ps
CPU time 5.19 seconds
Started Oct 02 10:53:34 PM UTC 24
Finished Oct 02 10:53:41 PM UTC 24
Peak memory 211600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311023916 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.3311023916
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.2127499146
Short name T337
Test name
Test status
Simulation time 8704208911 ps
CPU time 6.86 seconds
Started Oct 02 10:53:34 PM UTC 24
Finished Oct 02 10:53:42 PM UTC 24
Peak memory 211752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2127499146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmg
r_stress_all_with_rand_reset.2127499146
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.303390187
Short name T288
Test name
Test status
Simulation time 94710748 ps
CPU time 0.8 seconds
Started Oct 02 10:53:32 PM UTC 24
Finished Oct 02 10:53:34 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303390187 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.303390187
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.1302750912
Short name T290
Test name
Test status
Simulation time 159657238 ps
CPU time 0.92 seconds
Started Oct 02 10:53:32 PM UTC 24
Finished Oct 02 10:53:34 PM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302750912 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.1302750912
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/11.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.61364786
Short name T301
Test name
Test status
Simulation time 65063414 ps
CPU time 1.03 seconds
Started Oct 02 10:53:35 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 210592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61364786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=
pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.61364786
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.854733122
Short name T257
Test name
Test status
Simulation time 43745289 ps
CPU time 0.73 seconds
Started Oct 02 10:53:36 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854733122 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst_malfunc.854733122
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.2327863971
Short name T283
Test name
Test status
Simulation time 110127527 ps
CPU time 1.03 seconds
Started Oct 02 10:53:36 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 208448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327863971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.2327863971
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.1664063420
Short name T305
Test name
Test status
Simulation time 53375258 ps
CPU time 0.79 seconds
Started Oct 02 10:53:36 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664063420 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.1664063420
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.1731541506
Short name T303
Test name
Test status
Simulation time 47990061 ps
CPU time 0.7 seconds
Started Oct 02 10:53:36 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731541506 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.1731541506
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.2879498373
Short name T304
Test name
Test status
Simulation time 136645021 ps
CPU time 0.97 seconds
Started Oct 02 10:53:35 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 208564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879498373 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_wakeup_race.2879498373
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.2559931162
Short name T302
Test name
Test status
Simulation time 48548009 ps
CPU time 0.95 seconds
Started Oct 02 10:53:35 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559931162 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.2559931162
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.885966236
Short name T311
Test name
Test status
Simulation time 155228257 ps
CPU time 0.88 seconds
Started Oct 02 10:53:37 PM UTC 24
Finished Oct 02 10:53:39 PM UTC 24
Peak memory 220304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885966236 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.885966236
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.1360680970
Short name T307
Test name
Test status
Simulation time 273306355 ps
CPU time 1.01 seconds
Started Oct 02 10:53:36 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360680970 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_ctrl_config_regwen.1360680970
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2224388473
Short name T317
Test name
Test status
Simulation time 850414317 ps
CPU time 3.17 seconds
Started Oct 02 10:53:36 PM UTC 24
Finished Oct 02 10:53:40 PM UTC 24
Peak memory 211456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224388473 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2224388473
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3231991431
Short name T315
Test name
Test status
Simulation time 1014846816 ps
CPU time 2.7 seconds
Started Oct 02 10:53:36 PM UTC 24
Finished Oct 02 10:53:40 PM UTC 24
Peak memory 211636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231991431 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3231991431
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.55800858
Short name T308
Test name
Test status
Simulation time 55709445 ps
CPU time 0.98 seconds
Started Oct 02 10:53:36 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 209148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55800858 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_mubi.55800858
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.3304718977
Short name T296
Test name
Test status
Simulation time 56364092 ps
CPU time 0.64 seconds
Started Oct 02 10:53:34 PM UTC 24
Finished Oct 02 10:53:36 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304718977 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.3304718977
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all.2792800544
Short name T338
Test name
Test status
Simulation time 5548622813 ps
CPU time 3.96 seconds
Started Oct 02 10:53:37 PM UTC 24
Finished Oct 02 10:53:42 PM UTC 24
Peak memory 211728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792800544 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.2792800544
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all_with_rand_reset.1311303315
Short name T85
Test name
Test status
Simulation time 3808511189 ps
CPU time 5.66 seconds
Started Oct 02 10:53:37 PM UTC 24
Finished Oct 02 10:53:44 PM UTC 24
Peak memory 211312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1311303315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmg
r_stress_all_with_rand_reset.1311303315
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.3107297281
Short name T258
Test name
Test status
Simulation time 167772698 ps
CPU time 1.11 seconds
Started Oct 02 10:53:35 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107297281 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.3107297281
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.957963334
Short name T269
Test name
Test status
Simulation time 601742494 ps
CPU time 1.05 seconds
Started Oct 02 10:53:35 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 210180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957963334 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.957963334
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/12.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.74777427
Short name T314
Test name
Test status
Simulation time 27260382 ps
CPU time 0.79 seconds
Started Oct 02 10:53:37 PM UTC 24
Finished Oct 02 10:53:39 PM UTC 24
Peak memory 209008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74777427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=
pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.74777427
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_disable_rom_integrity_check.384989899
Short name T323
Test name
Test status
Simulation time 62367144 ps
CPU time 0.9 seconds
Started Oct 02 10:53:39 PM UTC 24
Finished Oct 02 10:53:41 PM UTC 24
Peak memory 208648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384989899 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disable_rom_integrity_check.384989899
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.1436829753
Short name T319
Test name
Test status
Simulation time 49453208 ps
CPU time 0.58 seconds
Started Oct 02 10:53:39 PM UTC 24
Finished Oct 02 10:53:41 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436829753 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_malfunc.1436829753
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.4014846118
Short name T324
Test name
Test status
Simulation time 489964179 ps
CPU time 0.93 seconds
Started Oct 02 10:53:39 PM UTC 24
Finished Oct 02 10:53:41 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014846118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.4014846118
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.2303445724
Short name T322
Test name
Test status
Simulation time 46119108 ps
CPU time 0.82 seconds
Started Oct 02 10:53:39 PM UTC 24
Finished Oct 02 10:53:41 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303445724 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.2303445724
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_global_esc.2273657367
Short name T320
Test name
Test status
Simulation time 56050898 ps
CPU time 0.68 seconds
Started Oct 02 10:53:39 PM UTC 24
Finished Oct 02 10:53:41 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273657367 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.2273657367
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.3790530721
Short name T309
Test name
Test status
Simulation time 51779567 ps
CPU time 0.68 seconds
Started Oct 02 10:53:37 PM UTC 24
Finished Oct 02 10:53:39 PM UTC 24
Peak memory 208192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790530721 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_wakeup_race.3790530721
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.3781299703
Short name T306
Test name
Test status
Simulation time 28000328 ps
CPU time 0.77 seconds
Started Oct 02 10:53:37 PM UTC 24
Finished Oct 02 10:53:39 PM UTC 24
Peak memory 208380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781299703 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.3781299703
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset_invalid.967655945
Short name T326
Test name
Test status
Simulation time 158032171 ps
CPU time 0.85 seconds
Started Oct 02 10:53:39 PM UTC 24
Finished Oct 02 10:53:41 PM UTC 24
Peak memory 220308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967655945 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.967655945
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.699969296
Short name T327
Test name
Test status
Simulation time 133324190 ps
CPU time 1.19 seconds
Started Oct 02 10:53:39 PM UTC 24
Finished Oct 02 10:53:41 PM UTC 24
Peak memory 210076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699969296 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_ctrl_config_regwen.699969296
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3409451891
Short name T321
Test name
Test status
Simulation time 986261400 ps
CPU time 2.51 seconds
Started Oct 02 10:53:38 PM UTC 24
Finished Oct 02 10:53:41 PM UTC 24
Peak memory 211512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409451891 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3409451891
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1479177086
Short name T333
Test name
Test status
Simulation time 921761086 ps
CPU time 2.9 seconds
Started Oct 02 10:53:38 PM UTC 24
Finished Oct 02 10:53:42 PM UTC 24
Peak memory 211572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479177086 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1479177086
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2286881279
Short name T325
Test name
Test status
Simulation time 87445580 ps
CPU time 1.08 seconds
Started Oct 02 10:53:39 PM UTC 24
Finished Oct 02 10:53:41 PM UTC 24
Peak memory 209148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286881279 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2286881279
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.3513339105
Short name T312
Test name
Test status
Simulation time 29279508 ps
CPU time 0.94 seconds
Started Oct 02 10:53:37 PM UTC 24
Finished Oct 02 10:53:39 PM UTC 24
Peak memory 208740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513339105 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.3513339105
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all.1242904265
Short name T336
Test name
Test status
Simulation time 578531901 ps
CPU time 1.44 seconds
Started Oct 02 10:53:39 PM UTC 24
Finished Oct 02 10:53:42 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242904265 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.1242904265
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.3407021949
Short name T86
Test name
Test status
Simulation time 4678502530 ps
CPU time 11.9 seconds
Started Oct 02 10:53:39 PM UTC 24
Finished Oct 02 10:53:53 PM UTC 24
Peak memory 211628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3407021949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmg
r_stress_all_with_rand_reset.3407021949
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.2166154114
Short name T316
Test name
Test status
Simulation time 241569602 ps
CPU time 1.24 seconds
Started Oct 02 10:53:37 PM UTC 24
Finished Oct 02 10:53:40 PM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166154114 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.2166154114
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.3709142474
Short name T313
Test name
Test status
Simulation time 144267633 ps
CPU time 0.78 seconds
Started Oct 02 10:53:37 PM UTC 24
Finished Oct 02 10:53:39 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709142474 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.3709142474
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/13.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.1207969253
Short name T328
Test name
Test status
Simulation time 157176753 ps
CPU time 0.6 seconds
Started Oct 02 10:53:40 PM UTC 24
Finished Oct 02 10:53:41 PM UTC 24
Peak memory 208804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207969253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.1207969253
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.1520997316
Short name T345
Test name
Test status
Simulation time 58930635 ps
CPU time 0.79 seconds
Started Oct 02 10:53:41 PM UTC 24
Finished Oct 02 10:53:43 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520997316 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_disable_rom_integrity_check.1520997316
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.791873072
Short name T339
Test name
Test status
Simulation time 30071734 ps
CPU time 0.66 seconds
Started Oct 02 10:53:41 PM UTC 24
Finished Oct 02 10:53:43 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791873072 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_malfunc.791873072
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_escalation_timeout.970813327
Short name T346
Test name
Test status
Simulation time 109358451 ps
CPU time 0.91 seconds
Started Oct 02 10:53:41 PM UTC 24
Finished Oct 02 10:53:43 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970813327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.970813327
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.3341868413
Short name T340
Test name
Test status
Simulation time 50853356 ps
CPU time 0.64 seconds
Started Oct 02 10:53:41 PM UTC 24
Finished Oct 02 10:53:43 PM UTC 24
Peak memory 208732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341868413 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.3341868413
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_global_esc.4178363431
Short name T341
Test name
Test status
Simulation time 85646147 ps
CPU time 0.71 seconds
Started Oct 02 10:53:41 PM UTC 24
Finished Oct 02 10:53:43 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178363431 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.4178363431
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_wakeup_race.3937636378
Short name T332
Test name
Test status
Simulation time 65525057 ps
CPU time 0.73 seconds
Started Oct 02 10:53:40 PM UTC 24
Finished Oct 02 10:53:42 PM UTC 24
Peak memory 208988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937636378 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_wakeup_race.3937636378
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset.1676925631
Short name T329
Test name
Test status
Simulation time 50402029 ps
CPU time 0.82 seconds
Started Oct 02 10:53:40 PM UTC 24
Finished Oct 02 10:53:42 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676925631 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.1676925631
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.2174852661
Short name T347
Test name
Test status
Simulation time 114384461 ps
CPU time 0.98 seconds
Started Oct 02 10:53:41 PM UTC 24
Finished Oct 02 10:53:43 PM UTC 24
Peak memory 220664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174852661 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.2174852661
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.3108903800
Short name T344
Test name
Test status
Simulation time 228430764 ps
CPU time 0.82 seconds
Started Oct 02 10:53:41 PM UTC 24
Finished Oct 02 10:53:43 PM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108903800 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_ctrl_config_regwen.3108903800
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1098345860
Short name T348
Test name
Test status
Simulation time 952926441 ps
CPU time 2.94 seconds
Started Oct 02 10:53:40 PM UTC 24
Finished Oct 02 10:53:44 PM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098345860 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1098345860
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3163582002
Short name T352
Test name
Test status
Simulation time 865216383 ps
CPU time 2.82 seconds
Started Oct 02 10:53:41 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 211440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163582002 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3163582002
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3821903155
Short name T343
Test name
Test status
Simulation time 98505544 ps
CPU time 0.93 seconds
Started Oct 02 10:53:41 PM UTC 24
Finished Oct 02 10:53:43 PM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821903155 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3821903155
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_smoke.1945830843
Short name T331
Test name
Test status
Simulation time 29755308 ps
CPU time 0.79 seconds
Started Oct 02 10:53:39 PM UTC 24
Finished Oct 02 10:53:42 PM UTC 24
Peak memory 208320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945830843 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.1945830843
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all.2491295573
Short name T359
Test name
Test status
Simulation time 627392330 ps
CPU time 2.5 seconds
Started Oct 02 10:53:41 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 211476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491295573 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.2491295573
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all_with_rand_reset.1198656267
Short name T72
Test name
Test status
Simulation time 2782908599 ps
CPU time 11.09 seconds
Started Oct 02 10:53:41 PM UTC 24
Finished Oct 02 10:53:53 PM UTC 24
Peak memory 211828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1198656267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmg
r_stress_all_with_rand_reset.1198656267
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup.2239331578
Short name T335
Test name
Test status
Simulation time 246219593 ps
CPU time 1.07 seconds
Started Oct 02 10:53:40 PM UTC 24
Finished Oct 02 10:53:42 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239331578 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.2239331578
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.3286343709
Short name T334
Test name
Test status
Simulation time 67378206 ps
CPU time 0.91 seconds
Started Oct 02 10:53:40 PM UTC 24
Finished Oct 02 10:53:42 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286343709 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.3286343709
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/14.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_aborted_low_power.4070696137
Short name T353
Test name
Test status
Simulation time 107547706 ps
CPU time 0.94 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 210328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070696137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.4070696137
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.4216049896
Short name T362
Test name
Test status
Simulation time 117427629 ps
CPU time 0.69 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 208376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216049896 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disable_rom_integrity_check.4216049896
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.3953855095
Short name T354
Test name
Test status
Simulation time 30353245 ps
CPU time 0.7 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 208720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953855095 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_malfunc.3953855095
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.3336643743
Short name T360
Test name
Test status
Simulation time 382425566 ps
CPU time 0.77 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336643743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.3336643743
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.3091005402
Short name T363
Test name
Test status
Simulation time 85867078 ps
CPU time 0.76 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 208728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091005402 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.3091005402
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_global_esc.517464417
Short name T356
Test name
Test status
Simulation time 36742158 ps
CPU time 0.64 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517464417 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.517464417
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_wakeup_race.181043380
Short name T351
Test name
Test status
Simulation time 308963433 ps
CPU time 0.88 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 209796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181043380 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_wakeup_race.181043380
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset.3988842727
Short name T349
Test name
Test status
Simulation time 49226474 ps
CPU time 0.67 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:44 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988842727 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.3988842727
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset_invalid.1036855939
Short name T368
Test name
Test status
Simulation time 116694839 ps
CPU time 1.04 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 220544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036855939 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.1036855939
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.356030227
Short name T364
Test name
Test status
Simulation time 362850854 ps
CPU time 1.01 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356030227 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_ctrl_config_regwen.356030227
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2025266731
Short name T371
Test name
Test status
Simulation time 975053205 ps
CPU time 2.55 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:47 PM UTC 24
Peak memory 211444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025266731 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2025266731
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1529581031
Short name T370
Test name
Test status
Simulation time 1337006314 ps
CPU time 2.13 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:46 PM UTC 24
Peak memory 211640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529581031 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1529581031
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.242028784
Short name T357
Test name
Test status
Simulation time 98367656 ps
CPU time 0.84 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 209688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242028784 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_mubi.242028784
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.3995687759
Short name T350
Test name
Test status
Simulation time 41446764 ps
CPU time 0.72 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995687759 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.3995687759
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.2934566020
Short name T366
Test name
Test status
Simulation time 987358537 ps
CPU time 2.65 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:47 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934566020 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.2934566020
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.1855498653
Short name T138
Test name
Test status
Simulation time 2570888553 ps
CPU time 3.61 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:48 PM UTC 24
Peak memory 211748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1855498653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmg
r_stress_all_with_rand_reset.1855498653
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup.1052678073
Short name T361
Test name
Test status
Simulation time 254135240 ps
CPU time 1.08 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 209792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052678073 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.1052678073
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup_reset.1868242860
Short name T355
Test name
Test status
Simulation time 147123585 ps
CPU time 0.96 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 210648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868242860 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.1868242860
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/15.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_aborted_low_power.2894187646
Short name T372
Test name
Test status
Simulation time 32232678 ps
CPU time 0.7 seconds
Started Oct 02 10:53:45 PM UTC 24
Finished Oct 02 10:53:47 PM UTC 24
Peak memory 208744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894187646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.2894187646
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.3639088067
Short name T178
Test name
Test status
Simulation time 72450438 ps
CPU time 0.68 seconds
Started Oct 02 10:53:45 PM UTC 24
Finished Oct 02 10:53:47 PM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639088067 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disable_rom_integrity_check.3639088067
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.4228747610
Short name T373
Test name
Test status
Simulation time 33167526 ps
CPU time 0.64 seconds
Started Oct 02 10:53:45 PM UTC 24
Finished Oct 02 10:53:47 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228747610 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_malfunc.4228747610
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_escalation_timeout.4013325981
Short name T342
Test name
Test status
Simulation time 112932922 ps
CPU time 1.04 seconds
Started Oct 02 10:53:45 PM UTC 24
Finished Oct 02 10:53:47 PM UTC 24
Peak memory 208440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013325981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.4013325981
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_glitch.652156080
Short name T310
Test name
Test status
Simulation time 62634661 ps
CPU time 0.67 seconds
Started Oct 02 10:53:45 PM UTC 24
Finished Oct 02 10:53:47 PM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652156080 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.652156080
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_global_esc.2874340761
Short name T376
Test name
Test status
Simulation time 72600440 ps
CPU time 0.62 seconds
Started Oct 02 10:53:45 PM UTC 24
Finished Oct 02 10:53:47 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874340761 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.2874340761
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_wakeup_race.819045173
Short name T369
Test name
Test status
Simulation time 423846059 ps
CPU time 0.86 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:46 PM UTC 24
Peak memory 209796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819045173 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_wakeup_race.819045173
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.1648775141
Short name T367
Test name
Test status
Simulation time 69164436 ps
CPU time 0.79 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648775141 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.1648775141
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset_invalid.2254030472
Short name T384
Test name
Test status
Simulation time 155568794 ps
CPU time 1.04 seconds
Started Oct 02 10:53:46 PM UTC 24
Finished Oct 02 10:53:49 PM UTC 24
Peak memory 220364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254030472 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.2254030472
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.1493252521
Short name T374
Test name
Test status
Simulation time 231580668 ps
CPU time 0.79 seconds
Started Oct 02 10:53:45 PM UTC 24
Finished Oct 02 10:53:47 PM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493252521 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_ctrl_config_regwen.1493252521
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.576825080
Short name T380
Test name
Test status
Simulation time 950158882 ps
CPU time 2.5 seconds
Started Oct 02 10:53:45 PM UTC 24
Finished Oct 02 10:53:48 PM UTC 24
Peak memory 211208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576825080 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.576825080
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.513323635
Short name T379
Test name
Test status
Simulation time 991524991 ps
CPU time 2.43 seconds
Started Oct 02 10:53:45 PM UTC 24
Finished Oct 02 10:53:48 PM UTC 24
Peak memory 211388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513323635 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.513323635
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2996054975
Short name T378
Test name
Test status
Simulation time 68742966 ps
CPU time 1.11 seconds
Started Oct 02 10:53:45 PM UTC 24
Finished Oct 02 10:53:47 PM UTC 24
Peak memory 209208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996054975 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2996054975
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.3055334601
Short name T365
Test name
Test status
Simulation time 56606084 ps
CPU time 0.65 seconds
Started Oct 02 10:53:43 PM UTC 24
Finished Oct 02 10:53:45 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055334601 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.3055334601
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all.910712058
Short name T404
Test name
Test status
Simulation time 1863180975 ps
CPU time 2.87 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:50 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910712058 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.910712058
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all_with_rand_reset.815199579
Short name T416
Test name
Test status
Simulation time 994327661 ps
CPU time 4.58 seconds
Started Oct 02 10:53:46 PM UTC 24
Finished Oct 02 10:53:52 PM UTC 24
Peak memory 211568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=815199579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr
_stress_all_with_rand_reset.815199579
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.3235914194
Short name T375
Test name
Test status
Simulation time 230586726 ps
CPU time 0.83 seconds
Started Oct 02 10:53:45 PM UTC 24
Finished Oct 02 10:53:47 PM UTC 24
Peak memory 209036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235914194 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.3235914194
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup_reset.2886386805
Short name T330
Test name
Test status
Simulation time 208221333 ps
CPU time 1.17 seconds
Started Oct 02 10:53:45 PM UTC 24
Finished Oct 02 10:53:47 PM UTC 24
Peak memory 210648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886386805 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.2886386805
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/16.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_aborted_low_power.1968119834
Short name T381
Test name
Test status
Simulation time 118140409 ps
CPU time 0.81 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:48 PM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968119834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.1968119834
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.1962200910
Short name T392
Test name
Test status
Simulation time 60910985 ps
CPU time 0.67 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:49 PM UTC 24
Peak memory 208560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962200910 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_disable_rom_integrity_check.1962200910
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.268388856
Short name T387
Test name
Test status
Simulation time 39840492 ps
CPU time 0.64 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:49 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268388856 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_malfunc.268388856
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_escalation_timeout.3312328206
Short name T393
Test name
Test status
Simulation time 440806522 ps
CPU time 0.81 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:49 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312328206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.3312328206
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_glitch.2534623813
Short name T390
Test name
Test status
Simulation time 55524996 ps
CPU time 0.61 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:49 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534623813 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.2534623813
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_global_esc.3794532282
Short name T388
Test name
Test status
Simulation time 47396584 ps
CPU time 0.66 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:49 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794532282 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.3794532282
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_invalid.759195637
Short name T44
Test name
Test status
Simulation time 58185384 ps
CPU time 0.76 seconds
Started Oct 02 10:53:48 PM UTC 24
Finished Oct 02 10:53:50 PM UTC 24
Peak memory 210164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759195637 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_invalid.759195637
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_wakeup_race.3938075050
Short name T391
Test name
Test status
Simulation time 153886184 ps
CPU time 1 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:49 PM UTC 24
Peak memory 209600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938075050 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_wakeup_race.3938075050
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset.1864165126
Short name T358
Test name
Test status
Simulation time 67813653 ps
CPU time 0.92 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:48 PM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864165126 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.1864165126
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset_invalid.2803599065
Short name T395
Test name
Test status
Simulation time 125411256 ps
CPU time 0.77 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:49 PM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803599065 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2803599065
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.879469798
Short name T396
Test name
Test status
Simulation time 316215970 ps
CPU time 1.23 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:49 PM UTC 24
Peak memory 210328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879469798 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_ctrl_config_regwen.879469798
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.245869010
Short name T397
Test name
Test status
Simulation time 1151700787 ps
CPU time 1.87 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:50 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245869010 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.245869010
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1078585780
Short name T401
Test name
Test status
Simulation time 908375678 ps
CPU time 2.37 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:50 PM UTC 24
Peak memory 211576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078585780 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1078585780
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1367835684
Short name T394
Test name
Test status
Simulation time 66097294 ps
CPU time 0.98 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:49 PM UTC 24
Peak memory 209832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367835684 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1367835684
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.1920555531
Short name T377
Test name
Test status
Simulation time 48968133 ps
CPU time 0.67 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:48 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920555531 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.1920555531
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all.625408178
Short name T413
Test name
Test status
Simulation time 736363727 ps
CPU time 1.81 seconds
Started Oct 02 10:53:48 PM UTC 24
Finished Oct 02 10:53:51 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625408178 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.625408178
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup.3137550603
Short name T389
Test name
Test status
Simulation time 199491442 ps
CPU time 1.01 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:49 PM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137550603 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.3137550603
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup_reset.1273546
Short name T385
Test name
Test status
Simulation time 156554890 ps
CPU time 0.77 seconds
Started Oct 02 10:53:47 PM UTC 24
Finished Oct 02 10:53:49 PM UTC 24
Peak memory 208560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273546 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.1273546
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/17.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_aborted_low_power.3832259029
Short name T408
Test name
Test status
Simulation time 66331366 ps
CPU time 0.89 seconds
Started Oct 02 10:53:49 PM UTC 24
Finished Oct 02 10:53:51 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832259029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.3832259029
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_disable_rom_integrity_check.2598368549
Short name T415
Test name
Test status
Simulation time 76304693 ps
CPU time 0.73 seconds
Started Oct 02 10:53:50 PM UTC 24
Finished Oct 02 10:53:52 PM UTC 24
Peak memory 208620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598368549 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disable_rom_integrity_check.2598368549
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.4007086666
Short name T409
Test name
Test status
Simulation time 29301703 ps
CPU time 0.81 seconds
Started Oct 02 10:53:49 PM UTC 24
Finished Oct 02 10:53:51 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007086666 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_malfunc.4007086666
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_escalation_timeout.2237062492
Short name T412
Test name
Test status
Simulation time 112869497 ps
CPU time 0.85 seconds
Started Oct 02 10:53:49 PM UTC 24
Finished Oct 02 10:53:51 PM UTC 24
Peak memory 208440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237062492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.2237062492
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_glitch.4044730464
Short name T414
Test name
Test status
Simulation time 64564170 ps
CPU time 0.63 seconds
Started Oct 02 10:53:50 PM UTC 24
Finished Oct 02 10:53:52 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044730464 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.4044730464
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_global_esc.4211402605
Short name T410
Test name
Test status
Simulation time 37541762 ps
CPU time 0.83 seconds
Started Oct 02 10:53:49 PM UTC 24
Finished Oct 02 10:53:51 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211402605 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.4211402605
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_wakeup_race.2852850422
Short name T406
Test name
Test status
Simulation time 331061242 ps
CPU time 0.93 seconds
Started Oct 02 10:53:49 PM UTC 24
Finished Oct 02 10:53:51 PM UTC 24
Peak memory 209600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852850422 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_wakeup_race.2852850422
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset.2122079984
Short name T402
Test name
Test status
Simulation time 31472062 ps
CPU time 0.73 seconds
Started Oct 02 10:53:49 PM UTC 24
Finished Oct 02 10:53:50 PM UTC 24
Peak memory 208740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122079984 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.2122079984
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset_invalid.3256427334
Short name T418
Test name
Test status
Simulation time 124708684 ps
CPU time 0.8 seconds
Started Oct 02 10:53:50 PM UTC 24
Finished Oct 02 10:53:52 PM UTC 24
Peak memory 220724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256427334 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.3256427334
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.3436831557
Short name T405
Test name
Test status
Simulation time 100060757 ps
CPU time 0.64 seconds
Started Oct 02 10:53:49 PM UTC 24
Finished Oct 02 10:53:50 PM UTC 24
Peak memory 208800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436831557 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_ctrl_config_regwen.3436831557
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.343056468
Short name T420
Test name
Test status
Simulation time 814559369 ps
CPU time 3.01 seconds
Started Oct 02 10:53:49 PM UTC 24
Finished Oct 02 10:53:53 PM UTC 24
Peak memory 211628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343056468 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.343056468
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1281911631
Short name T419
Test name
Test status
Simulation time 831011541 ps
CPU time 2.88 seconds
Started Oct 02 10:53:49 PM UTC 24
Finished Oct 02 10:53:53 PM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281911631 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1281911631
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1889289237
Short name T411
Test name
Test status
Simulation time 65848027 ps
CPU time 1 seconds
Started Oct 02 10:53:49 PM UTC 24
Finished Oct 02 10:53:51 PM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889289237 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1889289237
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_smoke.3905403851
Short name T400
Test name
Test status
Simulation time 54635805 ps
CPU time 0.72 seconds
Started Oct 02 10:53:49 PM UTC 24
Finished Oct 02 10:53:50 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905403851 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.3905403851
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all_with_rand_reset.3723219858
Short name T139
Test name
Test status
Simulation time 8226260467 ps
CPU time 16.55 seconds
Started Oct 02 10:53:50 PM UTC 24
Finished Oct 02 10:54:08 PM UTC 24
Peak memory 211684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3723219858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmg
r_stress_all_with_rand_reset.3723219858
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup.2870050879
Short name T403
Test name
Test status
Simulation time 75244396 ps
CPU time 0.67 seconds
Started Oct 02 10:53:49 PM UTC 24
Finished Oct 02 10:53:50 PM UTC 24
Peak memory 209036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870050879 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.2870050879
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup_reset.1613849176
Short name T407
Test name
Test status
Simulation time 194101429 ps
CPU time 0.91 seconds
Started Oct 02 10:53:49 PM UTC 24
Finished Oct 02 10:53:51 PM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613849176 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.1613849176
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/18.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_aborted_low_power.3940310662
Short name T422
Test name
Test status
Simulation time 36864274 ps
CPU time 0.7 seconds
Started Oct 02 10:53:51 PM UTC 24
Finished Oct 02 10:53:59 PM UTC 24
Peak memory 209740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940310662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.3940310662
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_disable_rom_integrity_check.3749577998
Short name T429
Test name
Test status
Simulation time 66760464 ps
CPU time 0.79 seconds
Started Oct 02 10:53:51 PM UTC 24
Finished Oct 02 10:54:03 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749577998 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disable_rom_integrity_check.3749577998
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.4111618529
Short name T421
Test name
Test status
Simulation time 38768615 ps
CPU time 0.51 seconds
Started Oct 02 10:53:51 PM UTC 24
Finished Oct 02 10:53:59 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111618529 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_malfunc.4111618529
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_escalation_timeout.311848885
Short name T435
Test name
Test status
Simulation time 1590190690 ps
CPU time 0.76 seconds
Started Oct 02 10:53:51 PM UTC 24
Finished Oct 02 10:54:10 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311848885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.311848885
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_glitch.4210587460
Short name T428
Test name
Test status
Simulation time 112191982 ps
CPU time 0.56 seconds
Started Oct 02 10:53:51 PM UTC 24
Finished Oct 02 10:54:03 PM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210587460 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.4210587460
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_global_esc.2139088305
Short name T434
Test name
Test status
Simulation time 67538918 ps
CPU time 0.55 seconds
Started Oct 02 10:53:51 PM UTC 24
Finished Oct 02 10:54:10 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139088305 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.2139088305
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_wakeup_race.1473964177
Short name T432
Test name
Test status
Simulation time 85161324 ps
CPU time 0.78 seconds
Started Oct 02 10:53:51 PM UTC 24
Finished Oct 02 10:54:09 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473964177 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_wakeup_race.1473964177
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.2332295605
Short name T433
Test name
Test status
Simulation time 163314062 ps
CPU time 0.64 seconds
Started Oct 02 10:53:51 PM UTC 24
Finished Oct 02 10:54:10 PM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332295605 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_ctrl_config_regwen.2332295605
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4137215888
Short name T426
Test name
Test status
Simulation time 1938962243 ps
CPU time 1.86 seconds
Started Oct 02 10:53:51 PM UTC 24
Finished Oct 02 10:54:01 PM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137215888 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4137215888
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1515756230
Short name T427
Test name
Test status
Simulation time 870213070 ps
CPU time 2.89 seconds
Started Oct 02 10:53:51 PM UTC 24
Finished Oct 02 10:54:02 PM UTC 24
Peak memory 211380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515756230 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1515756230
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.2952366594
Short name T423
Test name
Test status
Simulation time 51590940 ps
CPU time 0.88 seconds
Started Oct 02 10:53:51 PM UTC 24
Finished Oct 02 10:54:00 PM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952366594 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_mubi.2952366594
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup.1436263215
Short name T424
Test name
Test status
Simulation time 293095404 ps
CPU time 1.19 seconds
Started Oct 02 10:53:51 PM UTC 24
Finished Oct 02 10:54:00 PM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436263215 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.1436263215
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup_reset.3169543433
Short name T425
Test name
Test status
Simulation time 382685991 ps
CPU time 1.21 seconds
Started Oct 02 10:53:51 PM UTC 24
Finished Oct 02 10:54:00 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169543433 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.3169543433
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/19.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.853767046
Short name T41
Test name
Test status
Simulation time 102329131 ps
CPU time 1.1 seconds
Started Oct 02 10:53:07 PM UTC 24
Finished Oct 02 10:53:09 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853767046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.853767046
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.2876576359
Short name T149
Test name
Test status
Simulation time 39169689 ps
CPU time 0.77 seconds
Started Oct 02 10:53:08 PM UTC 24
Finished Oct 02 10:53:10 PM UTC 24
Peak memory 208864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876576359 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_malfunc.2876576359
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.2025907650
Short name T142
Test name
Test status
Simulation time 477931897 ps
CPU time 0.88 seconds
Started Oct 02 10:53:08 PM UTC 24
Finished Oct 02 10:53:10 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025907650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.2025907650
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.298468184
Short name T19
Test name
Test status
Simulation time 48296381 ps
CPU time 0.8 seconds
Started Oct 02 10:53:08 PM UTC 24
Finished Oct 02 10:53:10 PM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298468184 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.298468184
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.294641214
Short name T183
Test name
Test status
Simulation time 21373734 ps
CPU time 0.87 seconds
Started Oct 02 10:53:08 PM UTC 24
Finished Oct 02 10:53:10 PM UTC 24
Peak memory 208860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294641214 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.294641214
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.3433535039
Short name T82
Test name
Test status
Simulation time 184451779 ps
CPU time 0.86 seconds
Started Oct 02 10:53:07 PM UTC 24
Finished Oct 02 10:53:08 PM UTC 24
Peak memory 208800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433535039 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wakeup_race.3433535039
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.1200055646
Short name T132
Test name
Test status
Simulation time 76524037 ps
CPU time 1.12 seconds
Started Oct 02 10:53:07 PM UTC 24
Finished Oct 02 10:53:09 PM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200055646 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.1200055646
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.2236293171
Short name T42
Test name
Test status
Simulation time 96559144 ps
CPU time 1.26 seconds
Started Oct 02 10:53:08 PM UTC 24
Finished Oct 02 10:53:11 PM UTC 24
Peak memory 220372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236293171 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.2236293171
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.2689193532
Short name T22
Test name
Test status
Simulation time 769167731 ps
CPU time 1.89 seconds
Started Oct 02 10:53:08 PM UTC 24
Finished Oct 02 10:53:11 PM UTC 24
Peak memory 237576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689193532 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.2689193532
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.360642988
Short name T60
Test name
Test status
Simulation time 156346341 ps
CPU time 1.16 seconds
Started Oct 02 10:53:08 PM UTC 24
Finished Oct 02 10:53:10 PM UTC 24
Peak memory 209008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360642988 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_ctrl_config_regwen.360642988
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1440735592
Short name T156
Test name
Test status
Simulation time 765809167 ps
CPU time 3.56 seconds
Started Oct 02 10:53:08 PM UTC 24
Finished Oct 02 10:53:13 PM UTC 24
Peak memory 211436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440735592 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.1440735592
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1171651670
Short name T79
Test name
Test status
Simulation time 891201862 ps
CPU time 3.58 seconds
Started Oct 02 10:53:08 PM UTC 24
Finished Oct 02 10:53:13 PM UTC 24
Peak memory 211436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171651670 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.1171651670
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1074137129
Short name T184
Test name
Test status
Simulation time 153344014 ps
CPU time 1.1 seconds
Started Oct 02 10:53:08 PM UTC 24
Finished Oct 02 10:53:10 PM UTC 24
Peak memory 209152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074137129 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1074137129
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.1100693451
Short name T131
Test name
Test status
Simulation time 155925553 ps
CPU time 0.74 seconds
Started Oct 02 10:53:07 PM UTC 24
Finished Oct 02 10:53:08 PM UTC 24
Peak memory 208712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100693451 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.1100693451
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.451928324
Short name T105
Test name
Test status
Simulation time 401904612 ps
CPU time 2.34 seconds
Started Oct 02 10:53:10 PM UTC 24
Finished Oct 02 10:53:13 PM UTC 24
Peak memory 211384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451928324 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.451928324
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.2561055497
Short name T24
Test name
Test status
Simulation time 4062458959 ps
CPU time 9.12 seconds
Started Oct 02 10:53:09 PM UTC 24
Finished Oct 02 10:53:19 PM UTC 24
Peak memory 211696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2561055497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr
_stress_all_with_rand_reset.2561055497
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.3747196747
Short name T182
Test name
Test status
Simulation time 34781092 ps
CPU time 0.88 seconds
Started Oct 02 10:53:07 PM UTC 24
Finished Oct 02 10:53:08 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747196747 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.3747196747
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.4140517296
Short name T155
Test name
Test status
Simulation time 363669298 ps
CPU time 1.58 seconds
Started Oct 02 10:53:07 PM UTC 24
Finished Oct 02 10:53:09 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140517296 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.4140517296
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/2.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_aborted_low_power.2763826414
Short name T430
Test name
Test status
Simulation time 40156912 ps
CPU time 0.78 seconds
Started Oct 02 10:53:53 PM UTC 24
Finished Oct 02 10:54:04 PM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763826414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.2763826414
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/20.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.283102717
Short name T472
Test name
Test status
Simulation time 56918934 ps
CPU time 0.75 seconds
Started Oct 02 10:53:54 PM UTC 24
Finished Oct 02 10:54:51 PM UTC 24
Peak memory 208656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283102717 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disable_rom_integrity_check.283102717
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.3445713913
Short name T439
Test name
Test status
Simulation time 39871644 ps
CPU time 0.55 seconds
Started Oct 02 10:53:53 PM UTC 24
Finished Oct 02 10:54:11 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445713913 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst_malfunc.3445713913
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_escalation_timeout.1465906392
Short name T471
Test name
Test status
Simulation time 380638124 ps
CPU time 0.79 seconds
Started Oct 02 10:53:54 PM UTC 24
Finished Oct 02 10:54:51 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465906392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.1465906392
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/20.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_glitch.906550070
Short name T469
Test name
Test status
Simulation time 69015978 ps
CPU time 0.56 seconds
Started Oct 02 10:53:54 PM UTC 24
Finished Oct 02 10:54:50 PM UTC 24
Peak memory 208744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906550070 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.906550070
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/20.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_global_esc.725640560
Short name T468
Test name
Test status
Simulation time 42795798 ps
CPU time 0.62 seconds
Started Oct 02 10:53:54 PM UTC 24
Finished Oct 02 10:54:50 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725640560 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.725640560
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/20.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset_invalid.1210945737
Short name T487
Test name
Test status
Simulation time 111902727 ps
CPU time 1.01 seconds
Started Oct 02 10:53:54 PM UTC 24
Finished Oct 02 10:55:01 PM UTC 24
Peak memory 220336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210945737 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.1210945737
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/20.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.3093212615
Short name T441
Test name
Test status
Simulation time 280906117 ps
CPU time 1.33 seconds
Started Oct 02 10:53:53 PM UTC 24
Finished Oct 02 10:54:12 PM UTC 24
Peak memory 209736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093212615 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_ctrl_config_regwen.3093212615
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all_with_rand_reset.521882769
Short name T499
Test name
Test status
Simulation time 1591376499 ps
CPU time 6.07 seconds
Started Oct 02 10:53:54 PM UTC 24
Finished Oct 02 10:55:06 PM UTC 24
Peak memory 211624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=521882769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr
_stress_all_with_rand_reset.521882769
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/20.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.2023069038
Short name T438
Test name
Test status
Simulation time 61093025 ps
CPU time 0.77 seconds
Started Oct 02 10:54:09 PM UTC 24
Finished Oct 02 10:54:11 PM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023069038 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disable_rom_integrity_check.2023069038
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_escalation_timeout.1890331156
Short name T510
Test name
Test status
Simulation time 111996563 ps
CPU time 0.79 seconds
Started Oct 02 10:54:05 PM UTC 24
Finished Oct 02 10:55:07 PM UTC 24
Peak memory 208960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890331156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.1890331156
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/21.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_glitch.2536429732
Short name T437
Test name
Test status
Simulation time 121661198 ps
CPU time 0.53 seconds
Started Oct 02 10:54:09 PM UTC 24
Finished Oct 02 10:54:11 PM UTC 24
Peak memory 208728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536429732 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.2536429732
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/21.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_global_esc.1308516870
Short name T507
Test name
Test status
Simulation time 36172925 ps
CPU time 0.6 seconds
Started Oct 02 10:54:05 PM UTC 24
Finished Oct 02 10:55:07 PM UTC 24
Peak memory 208988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308516870 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.1308516870
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/21.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset.817143205
Short name T436
Test name
Test status
Simulation time 58893757 ps
CPU time 0.75 seconds
Started Oct 02 10:53:55 PM UTC 24
Finished Oct 02 10:54:10 PM UTC 24
Peak memory 208640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817143205 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.817143205
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/21.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset_invalid.784341857
Short name T443
Test name
Test status
Simulation time 212225732 ps
CPU time 0.69 seconds
Started Oct 02 10:54:10 PM UTC 24
Finished Oct 02 10:54:15 PM UTC 24
Peak memory 220544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784341857 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.784341857
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/21.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4110241667
Short name T440
Test name
Test status
Simulation time 984522298 ps
CPU time 1.8 seconds
Started Oct 02 10:54:02 PM UTC 24
Finished Oct 02 10:54:12 PM UTC 24
Peak memory 210924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110241667 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.4110241667
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3186393064
Short name T431
Test name
Test status
Simulation time 63802570 ps
CPU time 0.71 seconds
Started Oct 02 10:54:03 PM UTC 24
Finished Oct 02 10:54:04 PM UTC 24
Peak memory 209148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186393064 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3186393064
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_smoke.2984009809
Short name T501
Test name
Test status
Simulation time 30808068 ps
CPU time 0.63 seconds
Started Oct 02 10:53:54 PM UTC 24
Finished Oct 02 10:55:06 PM UTC 24
Peak memory 208560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984009809 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.2984009809
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/21.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all.1721097854
Short name T444
Test name
Test status
Simulation time 2035921143 ps
CPU time 5.84 seconds
Started Oct 02 10:54:10 PM UTC 24
Finished Oct 02 10:54:20 PM UTC 24
Peak memory 211532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721097854 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.1721097854
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/21.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all_with_rand_reset.1196939687
Short name T87
Test name
Test status
Simulation time 3233959167 ps
CPU time 11.64 seconds
Started Oct 02 10:54:10 PM UTC 24
Finished Oct 02 10:54:26 PM UTC 24
Peak memory 211752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1196939687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmg
r_stress_all_with_rand_reset.1196939687
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/21.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_disable_rom_integrity_check.3066693871
Short name T447
Test name
Test status
Simulation time 63077891 ps
CPU time 0.59 seconds
Started Oct 02 10:54:22 PM UTC 24
Finished Oct 02 10:54:31 PM UTC 24
Peak memory 208620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066693871 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_disable_rom_integrity_check.3066693871
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_glitch.3042899430
Short name T417
Test name
Test status
Simulation time 46400219 ps
CPU time 0.59 seconds
Started Oct 02 10:54:22 PM UTC 24
Finished Oct 02 10:54:31 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042899430 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.3042899430
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/22.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_wakeup_race.626216213
Short name T382
Test name
Test status
Simulation time 34528377 ps
CPU time 0.61 seconds
Started Oct 02 10:54:11 PM UTC 24
Finished Oct 02 10:54:20 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626216213 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_wakeup_race.626216213
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset.2869657373
Short name T399
Test name
Test status
Simulation time 40442594 ps
CPU time 0.68 seconds
Started Oct 02 10:54:11 PM UTC 24
Finished Oct 02 10:54:20 PM UTC 24
Peak memory 208380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869657373 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.2869657373
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/22.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset_invalid.1655584812
Short name T442
Test name
Test status
Simulation time 108607680 ps
CPU time 0.85 seconds
Started Oct 02 10:54:22 PM UTC 24
Finished Oct 02 10:54:31 PM UTC 24
Peak memory 220784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655584812 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.1655584812
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/22.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1852597361
Short name T446
Test name
Test status
Simulation time 1346747298 ps
CPU time 1.99 seconds
Started Oct 02 10:54:16 PM UTC 24
Finished Oct 02 10:54:22 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852597361 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1852597361
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1603282022
Short name T445
Test name
Test status
Simulation time 1176220924 ps
CPU time 1.95 seconds
Started Oct 02 10:54:16 PM UTC 24
Finished Oct 02 10:54:22 PM UTC 24
Peak memory 210624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603282022 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1603282022
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3052328999
Short name T449
Test name
Test status
Simulation time 313092797 ps
CPU time 0.75 seconds
Started Oct 02 10:54:20 PM UTC 24
Finished Oct 02 10:54:35 PM UTC 24
Peak memory 209148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052328999 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3052328999
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_smoke.3109377923
Short name T398
Test name
Test status
Simulation time 66570782 ps
CPU time 0.58 seconds
Started Oct 02 10:54:11 PM UTC 24
Finished Oct 02 10:54:20 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109377923 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.3109377923
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/22.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all.2082251717
Short name T448
Test name
Test status
Simulation time 2346477776 ps
CPU time 3.55 seconds
Started Oct 02 10:54:27 PM UTC 24
Finished Oct 02 10:54:33 PM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082251717 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.2082251717
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/22.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all_with_rand_reset.3300155755
Short name T457
Test name
Test status
Simulation time 8395356687 ps
CPU time 11.1 seconds
Started Oct 02 10:54:26 PM UTC 24
Finished Oct 02 10:54:42 PM UTC 24
Peak memory 211760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3300155755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmg
r_stress_all_with_rand_reset.3300155755
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/22.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup.2019460581
Short name T383
Test name
Test status
Simulation time 58075912 ps
CPU time 0.55 seconds
Started Oct 02 10:54:12 PM UTC 24
Finished Oct 02 10:54:25 PM UTC 24
Peak memory 208856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019460581 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.2019460581
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/22.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_aborted_low_power.3160393918
Short name T459
Test name
Test status
Simulation time 156590909 ps
CPU time 0.63 seconds
Started Oct 02 10:54:33 PM UTC 24
Finished Oct 02 10:54:42 PM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160393918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.3160393918
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_disable_rom_integrity_check.3802249488
Short name T511
Test name
Test status
Simulation time 78222049 ps
CPU time 0.66 seconds
Started Oct 02 10:54:35 PM UTC 24
Finished Oct 02 10:55:07 PM UTC 24
Peak memory 208560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802249488 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_disable_rom_integrity_check.3802249488
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.1528045577
Short name T503
Test name
Test status
Simulation time 31696135 ps
CPU time 0.56 seconds
Started Oct 02 10:54:35 PM UTC 24
Finished Oct 02 10:55:07 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528045577 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_malfunc.1528045577
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_escalation_timeout.2273163979
Short name T512
Test name
Test status
Simulation time 215191676 ps
CPU time 0.82 seconds
Started Oct 02 10:54:35 PM UTC 24
Finished Oct 02 10:55:07 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273163979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.2273163979
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_glitch.835962674
Short name T508
Test name
Test status
Simulation time 55969577 ps
CPU time 0.6 seconds
Started Oct 02 10:54:35 PM UTC 24
Finished Oct 02 10:55:07 PM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835962674 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.835962674
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_global_esc.3930740431
Short name T505
Test name
Test status
Simulation time 42562078 ps
CPU time 0.57 seconds
Started Oct 02 10:54:35 PM UTC 24
Finished Oct 02 10:55:07 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930740431 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.3930740431
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_wakeup_race.2280579588
Short name T452
Test name
Test status
Simulation time 284291234 ps
CPU time 0.79 seconds
Started Oct 02 10:54:31 PM UTC 24
Finished Oct 02 10:54:40 PM UTC 24
Peak memory 208808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280579588 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_wakeup_race.2280579588
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset.1053431144
Short name T386
Test name
Test status
Simulation time 88686488 ps
CPU time 0.89 seconds
Started Oct 02 10:54:31 PM UTC 24
Finished Oct 02 10:54:40 PM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053431144 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.1053431144
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset_invalid.1815760542
Short name T513
Test name
Test status
Simulation time 172319148 ps
CPU time 0.8 seconds
Started Oct 02 10:54:35 PM UTC 24
Finished Oct 02 10:55:07 PM UTC 24
Peak memory 220308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815760542 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.1815760542
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.4020127702
Short name T506
Test name
Test status
Simulation time 110188353 ps
CPU time 0.66 seconds
Started Oct 02 10:54:35 PM UTC 24
Finished Oct 02 10:55:07 PM UTC 24
Peak memory 208872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020127702 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_ctrl_config_regwen.4020127702
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3728690302
Short name T451
Test name
Test status
Simulation time 1003447012 ps
CPU time 2.35 seconds
Started Oct 02 10:54:33 PM UTC 24
Finished Oct 02 10:54:37 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728690302 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3728690302
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1851833677
Short name T460
Test name
Test status
Simulation time 1385738131 ps
CPU time 1.68 seconds
Started Oct 02 10:54:34 PM UTC 24
Finished Oct 02 10:54:44 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851833677 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1851833677
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1519374527
Short name T514
Test name
Test status
Simulation time 73003633 ps
CPU time 0.93 seconds
Started Oct 02 10:54:35 PM UTC 24
Finished Oct 02 10:55:07 PM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519374527 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1519374527
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_smoke.4032711833
Short name T455
Test name
Test status
Simulation time 57593174 ps
CPU time 0.56 seconds
Started Oct 02 10:54:29 PM UTC 24
Finished Oct 02 10:54:41 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032711833 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.4032711833
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all.2632476807
Short name T456
Test name
Test status
Simulation time 78520676 ps
CPU time 0.87 seconds
Started Oct 02 10:54:36 PM UTC 24
Finished Oct 02 10:54:41 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632476807 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.2632476807
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all_with_rand_reset.3515280598
Short name T98
Test name
Test status
Simulation time 1650146733 ps
CPU time 3.41 seconds
Started Oct 02 10:54:36 PM UTC 24
Finished Oct 02 10:54:44 PM UTC 24
Peak memory 211564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3515280598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmg
r_stress_all_with_rand_reset.3515280598
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup.1079032319
Short name T453
Test name
Test status
Simulation time 336899206 ps
CPU time 0.82 seconds
Started Oct 02 10:54:31 PM UTC 24
Finished Oct 02 10:54:40 PM UTC 24
Peak memory 209468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079032319 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.1079032319
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup_reset.3686684505
Short name T450
Test name
Test status
Simulation time 325167293 ps
CPU time 0.88 seconds
Started Oct 02 10:54:33 PM UTC 24
Finished Oct 02 10:54:35 PM UTC 24
Peak memory 210468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686684505 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.3686684505
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/23.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_aborted_low_power.3050481978
Short name T461
Test name
Test status
Simulation time 90743981 ps
CPU time 0.64 seconds
Started Oct 02 10:54:43 PM UTC 24
Finished Oct 02 10:54:45 PM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050481978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.3050481978
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/24.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.152238383
Short name T462
Test name
Test status
Simulation time 38002547 ps
CPU time 0.54 seconds
Started Oct 02 10:54:43 PM UTC 24
Finished Oct 02 10:54:46 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152238383 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_malfunc.152238383
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_global_esc.4183917382
Short name T463
Test name
Test status
Simulation time 73738683 ps
CPU time 0.53 seconds
Started Oct 02 10:54:43 PM UTC 24
Finished Oct 02 10:54:46 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183917382 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.4183917382
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/24.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_wakeup_race.178332074
Short name T484
Test name
Test status
Simulation time 272167290 ps
CPU time 0.77 seconds
Started Oct 02 10:54:41 PM UTC 24
Finished Oct 02 10:55:00 PM UTC 24
Peak memory 209472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178332074 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_wakeup_race.178332074
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset.122114768
Short name T482
Test name
Test status
Simulation time 124334546 ps
CPU time 0.74 seconds
Started Oct 02 10:54:41 PM UTC 24
Finished Oct 02 10:55:00 PM UTC 24
Peak memory 208640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122114768 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.122114768
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/24.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset_invalid.92550069
Short name T515
Test name
Test status
Simulation time 105234577 ps
CPU time 0.9 seconds
Started Oct 02 10:54:45 PM UTC 24
Finished Oct 02 10:55:07 PM UTC 24
Peak memory 220304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92550069 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.92550069
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/24.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.1327200801
Short name T465
Test name
Test status
Simulation time 298270968 ps
CPU time 1.23 seconds
Started Oct 02 10:54:43 PM UTC 24
Finished Oct 02 10:54:46 PM UTC 24
Peak memory 210168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327200801 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_ctrl_config_regwen.1327200801
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2453619382
Short name T467
Test name
Test status
Simulation time 870059201 ps
CPU time 3.08 seconds
Started Oct 02 10:54:43 PM UTC 24
Finished Oct 02 10:54:48 PM UTC 24
Peak memory 211444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453619382 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2453619382
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3082825699
Short name T466
Test name
Test status
Simulation time 790914862 ps
CPU time 2.7 seconds
Started Oct 02 10:54:43 PM UTC 24
Finished Oct 02 10:54:48 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082825699 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3082825699
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.372174277
Short name T464
Test name
Test status
Simulation time 105528368 ps
CPU time 0.72 seconds
Started Oct 02 10:54:43 PM UTC 24
Finished Oct 02 10:54:46 PM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372174277 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_mubi.372174277
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_smoke.4092301984
Short name T458
Test name
Test status
Simulation time 45865157 ps
CPU time 0.58 seconds
Started Oct 02 10:54:37 PM UTC 24
Finished Oct 02 10:54:42 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092301984 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.4092301984
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/24.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all.503694772
Short name T490
Test name
Test status
Simulation time 1712786882 ps
CPU time 5.58 seconds
Started Oct 02 10:54:45 PM UTC 24
Finished Oct 02 10:55:05 PM UTC 24
Peak memory 211536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503694772 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.503694772
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/24.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all_with_rand_reset.1785149315
Short name T136
Test name
Test status
Simulation time 17237586760 ps
CPU time 21.12 seconds
Started Oct 02 10:54:45 PM UTC 24
Finished Oct 02 10:55:31 PM UTC 24
Peak memory 211752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1785149315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmg
r_stress_all_with_rand_reset.1785149315
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/24.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_aborted_low_power.4268787321
Short name T475
Test name
Test status
Simulation time 68147313 ps
CPU time 0.8 seconds
Started Oct 02 10:54:46 PM UTC 24
Finished Oct 02 10:54:55 PM UTC 24
Peak memory 210328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268787321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.4268787321
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_disable_rom_integrity_check.4206779548
Short name T479
Test name
Test status
Simulation time 59281632 ps
CPU time 0.71 seconds
Started Oct 02 10:54:51 PM UTC 24
Finished Oct 02 10:54:56 PM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206779548 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_disable_rom_integrity_check.4206779548
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.2110373148
Short name T536
Test name
Test status
Simulation time 34807550 ps
CPU time 0.59 seconds
Started Oct 02 10:54:50 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 208788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110373148 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_malfunc.2110373148
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_escalation_timeout.133272187
Short name T478
Test name
Test status
Simulation time 866567944 ps
CPU time 0.77 seconds
Started Oct 02 10:54:51 PM UTC 24
Finished Oct 02 10:54:56 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133272187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.133272187
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_glitch.4237178413
Short name T496
Test name
Test status
Simulation time 40502017 ps
CPU time 0.59 seconds
Started Oct 02 10:54:51 PM UTC 24
Finished Oct 02 10:55:06 PM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237178413 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.4237178413
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_global_esc.4293231375
Short name T476
Test name
Test status
Simulation time 31231934 ps
CPU time 0.57 seconds
Started Oct 02 10:54:51 PM UTC 24
Finished Oct 02 10:54:55 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293231375 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.4293231375
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_invalid.556268629
Short name T45
Test name
Test status
Simulation time 200920952 ps
CPU time 0.61 seconds
Started Oct 02 10:54:52 PM UTC 24
Finished Oct 02 10:55:01 PM UTC 24
Peak memory 210164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556268629 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invalid.556268629
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_wakeup_race.1765158616
Short name T473
Test name
Test status
Simulation time 256106284 ps
CPU time 0.66 seconds
Started Oct 02 10:54:46 PM UTC 24
Finished Oct 02 10:54:55 PM UTC 24
Peak memory 208988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765158616 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wakeup_race.1765158616
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset.2027594835
Short name T485
Test name
Test status
Simulation time 86911299 ps
CPU time 0.78 seconds
Started Oct 02 10:54:45 PM UTC 24
Finished Oct 02 10:55:01 PM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027594835 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.2027594835
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset_invalid.3151430741
Short name T477
Test name
Test status
Simulation time 163149027 ps
CPU time 0.72 seconds
Started Oct 02 10:54:51 PM UTC 24
Finished Oct 02 10:54:56 PM UTC 24
Peak memory 220364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151430741 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.3151430741
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.311663301
Short name T481
Test name
Test status
Simulation time 115759546 ps
CPU time 0.91 seconds
Started Oct 02 10:54:51 PM UTC 24
Finished Oct 02 10:54:56 PM UTC 24
Peak memory 210004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311663301 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_ctrl_config_regwen.311663301
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1269947813
Short name T550
Test name
Test status
Simulation time 111871359 ps
CPU time 0.89 seconds
Started Oct 02 10:54:50 PM UTC 24
Finished Oct 02 10:55:12 PM UTC 24
Peak memory 209572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269947813 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1269947813
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_smoke.3550334838
Short name T483
Test name
Test status
Simulation time 31159095 ps
CPU time 0.63 seconds
Started Oct 02 10:54:45 PM UTC 24
Finished Oct 02 10:55:00 PM UTC 24
Peak memory 207960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550334838 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.3550334838
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.2195147788
Short name T488
Test name
Test status
Simulation time 783794500 ps
CPU time 3.12 seconds
Started Oct 02 10:54:52 PM UTC 24
Finished Oct 02 10:55:03 PM UTC 24
Peak memory 211444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195147788 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.2195147788
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all_with_rand_reset.3119444617
Short name T517
Test name
Test status
Simulation time 6820525674 ps
CPU time 8.46 seconds
Started Oct 02 10:54:52 PM UTC 24
Finished Oct 02 10:55:09 PM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3119444617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmg
r_stress_all_with_rand_reset.3119444617
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup.3880064311
Short name T480
Test name
Test status
Simulation time 314390298 ps
CPU time 1.28 seconds
Started Oct 02 10:54:46 PM UTC 24
Finished Oct 02 10:54:56 PM UTC 24
Peak memory 209792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880064311 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.3880064311
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup_reset.605836893
Short name T474
Test name
Test status
Simulation time 52641060 ps
CPU time 0.67 seconds
Started Oct 02 10:54:46 PM UTC 24
Finished Oct 02 10:54:55 PM UTC 24
Peak memory 208380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605836893 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.605836893
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/25.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_aborted_low_power.1521401630
Short name T548
Test name
Test status
Simulation time 70968630 ps
CPU time 0.91 seconds
Started Oct 02 10:54:56 PM UTC 24
Finished Oct 02 10:55:12 PM UTC 24
Peak memory 210832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521401630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.1521401630
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.3395323441
Short name T495
Test name
Test status
Simulation time 83289658 ps
CPU time 0.62 seconds
Started Oct 02 10:55:01 PM UTC 24
Finished Oct 02 10:55:06 PM UTC 24
Peak memory 208168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395323441 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disable_rom_integrity_check.3395323441
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.516630290
Short name T492
Test name
Test status
Simulation time 31480720 ps
CPU time 0.57 seconds
Started Oct 02 10:54:57 PM UTC 24
Finished Oct 02 10:55:06 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516630290 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst_malfunc.516630290
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.1558557806
Short name T497
Test name
Test status
Simulation time 388560163 ps
CPU time 0.75 seconds
Started Oct 02 10:54:57 PM UTC 24
Finished Oct 02 10:55:06 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558557806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.1558557806
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.1520611722
Short name T494
Test name
Test status
Simulation time 38902616 ps
CPU time 0.53 seconds
Started Oct 02 10:55:01 PM UTC 24
Finished Oct 02 10:55:06 PM UTC 24
Peak memory 208468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520611722 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.1520611722
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.2074729456
Short name T493
Test name
Test status
Simulation time 63982449 ps
CPU time 0.54 seconds
Started Oct 02 10:54:57 PM UTC 24
Finished Oct 02 10:55:06 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074729456 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.2074729456
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_invalid.4060497577
Short name T509
Test name
Test status
Simulation time 77929568 ps
CPU time 0.64 seconds
Started Oct 02 10:55:02 PM UTC 24
Finished Oct 02 10:55:07 PM UTC 24
Peak memory 210164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060497577 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invalid.4060497577
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_wakeup_race.613716248
Short name T538
Test name
Test status
Simulation time 74923059 ps
CPU time 0.76 seconds
Started Oct 02 10:54:56 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613716248 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_wakeup_race.613716248
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset.709390876
Short name T534
Test name
Test status
Simulation time 62243841 ps
CPU time 0.67 seconds
Started Oct 02 10:54:56 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709390876 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.709390876
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.1831069639
Short name T502
Test name
Test status
Simulation time 100792774 ps
CPU time 1.07 seconds
Started Oct 02 10:55:02 PM UTC 24
Finished Oct 02 10:55:07 PM UTC 24
Peak memory 220368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831069639 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.1831069639
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.3229547282
Short name T500
Test name
Test status
Simulation time 191817348 ps
CPU time 0.95 seconds
Started Oct 02 10:54:57 PM UTC 24
Finished Oct 02 10:55:06 PM UTC 24
Peak memory 209924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229547282 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_ctrl_config_regwen.3229547282
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2226687614
Short name T560
Test name
Test status
Simulation time 755913751 ps
CPU time 2.83 seconds
Started Oct 02 10:54:56 PM UTC 24
Finished Oct 02 10:55:14 PM UTC 24
Peak memory 211508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226687614 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2226687614
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2020761405
Short name T491
Test name
Test status
Simulation time 1194841519 ps
CPU time 1.8 seconds
Started Oct 02 10:54:56 PM UTC 24
Finished Oct 02 10:55:06 PM UTC 24
Peak memory 210564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020761405 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2020761405
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.152482321
Short name T489
Test name
Test status
Simulation time 70637627 ps
CPU time 0.82 seconds
Started Oct 02 10:54:56 PM UTC 24
Finished Oct 02 10:55:05 PM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152482321 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_mubi.152482321
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_smoke.359936539
Short name T486
Test name
Test status
Simulation time 71209416 ps
CPU time 0.58 seconds
Started Oct 02 10:54:52 PM UTC 24
Finished Oct 02 10:55:01 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359936539 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.359936539
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.637101578
Short name T525
Test name
Test status
Simulation time 269754221 ps
CPU time 1.39 seconds
Started Oct 02 10:55:02 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637101578 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.637101578
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.1152450528
Short name T56
Test name
Test status
Simulation time 1020101799 ps
CPU time 5.15 seconds
Started Oct 02 10:55:02 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 211624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1152450528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmg
r_stress_all_with_rand_reset.1152450528
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.1968472991
Short name T535
Test name
Test status
Simulation time 134884157 ps
CPU time 0.74 seconds
Started Oct 02 10:54:56 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 208496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968472991 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.1968472991
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup_reset.1913015255
Short name T551
Test name
Test status
Simulation time 182933408 ps
CPU time 1.03 seconds
Started Oct 02 10:54:56 PM UTC 24
Finished Oct 02 10:55:12 PM UTC 24
Peak memory 209916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913015255 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.1913015255
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/26.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.4157602393
Short name T549
Test name
Test status
Simulation time 43091130 ps
CPU time 0.93 seconds
Started Oct 02 10:55:06 PM UTC 24
Finished Oct 02 10:55:12 PM UTC 24
Peak memory 210232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157602393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.4157602393
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.2839866286
Short name T546
Test name
Test status
Simulation time 240907484 ps
CPU time 0.66 seconds
Started Oct 02 10:55:07 PM UTC 24
Finished Oct 02 10:55:12 PM UTC 24
Peak memory 208944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839866286 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disable_rom_integrity_check.2839866286
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.804182322
Short name T540
Test name
Test status
Simulation time 40463585 ps
CPU time 0.68 seconds
Started Oct 02 10:55:07 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804182322 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_malfunc.804182322
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_escalation_timeout.322063835
Short name T554
Test name
Test status
Simulation time 203209051 ps
CPU time 0.94 seconds
Started Oct 02 10:55:07 PM UTC 24
Finished Oct 02 10:55:12 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322063835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.322063835
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_glitch.2037160377
Short name T545
Test name
Test status
Simulation time 23003357 ps
CPU time 0.63 seconds
Started Oct 02 10:55:07 PM UTC 24
Finished Oct 02 10:55:12 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037160377 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.2037160377
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_global_esc.2793821605
Short name T543
Test name
Test status
Simulation time 110678049 ps
CPU time 0.67 seconds
Started Oct 02 10:55:07 PM UTC 24
Finished Oct 02 10:55:12 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793821605 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.2793821605
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.2491990950
Short name T523
Test name
Test status
Simulation time 317065574 ps
CPU time 0.88 seconds
Started Oct 02 10:55:05 PM UTC 24
Finished Oct 02 10:55:10 PM UTC 24
Peak memory 209804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491990950 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_wakeup_race.2491990950
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.2110558432
Short name T498
Test name
Test status
Simulation time 177787816 ps
CPU time 0.78 seconds
Started Oct 02 10:55:04 PM UTC 24
Finished Oct 02 10:55:06 PM UTC 24
Peak memory 209676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110558432 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.2110558432
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset_invalid.922187665
Short name T553
Test name
Test status
Simulation time 152785842 ps
CPU time 0.83 seconds
Started Oct 02 10:55:07 PM UTC 24
Finished Oct 02 10:55:12 PM UTC 24
Peak memory 220308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922187665 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.922187665
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.2880292304
Short name T552
Test name
Test status
Simulation time 218987560 ps
CPU time 0.89 seconds
Started Oct 02 10:55:07 PM UTC 24
Finished Oct 02 10:55:12 PM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880292304 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_ctrl_config_regwen.2880292304
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1965364348
Short name T559
Test name
Test status
Simulation time 838949313 ps
CPU time 2.42 seconds
Started Oct 02 10:55:06 PM UTC 24
Finished Oct 02 10:55:13 PM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965364348 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1965364348
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.773666056
Short name T561
Test name
Test status
Simulation time 777750476 ps
CPU time 3.01 seconds
Started Oct 02 10:55:07 PM UTC 24
Finished Oct 02 10:55:14 PM UTC 24
Peak memory 211416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773666056 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.773666056
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.3391357530
Short name T547
Test name
Test status
Simulation time 93371865 ps
CPU time 0.92 seconds
Started Oct 02 10:55:07 PM UTC 24
Finished Oct 02 10:55:12 PM UTC 24
Peak memory 209512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391357530 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_mubi.3391357530
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.1770771213
Short name T470
Test name
Test status
Simulation time 55794148 ps
CPU time 0.62 seconds
Started Oct 02 10:55:02 PM UTC 24
Finished Oct 02 10:55:10 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770771213 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.1770771213
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all.4167505369
Short name T581
Test name
Test status
Simulation time 1530341017 ps
CPU time 5.53 seconds
Started Oct 02 10:55:07 PM UTC 24
Finished Oct 02 10:55:17 PM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167505369 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.4167505369
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all_with_rand_reset.934169651
Short name T133
Test name
Test status
Simulation time 6662918208 ps
CPU time 8.62 seconds
Started Oct 02 10:55:07 PM UTC 24
Finished Oct 02 10:55:20 PM UTC 24
Peak memory 211688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=934169651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr
_stress_all_with_rand_reset.934169651
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.3789936324
Short name T516
Test name
Test status
Simulation time 198328695 ps
CPU time 0.89 seconds
Started Oct 02 10:55:05 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789936324 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.3789936324
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.1850093453
Short name T544
Test name
Test status
Simulation time 128924891 ps
CPU time 0.99 seconds
Started Oct 02 10:55:06 PM UTC 24
Finished Oct 02 10:55:12 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850093453 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.1850093453
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/27.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.3899466208
Short name T528
Test name
Test status
Simulation time 60962032 ps
CPU time 0.66 seconds
Started Oct 02 10:55:08 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899466208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.3899466208
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.1332791142
Short name T522
Test name
Test status
Simulation time 166708341 ps
CPU time 0.67 seconds
Started Oct 02 10:55:08 PM UTC 24
Finished Oct 02 10:55:10 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332791142 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_disable_rom_integrity_check.1332791142
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.2987919853
Short name T454
Test name
Test status
Simulation time 73526077 ps
CPU time 0.55 seconds
Started Oct 02 10:55:08 PM UTC 24
Finished Oct 02 10:55:10 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987919853 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst_malfunc.2987919853
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_escalation_timeout.3379738004
Short name T521
Test name
Test status
Simulation time 208335631 ps
CPU time 0.81 seconds
Started Oct 02 10:55:08 PM UTC 24
Finished Oct 02 10:55:10 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379738004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.3379738004
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_glitch.4084781721
Short name T520
Test name
Test status
Simulation time 66758639 ps
CPU time 0.56 seconds
Started Oct 02 10:55:08 PM UTC 24
Finished Oct 02 10:55:10 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084781721 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.4084781721
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_global_esc.2207863806
Short name T504
Test name
Test status
Simulation time 54471846 ps
CPU time 0.55 seconds
Started Oct 02 10:55:08 PM UTC 24
Finished Oct 02 10:55:10 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207863806 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.2207863806
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_wakeup_race.1028713813
Short name T526
Test name
Test status
Simulation time 67190509 ps
CPU time 0.59 seconds
Started Oct 02 10:55:08 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 208848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028713813 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_wakeup_race.1028713813
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset.362479209
Short name T555
Test name
Test status
Simulation time 89678301 ps
CPU time 0.66 seconds
Started Oct 02 10:55:07 PM UTC 24
Finished Oct 02 10:55:12 PM UTC 24
Peak memory 208640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362479209 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.362479209
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset_invalid.4284499939
Short name T541
Test name
Test status
Simulation time 166748298 ps
CPU time 0.74 seconds
Started Oct 02 10:55:10 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 220304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284499939 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.4284499939
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.499563474
Short name T524
Test name
Test status
Simulation time 194016425 ps
CPU time 1.02 seconds
Started Oct 02 10:55:08 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 209740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499563474 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_ctrl_config_regwen.499563474
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.971034247
Short name T542
Test name
Test status
Simulation time 1319835140 ps
CPU time 2.13 seconds
Started Oct 02 10:55:08 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 211496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971034247 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.971034247
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3428717945
Short name T527
Test name
Test status
Simulation time 1811372317 ps
CPU time 1.76 seconds
Started Oct 02 10:55:08 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 210616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428717945 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3428717945
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.3101811745
Short name T519
Test name
Test status
Simulation time 97976401 ps
CPU time 0.73 seconds
Started Oct 02 10:55:08 PM UTC 24
Finished Oct 02 10:55:10 PM UTC 24
Peak memory 209208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101811745 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig_mubi.3101811745
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_smoke.450196443
Short name T556
Test name
Test status
Simulation time 29513094 ps
CPU time 0.69 seconds
Started Oct 02 10:55:07 PM UTC 24
Finished Oct 02 10:55:12 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450196443 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.450196443
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all.2004273486
Short name T562
Test name
Test status
Simulation time 705067963 ps
CPU time 2.42 seconds
Started Oct 02 10:55:11 PM UTC 24
Finished Oct 02 10:55:14 PM UTC 24
Peak memory 211608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004273486 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.2004273486
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all_with_rand_reset.2223300774
Short name T134
Test name
Test status
Simulation time 30840322463 ps
CPU time 12.52 seconds
Started Oct 02 10:55:11 PM UTC 24
Finished Oct 02 10:55:24 PM UTC 24
Peak memory 211808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2223300774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmg
r_stress_all_with_rand_reset.2223300774
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup.18923363
Short name T533
Test name
Test status
Simulation time 322759720 ps
CPU time 0.91 seconds
Started Oct 02 10:55:08 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18923363 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.18923363
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup_reset.2002443265
Short name T539
Test name
Test status
Simulation time 377359932 ps
CPU time 1.04 seconds
Started Oct 02 10:55:08 PM UTC 24
Finished Oct 02 10:55:11 PM UTC 24
Peak memory 210744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002443265 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.2002443265
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/28.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_aborted_low_power.765414316
Short name T582
Test name
Test status
Simulation time 28753171 ps
CPU time 0.68 seconds
Started Oct 02 10:55:11 PM UTC 24
Finished Oct 02 10:55:20 PM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765414316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.765414316
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_disable_rom_integrity_check.2493971333
Short name T605
Test name
Test status
Simulation time 85179522 ps
CPU time 0.68 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493971333 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_disable_rom_integrity_check.2493971333
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2506421628
Short name T572
Test name
Test status
Simulation time 31267894 ps
CPU time 0.61 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:15 PM UTC 24
Peak memory 208776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506421628 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_malfunc.2506421628
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_escalation_timeout.1783655274
Short name T529
Test name
Test status
Simulation time 109732794 ps
CPU time 0.83 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:16 PM UTC 24
Peak memory 208120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783655274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.1783655274
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_glitch.1575128816
Short name T604
Test name
Test status
Simulation time 34514056 ps
CPU time 0.56 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:25 PM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575128816 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.1575128816
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_global_esc.645861788
Short name T578
Test name
Test status
Simulation time 74017147 ps
CPU time 0.66 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:15 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645861788 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.645861788
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_invalid.4208396164
Short name T577
Test name
Test status
Simulation time 39040277 ps
CPU time 0.65 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:15 PM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208396164 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invalid.4208396164
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_wakeup_race.1507149364
Short name T568
Test name
Test status
Simulation time 290919201 ps
CPU time 0.68 seconds
Started Oct 02 10:55:11 PM UTC 24
Finished Oct 02 10:55:20 PM UTC 24
Peak memory 208988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507149364 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_wakeup_race.1507149364
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset.2851597832
Short name T558
Test name
Test status
Simulation time 132212786 ps
CPU time 0.65 seconds
Started Oct 02 10:55:11 PM UTC 24
Finished Oct 02 10:55:13 PM UTC 24
Peak memory 208740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851597832 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.2851597832
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset_invalid.2764769463
Short name T611
Test name
Test status
Simulation time 162157915 ps
CPU time 0.76 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 220304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764769463 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.2764769463
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.1990701881
Short name T579
Test name
Test status
Simulation time 31565741 ps
CPU time 0.7 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:15 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990701881 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_ctrl_config_regwen.1990701881
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1464196408
Short name T531
Test name
Test status
Simulation time 864619105 ps
CPU time 2.27 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:17 PM UTC 24
Peak memory 211568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464196408 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1464196408
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3671631180
Short name T530
Test name
Test status
Simulation time 1881932260 ps
CPU time 1.91 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:17 PM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671631180 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3671631180
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1367060742
Short name T576
Test name
Test status
Simulation time 174962241 ps
CPU time 0.83 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:15 PM UTC 24
Peak memory 209572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367060742 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1367060742
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_smoke.93866395
Short name T557
Test name
Test status
Simulation time 34927596 ps
CPU time 0.64 seconds
Started Oct 02 10:55:11 PM UTC 24
Finished Oct 02 10:55:13 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93866395 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.93866395
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all.484859713
Short name T629
Test name
Test status
Simulation time 3185153616 ps
CPU time 3.49 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:29 PM UTC 24
Peak memory 211676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484859713 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.484859713
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all_with_rand_reset.3817056097
Short name T97
Test name
Test status
Simulation time 4580918948 ps
CPU time 8.83 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:34 PM UTC 24
Peak memory 211620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3817056097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmg
r_stress_all_with_rand_reset.3817056097
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup.396491249
Short name T518
Test name
Test status
Simulation time 185578155 ps
CPU time 0.77 seconds
Started Oct 02 10:55:11 PM UTC 24
Finished Oct 02 10:55:20 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396491249 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.396491249
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup_reset.618231505
Short name T566
Test name
Test status
Simulation time 65478363 ps
CPU time 0.76 seconds
Started Oct 02 10:55:11 PM UTC 24
Finished Oct 02 10:55:20 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618231505 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.618231505
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/29.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.2145202070
Short name T106
Test name
Test status
Simulation time 41829196 ps
CPU time 1.12 seconds
Started Oct 02 10:53:10 PM UTC 24
Finished Oct 02 10:53:12 PM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145202070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.2145202070
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.818478210
Short name T152
Test name
Test status
Simulation time 64442875 ps
CPU time 1.3 seconds
Started Oct 02 10:53:12 PM UTC 24
Finished Oct 02 10:53:14 PM UTC 24
Peak memory 208648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818478210 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disable_rom_integrity_check.818478210
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2827422979
Short name T143
Test name
Test status
Simulation time 29035781 ps
CPU time 0.92 seconds
Started Oct 02 10:53:11 PM UTC 24
Finished Oct 02 10:53:13 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827422979 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_malfunc.2827422979
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.3092224330
Short name T144
Test name
Test status
Simulation time 400617031 ps
CPU time 1.11 seconds
Started Oct 02 10:53:11 PM UTC 24
Finished Oct 02 10:53:14 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092224330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.3092224330
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.1293323683
Short name T190
Test name
Test status
Simulation time 48395835 ps
CPU time 1.01 seconds
Started Oct 02 10:53:11 PM UTC 24
Finished Oct 02 10:53:14 PM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293323683 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.1293323683
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.2725920309
Short name T12
Test name
Test status
Simulation time 52503658 ps
CPU time 0.92 seconds
Started Oct 02 10:53:11 PM UTC 24
Finished Oct 02 10:53:13 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725920309 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.2725920309
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.3892501771
Short name T189
Test name
Test status
Simulation time 176227614 ps
CPU time 1.59 seconds
Started Oct 02 10:53:10 PM UTC 24
Finished Oct 02 10:53:12 PM UTC 24
Peak memory 208740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892501771 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wakeup_race.3892501771
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.2436422491
Short name T186
Test name
Test status
Simulation time 447630857 ps
CPU time 1 seconds
Started Oct 02 10:53:10 PM UTC 24
Finished Oct 02 10:53:12 PM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436422491 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.2436422491
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.384107244
Short name T192
Test name
Test status
Simulation time 147804309 ps
CPU time 1.01 seconds
Started Oct 02 10:53:12 PM UTC 24
Finished Oct 02 10:53:14 PM UTC 24
Peak memory 220304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384107244 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.384107244
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.47687749
Short name T29
Test name
Test status
Simulation time 2308347440 ps
CPU time 1.64 seconds
Started Oct 02 10:53:12 PM UTC 24
Finished Oct 02 10:53:14 PM UTC 24
Peak memory 237512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47687749 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.47687749
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.2216643974
Short name T61
Test name
Test status
Simulation time 159725651 ps
CPU time 1.53 seconds
Started Oct 02 10:53:11 PM UTC 24
Finished Oct 02 10:53:14 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216643974 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_ctrl_config_regwen.2216643974
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2390532935
Short name T151
Test name
Test status
Simulation time 1048791294 ps
CPU time 2.4 seconds
Started Oct 02 10:53:10 PM UTC 24
Finished Oct 02 10:53:13 PM UTC 24
Peak memory 211344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390532935 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.2390532935
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.450184995
Short name T187
Test name
Test status
Simulation time 95151728 ps
CPU time 1.09 seconds
Started Oct 02 10:53:10 PM UTC 24
Finished Oct 02 10:53:12 PM UTC 24
Peak memory 208940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450184995 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_mubi.450184995
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.2715820936
Short name T185
Test name
Test status
Simulation time 28987647 ps
CPU time 0.96 seconds
Started Oct 02 10:53:10 PM UTC 24
Finished Oct 02 10:53:12 PM UTC 24
Peak memory 208316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715820936 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.2715820936
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.1743299653
Short name T93
Test name
Test status
Simulation time 2515580826 ps
CPU time 5.56 seconds
Started Oct 02 10:53:13 PM UTC 24
Finished Oct 02 10:53:20 PM UTC 24
Peak memory 211544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743299653 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.1743299653
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.3636702502
Short name T188
Test name
Test status
Simulation time 293787594 ps
CPU time 1.5 seconds
Started Oct 02 10:53:10 PM UTC 24
Finished Oct 02 10:53:12 PM UTC 24
Peak memory 209720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636702502 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.3636702502
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.3249308706
Short name T78
Test name
Test status
Simulation time 155207341 ps
CPU time 1.08 seconds
Started Oct 02 10:53:10 PM UTC 24
Finished Oct 02 10:53:12 PM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249308706 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.3249308706
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/3.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_aborted_low_power.4114700372
Short name T616
Test name
Test status
Simulation time 59478247 ps
CPU time 0.75 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 208992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114700372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.4114700372
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.1075188836
Short name T573
Test name
Test status
Simulation time 58238003 ps
CPU time 0.85 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:15 PM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075188836 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disable_rom_integrity_check.1075188836
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.417545056
Short name T617
Test name
Test status
Simulation time 27905403 ps
CPU time 0.57 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417545056 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_malfunc.417545056
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_escalation_timeout.1784263477
Short name T567
Test name
Test status
Simulation time 347989024 ps
CPU time 0.83 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:15 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784263477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.1784263477
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_glitch.1553920807
Short name T564
Test name
Test status
Simulation time 54958345 ps
CPU time 0.6 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:15 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553920807 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.1553920807
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_global_esc.1578785073
Short name T563
Test name
Test status
Simulation time 37715004 ps
CPU time 0.54 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:15 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578785073 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.1578785073
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_wakeup_race.2011097022
Short name T619
Test name
Test status
Simulation time 183971707 ps
CPU time 0.88 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 208988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011097022 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_wakeup_race.2011097022
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset.119614636
Short name T610
Test name
Test status
Simulation time 41687327 ps
CPU time 0.74 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 208372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119614636 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.119614636
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset_invalid.4190564816
Short name T569
Test name
Test status
Simulation time 323423228 ps
CPU time 0.77 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:15 PM UTC 24
Peak memory 220724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190564816 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.4190564816
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.1977001251
Short name T570
Test name
Test status
Simulation time 212522886 ps
CPU time 0.98 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:15 PM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977001251 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_ctrl_config_regwen.1977001251
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2882733427
Short name T627
Test name
Test status
Simulation time 888039483 ps
CPU time 2.34 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:28 PM UTC 24
Peak memory 211572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882733427 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2882733427
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.218025538
Short name T626
Test name
Test status
Simulation time 1285099921 ps
CPU time 2.06 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:28 PM UTC 24
Peak memory 211384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218025538 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.218025538
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3087323772
Short name T621
Test name
Test status
Simulation time 64320944 ps
CPU time 0.78 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 209148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087323772 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3087323772
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_smoke.2562941874
Short name T609
Test name
Test status
Simulation time 53053432 ps
CPU time 0.64 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562941874 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.2562941874
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all.2079838609
Short name T565
Test name
Test status
Simulation time 1469115871 ps
CPU time 3.73 seconds
Started Oct 02 10:55:14 PM UTC 24
Finished Oct 02 10:55:18 PM UTC 24
Peak memory 211536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079838609 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.2079838609
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all_with_rand_reset.1324887157
Short name T650
Test name
Test status
Simulation time 11464831155 ps
CPU time 15.84 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:31 PM UTC 24
Peak memory 211696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1324887157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmg
r_stress_all_with_rand_reset.1324887157
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup.317034208
Short name T615
Test name
Test status
Simulation time 288465514 ps
CPU time 0.65 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317034208 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.317034208
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup_reset.1128082370
Short name T623
Test name
Test status
Simulation time 264159240 ps
CPU time 1.06 seconds
Started Oct 02 10:55:13 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 210644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128082370 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.1128082370
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/30.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_aborted_low_power.4027478690
Short name T636
Test name
Test status
Simulation time 66404229 ps
CPU time 0.7 seconds
Started Oct 02 10:55:15 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027478690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.4027478690
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_disable_rom_integrity_check.2338718590
Short name T587
Test name
Test status
Simulation time 58830321 ps
CPU time 0.71 seconds
Started Oct 02 10:55:16 PM UTC 24
Finished Oct 02 10:55:21 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338718590 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disable_rom_integrity_check.2338718590
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2602266098
Short name T635
Test name
Test status
Simulation time 36469245 ps
CPU time 0.57 seconds
Started Oct 02 10:55:15 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602266098 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_malfunc.2602266098
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_escalation_timeout.291273977
Short name T588
Test name
Test status
Simulation time 1835823777 ps
CPU time 0.79 seconds
Started Oct 02 10:55:16 PM UTC 24
Finished Oct 02 10:55:21 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291273977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.291273977
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_glitch.3250601696
Short name T586
Test name
Test status
Simulation time 40720689 ps
CPU time 0.6 seconds
Started Oct 02 10:55:16 PM UTC 24
Finished Oct 02 10:55:21 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250601696 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.3250601696
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_global_esc.1348469651
Short name T584
Test name
Test status
Simulation time 24404685 ps
CPU time 0.55 seconds
Started Oct 02 10:55:16 PM UTC 24
Finished Oct 02 10:55:21 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348469651 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.1348469651
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_wakeup_race.125465741
Short name T580
Test name
Test status
Simulation time 235187015 ps
CPU time 1.09 seconds
Started Oct 02 10:55:14 PM UTC 24
Finished Oct 02 10:55:16 PM UTC 24
Peak memory 209296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125465741 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_wakeup_race.125465741
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset.3429147890
Short name T574
Test name
Test status
Simulation time 87278258 ps
CPU time 0.67 seconds
Started Oct 02 10:55:14 PM UTC 24
Finished Oct 02 10:55:15 PM UTC 24
Peak memory 208380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429147890 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.3429147890
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset_invalid.529923539
Short name T591
Test name
Test status
Simulation time 126735787 ps
CPU time 0.75 seconds
Started Oct 02 10:55:16 PM UTC 24
Finished Oct 02 10:55:21 PM UTC 24
Peak memory 220664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529923539 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.529923539
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.2328031689
Short name T652
Test name
Test status
Simulation time 205265692 ps
CPU time 1.13 seconds
Started Oct 02 10:55:15 PM UTC 24
Finished Oct 02 10:55:31 PM UTC 24
Peak memory 209796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328031689 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_ctrl_config_regwen.2328031689
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2854388021
Short name T657
Test name
Test status
Simulation time 958486755 ps
CPU time 2.37 seconds
Started Oct 02 10:55:15 PM UTC 24
Finished Oct 02 10:55:32 PM UTC 24
Peak memory 211500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854388021 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2854388021
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.636008773
Short name T659
Test name
Test status
Simulation time 934794545 ps
CPU time 2.43 seconds
Started Oct 02 10:55:15 PM UTC 24
Finished Oct 02 10:55:32 PM UTC 24
Peak memory 211508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636008773 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.636008773
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1778768377
Short name T642
Test name
Test status
Simulation time 126199943 ps
CPU time 0.89 seconds
Started Oct 02 10:55:15 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 209472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778768377 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1778768377
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_smoke.3965073203
Short name T571
Test name
Test status
Simulation time 32863754 ps
CPU time 0.62 seconds
Started Oct 02 10:55:14 PM UTC 24
Finished Oct 02 10:55:15 PM UTC 24
Peak memory 208976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965073203 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.3965073203
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all.3346305365
Short name T600
Test name
Test status
Simulation time 922304975 ps
CPU time 3.37 seconds
Started Oct 02 10:55:16 PM UTC 24
Finished Oct 02 10:55:24 PM UTC 24
Peak memory 211532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346305365 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.3346305365
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all_with_rand_reset.685128052
Short name T73
Test name
Test status
Simulation time 5052277668 ps
CPU time 11.78 seconds
Started Oct 02 10:55:16 PM UTC 24
Finished Oct 02 10:55:32 PM UTC 24
Peak memory 211688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=685128052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr
_stress_all_with_rand_reset.685128052
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup.1053984443
Short name T575
Test name
Test status
Simulation time 240957489 ps
CPU time 0.72 seconds
Started Oct 02 10:55:14 PM UTC 24
Finished Oct 02 10:55:15 PM UTC 24
Peak memory 209036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053984443 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.1053984443
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup_reset.1047556713
Short name T637
Test name
Test status
Simulation time 118187522 ps
CPU time 0.75 seconds
Started Oct 02 10:55:15 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047556713 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.1047556713
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/31.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.1527298614
Short name T594
Test name
Test status
Simulation time 38702615 ps
CPU time 0.81 seconds
Started Oct 02 10:55:17 PM UTC 24
Finished Oct 02 10:55:22 PM UTC 24
Peak memory 210004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527298614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.1527298614
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.3134677213
Short name T601
Test name
Test status
Simulation time 168157472 ps
CPU time 0.63 seconds
Started Oct 02 10:55:20 PM UTC 24
Finished Oct 02 10:55:25 PM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134677213 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disable_rom_integrity_check.3134677213
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.1323062654
Short name T532
Test name
Test status
Simulation time 54861945 ps
CPU time 0.51 seconds
Started Oct 02 10:55:18 PM UTC 24
Finished Oct 02 10:55:20 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323062654 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_malfunc.1323062654
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_escalation_timeout.3775958811
Short name T585
Test name
Test status
Simulation time 338786887 ps
CPU time 0.75 seconds
Started Oct 02 10:55:19 PM UTC 24
Finished Oct 02 10:55:21 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775958811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.3775958811
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_glitch.2758011255
Short name T595
Test name
Test status
Simulation time 343007239 ps
CPU time 0.59 seconds
Started Oct 02 10:55:20 PM UTC 24
Finished Oct 02 10:55:22 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758011255 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.2758011255
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_global_esc.1419398651
Short name T537
Test name
Test status
Simulation time 24250566 ps
CPU time 0.55 seconds
Started Oct 02 10:55:18 PM UTC 24
Finished Oct 02 10:55:21 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419398651 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.1419398651
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_invalid.1251668701
Short name T603
Test name
Test status
Simulation time 81728849 ps
CPU time 0.61 seconds
Started Oct 02 10:55:20 PM UTC 24
Finished Oct 02 10:55:25 PM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251668701 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invalid.1251668701
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_wakeup_race.3173745681
Short name T592
Test name
Test status
Simulation time 90984985 ps
CPU time 0.6 seconds
Started Oct 02 10:55:17 PM UTC 24
Finished Oct 02 10:55:21 PM UTC 24
Peak memory 208988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173745681 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_wakeup_race.3173745681
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset.2661991834
Short name T590
Test name
Test status
Simulation time 67051187 ps
CPU time 0.57 seconds
Started Oct 02 10:55:17 PM UTC 24
Finished Oct 02 10:55:21 PM UTC 24
Peak memory 208380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661991834 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.2661991834
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset_invalid.1388991257
Short name T602
Test name
Test status
Simulation time 151420226 ps
CPU time 0.73 seconds
Started Oct 02 10:55:20 PM UTC 24
Finished Oct 02 10:55:25 PM UTC 24
Peak memory 220724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388991257 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.1388991257
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.1610640887
Short name T583
Test name
Test status
Simulation time 208945885 ps
CPU time 0.76 seconds
Started Oct 02 10:55:18 PM UTC 24
Finished Oct 02 10:55:21 PM UTC 24
Peak memory 210128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610640887 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_ctrl_config_regwen.1610640887
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1290437430
Short name T599
Test name
Test status
Simulation time 1009706960 ps
CPU time 1.92 seconds
Started Oct 02 10:55:17 PM UTC 24
Finished Oct 02 10:55:23 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290437430 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1290437430
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.333180436
Short name T598
Test name
Test status
Simulation time 2451248369 ps
CPU time 1.93 seconds
Started Oct 02 10:55:17 PM UTC 24
Finished Oct 02 10:55:23 PM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333180436 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.333180436
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2337892622
Short name T596
Test name
Test status
Simulation time 139491798 ps
CPU time 0.79 seconds
Started Oct 02 10:55:17 PM UTC 24
Finished Oct 02 10:55:22 PM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337892622 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2337892622
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_smoke.2485038448
Short name T589
Test name
Test status
Simulation time 76466674 ps
CPU time 0.6 seconds
Started Oct 02 10:55:16 PM UTC 24
Finished Oct 02 10:55:21 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485038448 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.2485038448
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all.2714749345
Short name T630
Test name
Test status
Simulation time 2155379539 ps
CPU time 2.87 seconds
Started Oct 02 10:55:21 PM UTC 24
Finished Oct 02 10:55:29 PM UTC 24
Peak memory 211668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714749345 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.2714749345
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.4185491430
Short name T135
Test name
Test status
Simulation time 2068546831 ps
CPU time 6.36 seconds
Started Oct 02 10:55:20 PM UTC 24
Finished Oct 02 10:55:31 PM UTC 24
Peak memory 211380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4185491430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmg
r_stress_all_with_rand_reset.4185491430
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup.443660618
Short name T593
Test name
Test status
Simulation time 106172141 ps
CPU time 0.76 seconds
Started Oct 02 10:55:17 PM UTC 24
Finished Oct 02 10:55:21 PM UTC 24
Peak memory 208556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443660618 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.443660618
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup_reset.784464641
Short name T597
Test name
Test status
Simulation time 489818087 ps
CPU time 1.11 seconds
Started Oct 02 10:55:17 PM UTC 24
Finished Oct 02 10:55:22 PM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784464641 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.784464641
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/32.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_aborted_low_power.2471589252
Short name T634
Test name
Test status
Simulation time 80203877 ps
CPU time 0.7 seconds
Started Oct 02 10:55:22 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471589252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.2471589252
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.3428242608
Short name T618
Test name
Test status
Simulation time 62392954 ps
CPU time 0.78 seconds
Started Oct 02 10:55:23 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 208620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428242608 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_disable_rom_integrity_check.3428242608
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.1514978429
Short name T608
Test name
Test status
Simulation time 28900853 ps
CPU time 0.59 seconds
Started Oct 02 10:55:23 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 207208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514978429 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst_malfunc.1514978429
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_escalation_timeout.2134688787
Short name T612
Test name
Test status
Simulation time 230426277 ps
CPU time 0.81 seconds
Started Oct 02 10:55:23 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 207420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134688787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.2134688787
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_glitch.257035671
Short name T613
Test name
Test status
Simulation time 50127508 ps
CPU time 0.57 seconds
Started Oct 02 10:55:23 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257035671 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.257035671
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_global_esc.967995835
Short name T606
Test name
Test status
Simulation time 26605884 ps
CPU time 0.53 seconds
Started Oct 02 10:55:23 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967995835 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.967995835
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_wakeup_race.2866448725
Short name T625
Test name
Test status
Simulation time 182333666 ps
CPU time 0.76 seconds
Started Oct 02 10:55:22 PM UTC 24
Finished Oct 02 10:55:27 PM UTC 24
Peak memory 208748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866448725 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wakeup_race.2866448725
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset.1502634512
Short name T624
Test name
Test status
Simulation time 108036383 ps
CPU time 0.63 seconds
Started Oct 02 10:55:21 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 209004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502634512 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.1502634512
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.3337761695
Short name T620
Test name
Test status
Simulation time 122146689 ps
CPU time 0.78 seconds
Started Oct 02 10:55:23 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 220364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337761695 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.3337761695
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.4100215824
Short name T614
Test name
Test status
Simulation time 540452088 ps
CPU time 0.82 seconds
Started Oct 02 10:55:23 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100215824 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_ctrl_config_regwen.4100215824
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.851885688
Short name T654
Test name
Test status
Simulation time 1082549972 ps
CPU time 1.85 seconds
Started Oct 02 10:55:22 PM UTC 24
Finished Oct 02 10:55:31 PM UTC 24
Peak memory 210256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851885688 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.851885688
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2987987925
Short name T628
Test name
Test status
Simulation time 881087747 ps
CPU time 3.01 seconds
Started Oct 02 10:55:23 PM UTC 24
Finished Oct 02 10:55:28 PM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987987925 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2987987925
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.1297225315
Short name T607
Test name
Test status
Simulation time 128734980 ps
CPU time 0.77 seconds
Started Oct 02 10:55:23 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 209472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297225315 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_mubi.1297225315
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_smoke.2757178803
Short name T622
Test name
Test status
Simulation time 26670034 ps
CPU time 0.61 seconds
Started Oct 02 10:55:21 PM UTC 24
Finished Oct 02 10:55:26 PM UTC 24
Peak memory 208320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757178803 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.2757178803
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all.2944830755
Short name T631
Test name
Test status
Simulation time 5773167387 ps
CPU time 3.44 seconds
Started Oct 02 10:55:24 PM UTC 24
Finished Oct 02 10:55:29 PM UTC 24
Peak memory 211740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944830755 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.2944830755
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all_with_rand_reset.877775680
Short name T137
Test name
Test status
Simulation time 1992527736 ps
CPU time 6.88 seconds
Started Oct 02 10:55:24 PM UTC 24
Finished Oct 02 10:55:32 PM UTC 24
Peak memory 211564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=877775680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr
_stress_all_with_rand_reset.877775680
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup.3994291664
Short name T633
Test name
Test status
Simulation time 198970310 ps
CPU time 0.81 seconds
Started Oct 02 10:55:22 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994291664 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.3994291664
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup_reset.2119694969
Short name T632
Test name
Test status
Simulation time 66798920 ps
CPU time 0.56 seconds
Started Oct 02 10:55:22 PM UTC 24
Finished Oct 02 10:55:29 PM UTC 24
Peak memory 208380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119694969 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.2119694969
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/33.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_aborted_low_power.2859923163
Short name T655
Test name
Test status
Simulation time 19952396 ps
CPU time 0.64 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:32 PM UTC 24
Peak memory 208968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859923163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.2859923163
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_disable_rom_integrity_check.2401973805
Short name T668
Test name
Test status
Simulation time 83239430 ps
CPU time 0.66 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 209688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401973805 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disable_rom_integrity_check.2401973805
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.2202625055
Short name T673
Test name
Test status
Simulation time 29556123 ps
CPU time 0.64 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202625055 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_malfunc.2202625055
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_escalation_timeout.1287698993
Short name T675
Test name
Test status
Simulation time 110382979 ps
CPU time 0.82 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 208440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287698993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.1287698993
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_glitch.1512702850
Short name T666
Test name
Test status
Simulation time 75733054 ps
CPU time 0.6 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512702850 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.1512702850
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_global_esc.365535598
Short name T670
Test name
Test status
Simulation time 34822884 ps
CPU time 0.58 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365535598 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.365535598
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_wakeup_race.1001213811
Short name T640
Test name
Test status
Simulation time 170819543 ps
CPU time 0.7 seconds
Started Oct 02 10:55:25 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 208848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001213811 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_wakeup_race.1001213811
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset.3270061726
Short name T645
Test name
Test status
Simulation time 147084730 ps
CPU time 0.81 seconds
Started Oct 02 10:55:25 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 208964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270061726 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.3270061726
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset_invalid.2543969744
Short name T672
Test name
Test status
Simulation time 353407513 ps
CPU time 0.75 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 220304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543969744 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.2543969744
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.2147999979
Short name T685
Test name
Test status
Simulation time 250828193 ps
CPU time 0.98 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:36 PM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147999979 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_ctrl_config_regwen.2147999979
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2776633223
Short name T661
Test name
Test status
Simulation time 777387270 ps
CPU time 2.79 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:34 PM UTC 24
Peak memory 211376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776633223 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2776633223
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3261358392
Short name T662
Test name
Test status
Simulation time 885261202 ps
CPU time 2.81 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:34 PM UTC 24
Peak memory 211688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261358392 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3261358392
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.3380120736
Short name T665
Test name
Test status
Simulation time 61623572 ps
CPU time 0.78 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380120736 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_mubi.3380120736
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_smoke.91125008
Short name T639
Test name
Test status
Simulation time 31340953 ps
CPU time 0.65 seconds
Started Oct 02 10:55:25 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 208092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91125008 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.91125008
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all.3445626263
Short name T692
Test name
Test status
Simulation time 1473813657 ps
CPU time 2.96 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:38 PM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445626263 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.3445626263
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all_with_rand_reset.2268514278
Short name T46
Test name
Test status
Simulation time 6779700721 ps
CPU time 9 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:43 PM UTC 24
Peak memory 211616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2268514278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmg
r_stress_all_with_rand_reset.2268514278
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup.2217658168
Short name T643
Test name
Test status
Simulation time 95822632 ps
CPU time 0.68 seconds
Started Oct 02 10:55:25 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 209036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217658168 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.2217658168
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup_reset.1612418127
Short name T649
Test name
Test status
Simulation time 164936620 ps
CPU time 0.84 seconds
Started Oct 02 10:55:25 PM UTC 24
Finished Oct 02 10:55:31 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612418127 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.1612418127
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/34.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_aborted_low_power.753337770
Short name T638
Test name
Test status
Simulation time 39164031 ps
CPU time 0.61 seconds
Started Oct 02 10:55:28 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 208808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753337770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.753337770
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_disable_rom_integrity_check.551640784
Short name T663
Test name
Test status
Simulation time 47325489 ps
CPU time 0.71 seconds
Started Oct 02 10:55:30 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 208324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551640784 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disable_rom_integrity_check.551640784
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.901738043
Short name T647
Test name
Test status
Simulation time 38055558 ps
CPU time 0.59 seconds
Started Oct 02 10:55:29 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901738043 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_malfunc.901738043
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_escalation_timeout.1880918143
Short name T658
Test name
Test status
Simulation time 394093874 ps
CPU time 0.75 seconds
Started Oct 02 10:55:30 PM UTC 24
Finished Oct 02 10:55:32 PM UTC 24
Peak memory 208896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880918143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.1880918143
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_glitch.2228107701
Short name T664
Test name
Test status
Simulation time 59165637 ps
CPU time 0.58 seconds
Started Oct 02 10:55:30 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228107701 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.2228107701
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_global_esc.162165878
Short name T646
Test name
Test status
Simulation time 163496292 ps
CPU time 0.58 seconds
Started Oct 02 10:55:29 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162165878 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.162165878
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_wakeup_race.168287897
Short name T641
Test name
Test status
Simulation time 173204960 ps
CPU time 0.76 seconds
Started Oct 02 10:55:28 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168287897 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_wakeup_race.168287897
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset.3355179576
Short name T676
Test name
Test status
Simulation time 103195092 ps
CPU time 0.65 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 208380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355179576 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.3355179576
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset_invalid.2258912709
Short name T688
Test name
Test status
Simulation time 108275907 ps
CPU time 1.02 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:36 PM UTC 24
Peak memory 220368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258912709 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.2258912709
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.550889692
Short name T653
Test name
Test status
Simulation time 131794139 ps
CPU time 0.69 seconds
Started Oct 02 10:55:29 PM UTC 24
Finished Oct 02 10:55:31 PM UTC 24
Peak memory 208744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550889692 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_ctrl_config_regwen.550889692
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3799373379
Short name T660
Test name
Test status
Simulation time 930347372 ps
CPU time 2.25 seconds
Started Oct 02 10:55:28 PM UTC 24
Finished Oct 02 10:55:32 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799373379 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3799373379
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1827398809
Short name T656
Test name
Test status
Simulation time 1254463061 ps
CPU time 2 seconds
Started Oct 02 10:55:28 PM UTC 24
Finished Oct 02 10:55:32 PM UTC 24
Peak memory 210912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827398809 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1827398809
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.891533291
Short name T651
Test name
Test status
Simulation time 164783902 ps
CPU time 0.84 seconds
Started Oct 02 10:55:29 PM UTC 24
Finished Oct 02 10:55:31 PM UTC 24
Peak memory 209532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891533291 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_mubi.891533291
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_smoke.1661022569
Short name T667
Test name
Test status
Simulation time 38770469 ps
CPU time 0.59 seconds
Started Oct 02 10:55:27 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661022569 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.1661022569
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all.3152668293
Short name T693
Test name
Test status
Simulation time 731316462 ps
CPU time 3.31 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:39 PM UTC 24
Peak memory 211424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152668293 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.3152668293
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all_with_rand_reset.125730377
Short name T74
Test name
Test status
Simulation time 3883743195 ps
CPU time 13.24 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:56 PM UTC 24
Peak memory 211624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=125730377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr
_stress_all_with_rand_reset.125730377
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup.1524429144
Short name T644
Test name
Test status
Simulation time 249321922 ps
CPU time 0.79 seconds
Started Oct 02 10:55:28 PM UTC 24
Finished Oct 02 10:55:30 PM UTC 24
Peak memory 209792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524429144 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.1524429144
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup_reset.1954087473
Short name T648
Test name
Test status
Simulation time 215239354 ps
CPU time 1.05 seconds
Started Oct 02 10:55:28 PM UTC 24
Finished Oct 02 10:55:31 PM UTC 24
Peak memory 209976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954087473 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.1954087473
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/35.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_aborted_low_power.3899592093
Short name T703
Test name
Test status
Simulation time 27872537 ps
CPU time 0.64 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:40 PM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899592093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.3899592093
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_disable_rom_integrity_check.1681843778
Short name T697
Test name
Test status
Simulation time 69396831 ps
CPU time 0.64 seconds
Started Oct 02 10:55:32 PM UTC 24
Finished Oct 02 10:55:39 PM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681843778 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_disable_rom_integrity_check.1681843778
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2183518507
Short name T735
Test name
Test status
Simulation time 36591626 ps
CPU time 0.58 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:43 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183518507 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_malfunc.2183518507
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_escalation_timeout.1798795362
Short name T699
Test name
Test status
Simulation time 396585769 ps
CPU time 0.79 seconds
Started Oct 02 10:55:32 PM UTC 24
Finished Oct 02 10:55:40 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798795362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.1798795362
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_glitch.2389991471
Short name T694
Test name
Test status
Simulation time 41116468 ps
CPU time 0.56 seconds
Started Oct 02 10:55:32 PM UTC 24
Finished Oct 02 10:55:39 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389991471 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.2389991471
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_global_esc.1942373696
Short name T702
Test name
Test status
Simulation time 44158756 ps
CPU time 0.55 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:40 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942373696 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.1942373696
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_wakeup_race.2500975919
Short name T740
Test name
Test status
Simulation time 774224887 ps
CPU time 0.88 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:43 PM UTC 24
Peak memory 210284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500975919 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_wakeup_race.2500975919
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset.1308763755
Short name T732
Test name
Test status
Simulation time 45130857 ps
CPU time 0.73 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:43 PM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308763755 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.1308763755
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset_invalid.3737009278
Short name T700
Test name
Test status
Simulation time 101272395 ps
CPU time 0.84 seconds
Started Oct 02 10:55:32 PM UTC 24
Finished Oct 02 10:55:40 PM UTC 24
Peak memory 219300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737009278 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.3737009278
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.2454533027
Short name T743
Test name
Test status
Simulation time 87344923 ps
CPU time 0.86 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454533027 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_ctrl_config_regwen.2454533027
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2719543054
Short name T709
Test name
Test status
Simulation time 1151959190 ps
CPU time 2.11 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 211628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719543054 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2719543054
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3201874975
Short name T758
Test name
Test status
Simulation time 1096458080 ps
CPU time 1.96 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:45 PM UTC 24
Peak memory 210624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201874975 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3201874975
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.2910982623
Short name T738
Test name
Test status
Simulation time 63659910 ps
CPU time 0.89 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:43 PM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910982623 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig_mubi.2910982623
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_smoke.3928192317
Short name T696
Test name
Test status
Simulation time 56134843 ps
CPU time 0.61 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:39 PM UTC 24
Peak memory 207024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928192317 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.3928192317
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all.1756171844
Short name T690
Test name
Test status
Simulation time 2633687387 ps
CPU time 1.83 seconds
Started Oct 02 10:55:33 PM UTC 24
Finished Oct 02 10:55:37 PM UTC 24
Peak memory 210776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756171844 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.1756171844
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.1926080804
Short name T836
Test name
Test status
Simulation time 10636448076 ps
CPU time 22.45 seconds
Started Oct 02 10:55:33 PM UTC 24
Finished Oct 02 10:56:05 PM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1926080804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmg
r_stress_all_with_rand_reset.1926080804
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup.3489898993
Short name T736
Test name
Test status
Simulation time 59129538 ps
CPU time 0.59 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:43 PM UTC 24
Peak memory 209036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489898993 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.3489898993
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup_reset.971772294
Short name T745
Test name
Test status
Simulation time 181741228 ps
CPU time 0.98 seconds
Started Oct 02 10:55:31 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 209916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971772294 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.971772294
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/36.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_aborted_low_power.2668872909
Short name T678
Test name
Test status
Simulation time 28506664 ps
CPU time 0.7 seconds
Started Oct 02 10:55:33 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 209068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668872909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.2668872909
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_disable_rom_integrity_check.489266839
Short name T712
Test name
Test status
Simulation time 98824777 ps
CPU time 0.69 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 208948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489266839 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disable_rom_integrity_check.489266839
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.709248949
Short name T680
Test name
Test status
Simulation time 29545993 ps
CPU time 0.58 seconds
Started Oct 02 10:55:33 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 208852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709248949 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_malfunc.709248949
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_escalation_timeout.1284812543
Short name T701
Test name
Test status
Simulation time 111614422 ps
CPU time 0.85 seconds
Started Oct 02 10:55:35 PM UTC 24
Finished Oct 02 10:55:40 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284812543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.1284812543
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_glitch.1885638179
Short name T698
Test name
Test status
Simulation time 64618236 ps
CPU time 0.61 seconds
Started Oct 02 10:55:35 PM UTC 24
Finished Oct 02 10:55:39 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885638179 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.1885638179
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_global_esc.3808921569
Short name T695
Test name
Test status
Simulation time 49654951 ps
CPU time 0.58 seconds
Started Oct 02 10:55:35 PM UTC 24
Finished Oct 02 10:55:39 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808921569 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.3808921569
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_wakeup_race.2524980798
Short name T682
Test name
Test status
Simulation time 165895220 ps
CPU time 0.76 seconds
Started Oct 02 10:55:33 PM UTC 24
Finished Oct 02 10:55:36 PM UTC 24
Peak memory 208808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524980798 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_wakeup_race.2524980798
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset.3996682055
Short name T674
Test name
Test status
Simulation time 74184998 ps
CPU time 0.78 seconds
Started Oct 02 10:55:33 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 209436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996682055 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.3996682055
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset_invalid.4044976784
Short name T710
Test name
Test status
Simulation time 232881701 ps
CPU time 0.73 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 220304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044976784 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.4044976784
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.4020045482
Short name T683
Test name
Test status
Simulation time 150487572 ps
CPU time 0.9 seconds
Started Oct 02 10:55:34 PM UTC 24
Finished Oct 02 10:55:36 PM UTC 24
Peak memory 210540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020045482 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_ctrl_config_regwen.4020045482
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1102890846
Short name T689
Test name
Test status
Simulation time 1029509056 ps
CPU time 1.87 seconds
Started Oct 02 10:55:33 PM UTC 24
Finished Oct 02 10:55:37 PM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102890846 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1102890846
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1822952608
Short name T691
Test name
Test status
Simulation time 3595641437 ps
CPU time 1.88 seconds
Started Oct 02 10:55:33 PM UTC 24
Finished Oct 02 10:55:37 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822952608 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1822952608
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.2800378700
Short name T681
Test name
Test status
Simulation time 67208635 ps
CPU time 0.81 seconds
Started Oct 02 10:55:33 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800378700 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_mubi.2800378700
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_smoke.2248924885
Short name T686
Test name
Test status
Simulation time 32405652 ps
CPU time 0.65 seconds
Started Oct 02 10:55:33 PM UTC 24
Finished Oct 02 10:55:36 PM UTC 24
Peak memory 208320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248924885 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.2248924885
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all.823590234
Short name T779
Test name
Test status
Simulation time 1922337971 ps
CPU time 6.07 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:46 PM UTC 24
Peak memory 211548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823590234 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.823590234
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.4249297142
Short name T54
Test name
Test status
Simulation time 11694491879 ps
CPU time 13.79 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:54 PM UTC 24
Peak memory 211752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4249297142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmg
r_stress_all_with_rand_reset.4249297142
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup.3745399568
Short name T669
Test name
Test status
Simulation time 51553578 ps
CPU time 0.63 seconds
Started Oct 02 10:55:33 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 209036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745399568 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.3745399568
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup_reset.3192193723
Short name T679
Test name
Test status
Simulation time 284829890 ps
CPU time 0.88 seconds
Started Oct 02 10:55:33 PM UTC 24
Finished Oct 02 10:55:35 PM UTC 24
Peak memory 209976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192193723 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.3192193723
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/37.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_aborted_low_power.1529554906
Short name T718
Test name
Test status
Simulation time 24671947 ps
CPU time 0.65 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529554906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.1529554906
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_disable_rom_integrity_check.1806978197
Short name T705
Test name
Test status
Simulation time 61902138 ps
CPU time 0.69 seconds
Started Oct 02 10:55:38 PM UTC 24
Finished Oct 02 10:55:40 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806978197 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disable_rom_integrity_check.1806978197
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.4141938083
Short name T684
Test name
Test status
Simulation time 33725811 ps
CPU time 0.57 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141938083 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst_malfunc.4141938083
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_escalation_timeout.1665614363
Short name T723
Test name
Test status
Simulation time 205027873 ps
CPU time 0.79 seconds
Started Oct 02 10:55:37 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665614363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.1665614363
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_glitch.521291233
Short name T704
Test name
Test status
Simulation time 48444218 ps
CPU time 0.61 seconds
Started Oct 02 10:55:38 PM UTC 24
Finished Oct 02 10:55:40 PM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521291233 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.521291233
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_global_esc.3129419041
Short name T687
Test name
Test status
Simulation time 33279568 ps
CPU time 0.63 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129419041 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.3129419041
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_wakeup_race.2676554204
Short name T713
Test name
Test status
Simulation time 127687190 ps
CPU time 0.63 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 207968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676554204 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_wakeup_race.2676554204
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset.2850941122
Short name T677
Test name
Test status
Simulation time 144468128 ps
CPU time 0.77 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 208380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850941122 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.2850941122
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset_invalid.2236306994
Short name T716
Test name
Test status
Simulation time 108566302 ps
CPU time 1.11 seconds
Started Oct 02 10:55:38 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 220368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236306994 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.2236306994
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.4100895062
Short name T722
Test name
Test status
Simulation time 76260216 ps
CPU time 0.63 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 208800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100895062 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_ctrl_config_regwen.4100895062
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.939427394
Short name T730
Test name
Test status
Simulation time 922586670 ps
CPU time 2.4 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:43 PM UTC 24
Peak memory 211440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939427394 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.939427394
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.234130348
Short name T742
Test name
Test status
Simulation time 723972065 ps
CPU time 3.02 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 211696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234130348 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.234130348
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3167584524
Short name T721
Test name
Test status
Simulation time 59073282 ps
CPU time 0.77 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167584524 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3167584524
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_smoke.166284774
Short name T711
Test name
Test status
Simulation time 58306971 ps
CPU time 0.6 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 207876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166284774 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.166284774
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.4188539862
Short name T757
Test name
Test status
Simulation time 1922878007 ps
CPU time 4.6 seconds
Started Oct 02 10:55:38 PM UTC 24
Finished Oct 02 10:55:45 PM UTC 24
Peak memory 211532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188539862 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.4188539862
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.3439057867
Short name T140
Test name
Test status
Simulation time 6280661866 ps
CPU time 19.13 seconds
Started Oct 02 10:55:38 PM UTC 24
Finished Oct 02 10:55:59 PM UTC 24
Peak memory 211632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3439057867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmg
r_stress_all_with_rand_reset.3439057867
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup.1614735220
Short name T720
Test name
Test status
Simulation time 194094147 ps
CPU time 0.65 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 209036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614735220 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.1614735220
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup_reset.945264139
Short name T717
Test name
Test status
Simulation time 128961856 ps
CPU time 0.68 seconds
Started Oct 02 10:55:36 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945264139 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.945264139
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/38.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_aborted_low_power.3552338867
Short name T715
Test name
Test status
Simulation time 43205729 ps
CPU time 0.86 seconds
Started Oct 02 10:55:39 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552338867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.3552338867
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.702293836
Short name T724
Test name
Test status
Simulation time 32445063 ps
CPU time 0.6 seconds
Started Oct 02 10:55:40 PM UTC 24
Finished Oct 02 10:55:42 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702293836 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_malfunc.702293836
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_escalation_timeout.3825157064
Short name T728
Test name
Test status
Simulation time 388460765 ps
CPU time 0.9 seconds
Started Oct 02 10:55:40 PM UTC 24
Finished Oct 02 10:55:42 PM UTC 24
Peak memory 208464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825157064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.3825157064
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_glitch.4169763262
Short name T727
Test name
Test status
Simulation time 38443218 ps
CPU time 0.55 seconds
Started Oct 02 10:55:40 PM UTC 24
Finished Oct 02 10:55:42 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169763262 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.4169763262
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_global_esc.2200237898
Short name T726
Test name
Test status
Simulation time 55107780 ps
CPU time 0.6 seconds
Started Oct 02 10:55:40 PM UTC 24
Finished Oct 02 10:55:42 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200237898 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.2200237898
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_wakeup_race.4156949389
Short name T671
Test name
Test status
Simulation time 239471268 ps
CPU time 1.08 seconds
Started Oct 02 10:55:38 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 209864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156949389 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_wakeup_race.4156949389
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset.1987218304
Short name T708
Test name
Test status
Simulation time 125806369 ps
CPU time 0.74 seconds
Started Oct 02 10:55:38 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 208380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987218304 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.1987218304
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.1643368923
Short name T741
Test name
Test status
Simulation time 168053963 ps
CPU time 0.74 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 220664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643368923 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.1643368923
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.1451963682
Short name T729
Test name
Test status
Simulation time 238879924 ps
CPU time 1.11 seconds
Started Oct 02 10:55:40 PM UTC 24
Finished Oct 02 10:55:42 PM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451963682 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_ctrl_config_regwen.1451963682
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2390067723
Short name T731
Test name
Test status
Simulation time 1602757837 ps
CPU time 1.81 seconds
Started Oct 02 10:55:40 PM UTC 24
Finished Oct 02 10:55:43 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390067723 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2390067723
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1170297982
Short name T737
Test name
Test status
Simulation time 965210081 ps
CPU time 2.19 seconds
Started Oct 02 10:55:40 PM UTC 24
Finished Oct 02 10:55:43 PM UTC 24
Peak memory 211756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170297982 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1170297982
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2411694770
Short name T725
Test name
Test status
Simulation time 93384397 ps
CPU time 0.76 seconds
Started Oct 02 10:55:40 PM UTC 24
Finished Oct 02 10:55:42 PM UTC 24
Peak memory 209148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411694770 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2411694770
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.3464880308
Short name T707
Test name
Test status
Simulation time 29871694 ps
CPU time 0.65 seconds
Started Oct 02 10:55:38 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464880308 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.3464880308
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.1853497234
Short name T760
Test name
Test status
Simulation time 4202281123 ps
CPU time 2.17 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:45 PM UTC 24
Peak memory 211500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853497234 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.1853497234
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all_with_rand_reset.494532970
Short name T810
Test name
Test status
Simulation time 3729130941 ps
CPU time 7.98 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:51 PM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=494532970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr
_stress_all_with_rand_reset.494532970
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.1429633898
Short name T714
Test name
Test status
Simulation time 126122499 ps
CPU time 0.88 seconds
Started Oct 02 10:55:38 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 209036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429633898 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.1429633898
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup_reset.3898570956
Short name T719
Test name
Test status
Simulation time 196975347 ps
CPU time 0.92 seconds
Started Oct 02 10:55:39 PM UTC 24
Finished Oct 02 10:55:41 PM UTC 24
Peak memory 209916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898570956 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.3898570956
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/39.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.205149855
Short name T84
Test name
Test status
Simulation time 76491945 ps
CPU time 0.99 seconds
Started Oct 02 10:53:13 PM UTC 24
Finished Oct 02 10:53:16 PM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205149855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.205149855
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.3202189305
Short name T153
Test name
Test status
Simulation time 60447033 ps
CPU time 1.08 seconds
Started Oct 02 10:53:15 PM UTC 24
Finished Oct 02 10:53:17 PM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202189305 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disable_rom_integrity_check.3202189305
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1591339327
Short name T145
Test name
Test status
Simulation time 32400982 ps
CPU time 0.61 seconds
Started Oct 02 10:53:15 PM UTC 24
Finished Oct 02 10:53:16 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591339327 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_malfunc.1591339327
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.3953600967
Short name T146
Test name
Test status
Simulation time 202486415 ps
CPU time 0.86 seconds
Started Oct 02 10:53:15 PM UTC 24
Finished Oct 02 10:53:17 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953600967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.3953600967
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.3073938976
Short name T195
Test name
Test status
Simulation time 44482578 ps
CPU time 1.03 seconds
Started Oct 02 10:53:15 PM UTC 24
Finished Oct 02 10:53:17 PM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073938976 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.3073938976
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.1476830864
Short name T197
Test name
Test status
Simulation time 79239948 ps
CPU time 0.89 seconds
Started Oct 02 10:53:15 PM UTC 24
Finished Oct 02 10:53:17 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476830864 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.1476830864
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.3045300623
Short name T196
Test name
Test status
Simulation time 128376115 ps
CPU time 1.18 seconds
Started Oct 02 10:53:13 PM UTC 24
Finished Oct 02 10:53:16 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045300623 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wakeup_race.3045300623
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.2526995896
Short name T37
Test name
Test status
Simulation time 52640024 ps
CPU time 1.09 seconds
Started Oct 02 10:53:13 PM UTC 24
Finished Oct 02 10:53:16 PM UTC 24
Peak memory 209388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526995896 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.2526995896
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.1367818960
Short name T201
Test name
Test status
Simulation time 151413613 ps
CPU time 1.05 seconds
Started Oct 02 10:53:15 PM UTC 24
Finished Oct 02 10:53:17 PM UTC 24
Peak memory 220604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367818960 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1367818960
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.369462288
Short name T30
Test name
Test status
Simulation time 1543875071 ps
CPU time 1.36 seconds
Started Oct 02 10:53:15 PM UTC 24
Finished Oct 02 10:53:17 PM UTC 24
Peak memory 237572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369462288 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.369462288
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.1845593059
Short name T198
Test name
Test status
Simulation time 177525209 ps
CPU time 1.07 seconds
Started Oct 02 10:53:15 PM UTC 24
Finished Oct 02 10:53:17 PM UTC 24
Peak memory 209800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845593059 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_ctrl_config_regwen.1845593059
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2504324012
Short name T157
Test name
Test status
Simulation time 977239677 ps
CPU time 2.73 seconds
Started Oct 02 10:53:13 PM UTC 24
Finished Oct 02 10:53:18 PM UTC 24
Peak memory 211692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504324012 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.2504324012
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4091291825
Short name T88
Test name
Test status
Simulation time 913755042 ps
CPU time 3.61 seconds
Started Oct 02 10:53:15 PM UTC 24
Finished Oct 02 10:53:19 PM UTC 24
Peak memory 211508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091291825 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.4091291825
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.28408398
Short name T200
Test name
Test status
Simulation time 258439648 ps
CPU time 1.22 seconds
Started Oct 02 10:53:15 PM UTC 24
Finished Oct 02 10:53:17 PM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28408398 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_mubi.28408398
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.1888510033
Short name T193
Test name
Test status
Simulation time 32905868 ps
CPU time 0.86 seconds
Started Oct 02 10:53:13 PM UTC 24
Finished Oct 02 10:53:15 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888510033 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.1888510033
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.1002963121
Short name T89
Test name
Test status
Simulation time 1948600641 ps
CPU time 3.25 seconds
Started Oct 02 10:53:15 PM UTC 24
Finished Oct 02 10:53:19 PM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002963121 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.1002963121
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.2936454821
Short name T128
Test name
Test status
Simulation time 4705341575 ps
CPU time 15.41 seconds
Started Oct 02 10:53:15 PM UTC 24
Finished Oct 02 10:53:32 PM UTC 24
Peak memory 211760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2936454821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr
_stress_all_with_rand_reset.2936454821
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.855133240
Short name T191
Test name
Test status
Simulation time 95219492 ps
CPU time 1.26 seconds
Started Oct 02 10:53:13 PM UTC 24
Finished Oct 02 10:53:16 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855133240 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.855133240
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.4197262339
Short name T194
Test name
Test status
Simulation time 60889585 ps
CPU time 0.73 seconds
Started Oct 02 10:53:13 PM UTC 24
Finished Oct 02 10:53:15 PM UTC 24
Peak memory 208740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197262339 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.4197262339
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/4.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.2214114003
Short name T751
Test name
Test status
Simulation time 47831815 ps
CPU time 0.86 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 210652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214114003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.2214114003
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.3776635847
Short name T175
Test name
Test status
Simulation time 65301581 ps
CPU time 0.74 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 209748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776635847 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disable_rom_integrity_check.3776635847
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.1308287576
Short name T747
Test name
Test status
Simulation time 39551813 ps
CPU time 0.57 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308287576 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_malfunc.1308287576
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.4268003462
Short name T756
Test name
Test status
Simulation time 403932351 ps
CPU time 0.88 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268003462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.4268003462
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.380529023
Short name T755
Test name
Test status
Simulation time 45431025 ps
CPU time 0.6 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380529023 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.380529023
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.3971765921
Short name T752
Test name
Test status
Simulation time 31157043 ps
CPU time 0.57 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971765921 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.3971765921
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.2011105192
Short name T749
Test name
Test status
Simulation time 190480587 ps
CPU time 0.9 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011105192 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_wakeup_race.2011105192
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.566267239
Short name T750
Test name
Test status
Simulation time 84936752 ps
CPU time 0.89 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566267239 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.566267239
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.192131710
Short name T767
Test name
Test status
Simulation time 143745768 ps
CPU time 0.77 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:46 PM UTC 24
Peak memory 220304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192131710 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.192131710
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.3442942678
Short name T748
Test name
Test status
Simulation time 30665715 ps
CPU time 0.62 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 208860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442942678 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_ctrl_config_regwen.3442942678
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.736264552
Short name T759
Test name
Test status
Simulation time 1936509660 ps
CPU time 1.88 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:45 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736264552 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.736264552
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2758075275
Short name T764
Test name
Test status
Simulation time 1090311333 ps
CPU time 1.96 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:45 PM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758075275 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2758075275
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2857889352
Short name T753
Test name
Test status
Simulation time 338018747 ps
CPU time 0.8 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857889352 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2857889352
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.3163759035
Short name T744
Test name
Test status
Simulation time 33125108 ps
CPU time 0.68 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163759035 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.3163759035
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.4043370181
Short name T762
Test name
Test status
Simulation time 1328297889 ps
CPU time 3.13 seconds
Started Oct 02 10:55:43 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 211204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043370181 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.4043370181
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.1913650341
Short name T822
Test name
Test status
Simulation time 3770539066 ps
CPU time 8.91 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:52 PM UTC 24
Peak memory 211764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1913650341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmg
r_stress_all_with_rand_reset.1913650341
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.3988350061
Short name T746
Test name
Test status
Simulation time 128725765 ps
CPU time 0.67 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 209036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988350061 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.3988350061
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.2964046021
Short name T754
Test name
Test status
Simulation time 139044746 ps
CPU time 0.93 seconds
Started Oct 02 10:55:42 PM UTC 24
Finished Oct 02 10:55:44 PM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964046021 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.2964046021
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/40.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.1667496955
Short name T769
Test name
Test status
Simulation time 26447116 ps
CPU time 0.69 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:46 PM UTC 24
Peak memory 208940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667496955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.1667496955
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.3695681300
Short name T778
Test name
Test status
Simulation time 86451066 ps
CPU time 0.71 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:46 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695681300 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disable_rom_integrity_check.3695681300
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.1366780665
Short name T770
Test name
Test status
Simulation time 40914818 ps
CPU time 0.62 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:46 PM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366780665 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_malfunc.1366780665
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.2811458323
Short name T777
Test name
Test status
Simulation time 112147698 ps
CPU time 0.8 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:46 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811458323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.2811458323
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.2601763259
Short name T771
Test name
Test status
Simulation time 35117252 ps
CPU time 0.56 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:46 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601763259 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.2601763259
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.1127722540
Short name T774
Test name
Test status
Simulation time 94541385 ps
CPU time 0.59 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:46 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127722540 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.1127722540
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.3811625005
Short name T768
Test name
Test status
Simulation time 161267567 ps
CPU time 0.6 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:46 PM UTC 24
Peak memory 207916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811625005 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_wakeup_race.3811625005
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.798644971
Short name T765
Test name
Test status
Simulation time 48474827 ps
CPU time 0.65 seconds
Started Oct 02 10:55:43 PM UTC 24
Finished Oct 02 10:55:45 PM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798644971 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.798644971
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.3026642485
Short name T780
Test name
Test status
Simulation time 121634010 ps
CPU time 0.89 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:46 PM UTC 24
Peak memory 220364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026642485 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.3026642485
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.2206107599
Short name T772
Test name
Test status
Simulation time 69281835 ps
CPU time 0.66 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:46 PM UTC 24
Peak memory 208228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206107599 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_ctrl_config_regwen.2206107599
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1525383832
Short name T761
Test name
Test status
Simulation time 745220186 ps
CPU time 2.6 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 211700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525383832 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1525383832
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2219605512
Short name T734
Test name
Test status
Simulation time 822945232 ps
CPU time 2.74 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 211412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219605512 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2219605512
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3954190662
Short name T776
Test name
Test status
Simulation time 52122737 ps
CPU time 0.84 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:46 PM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954190662 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3954190662
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.3547182174
Short name T766
Test name
Test status
Simulation time 32895652 ps
CPU time 0.65 seconds
Started Oct 02 10:55:43 PM UTC 24
Finished Oct 02 10:55:45 PM UTC 24
Peak memory 208204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547182174 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.3547182174
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.276544350
Short name T803
Test name
Test status
Simulation time 1790048207 ps
CPU time 3.28 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:50 PM UTC 24
Peak memory 211416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276544350 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.276544350
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.2744279956
Short name T832
Test name
Test status
Simulation time 4390437936 ps
CPU time 12.87 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:58 PM UTC 24
Peak memory 211696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2744279956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmg
r_stress_all_with_rand_reset.2744279956
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.2225967772
Short name T773
Test name
Test status
Simulation time 511946444 ps
CPU time 0.93 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:46 PM UTC 24
Peak memory 209460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225967772 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.2225967772
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.4065881408
Short name T781
Test name
Test status
Simulation time 312743289 ps
CPU time 1.47 seconds
Started Oct 02 10:55:44 PM UTC 24
Finished Oct 02 10:55:47 PM UTC 24
Peak memory 210836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065881408 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.4065881408
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/41.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.2640000609
Short name T785
Test name
Test status
Simulation time 23590327 ps
CPU time 0.74 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 210004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640000609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.2640000609
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.950299286
Short name T763
Test name
Test status
Simulation time 77485989 ps
CPU time 0.67 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 208564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950299286 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disable_rom_integrity_check.950299286
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.3187333782
Short name T786
Test name
Test status
Simulation time 39002216 ps
CPU time 0.6 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187333782 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_malfunc.3187333782
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.4255713407
Short name T739
Test name
Test status
Simulation time 113458665 ps
CPU time 0.79 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255713407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.4255713407
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.2461492583
Short name T787
Test name
Test status
Simulation time 42049807 ps
CPU time 0.55 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461492583 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.2461492583
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.1338076431
Short name T788
Test name
Test status
Simulation time 64050494 ps
CPU time 0.65 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338076431 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.1338076431
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.3387166481
Short name T784
Test name
Test status
Simulation time 89833531 ps
CPU time 0.7 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 208988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387166481 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wakeup_race.3387166481
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.3897613770
Short name T783
Test name
Test status
Simulation time 126838362 ps
CPU time 0.68 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897613770 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.3897613770
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.4191377889
Short name T813
Test name
Test status
Simulation time 146669139 ps
CPU time 0.76 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:51 PM UTC 24
Peak memory 220364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191377889 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.4191377889
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.1507520855
Short name T733
Test name
Test status
Simulation time 78801059 ps
CPU time 0.65 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 208740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507520855 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_ctrl_config_regwen.1507520855
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.135474449
Short name T792
Test name
Test status
Simulation time 1122209786 ps
CPU time 1.99 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:49 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135474449 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.135474449
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1212994925
Short name T790
Test name
Test status
Simulation time 1001286166 ps
CPU time 2 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:49 PM UTC 24
Peak memory 210616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212994925 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1212994925
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.590689588
Short name T706
Test name
Test status
Simulation time 71701085 ps
CPU time 0.87 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 209148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590689588 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_mubi.590689588
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.1433869499
Short name T782
Test name
Test status
Simulation time 62958997 ps
CPU time 0.62 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:47 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433869499 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.1433869499
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.577061764
Short name T830
Test name
Test status
Simulation time 1998327474 ps
CPU time 7.12 seconds
Started Oct 02 10:55:47 PM UTC 24
Finished Oct 02 10:55:58 PM UTC 24
Peak memory 211544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577061764 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.577061764
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.1026182444
Short name T833
Test name
Test status
Simulation time 10378438817 ps
CPU time 11.24 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:56:02 PM UTC 24
Peak memory 211696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1026182444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmg
r_stress_all_with_rand_reset.1026182444
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.2886162239
Short name T775
Test name
Test status
Simulation time 239151529 ps
CPU time 1.35 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 209468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886162239 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.2886162239
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.771389134
Short name T789
Test name
Test status
Simulation time 295773683 ps
CPU time 1.07 seconds
Started Oct 02 10:55:46 PM UTC 24
Finished Oct 02 10:55:48 PM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771389134 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.771389134
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/42.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.3543379200
Short name T793
Test name
Test status
Simulation time 54255287 ps
CPU time 0.73 seconds
Started Oct 02 10:55:47 PM UTC 24
Finished Oct 02 10:55:50 PM UTC 24
Peak memory 208948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543379200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.3543379200
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.3468408694
Short name T798
Test name
Test status
Simulation time 67376301 ps
CPU time 0.84 seconds
Started Oct 02 10:55:48 PM UTC 24
Finished Oct 02 10:55:50 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468408694 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disable_rom_integrity_check.3468408694
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.2453816219
Short name T807
Test name
Test status
Simulation time 38494021 ps
CPU time 0.59 seconds
Started Oct 02 10:55:48 PM UTC 24
Finished Oct 02 10:55:51 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453816219 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_malfunc.2453816219
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.2822748228
Short name T797
Test name
Test status
Simulation time 399963213 ps
CPU time 0.82 seconds
Started Oct 02 10:55:48 PM UTC 24
Finished Oct 02 10:55:50 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822748228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.2822748228
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.1810311455
Short name T795
Test name
Test status
Simulation time 56060173 ps
CPU time 0.58 seconds
Started Oct 02 10:55:48 PM UTC 24
Finished Oct 02 10:55:50 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810311455 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.1810311455
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.2047575888
Short name T809
Test name
Test status
Simulation time 68274244 ps
CPU time 0.56 seconds
Started Oct 02 10:55:48 PM UTC 24
Finished Oct 02 10:55:51 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047575888 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.2047575888
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.4190595285
Short name T794
Test name
Test status
Simulation time 184089675 ps
CPU time 0.99 seconds
Started Oct 02 10:55:47 PM UTC 24
Finished Oct 02 10:55:50 PM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190595285 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_wakeup_race.4190595285
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.2881778266
Short name T814
Test name
Test status
Simulation time 74692649 ps
CPU time 0.66 seconds
Started Oct 02 10:55:47 PM UTC 24
Finished Oct 02 10:55:51 PM UTC 24
Peak memory 208740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881778266 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.2881778266
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.1059644658
Short name T802
Test name
Test status
Simulation time 110508223 ps
CPU time 0.84 seconds
Started Oct 02 10:55:48 PM UTC 24
Finished Oct 02 10:55:50 PM UTC 24
Peak memory 220364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059644658 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.1059644658
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.1831527802
Short name T812
Test name
Test status
Simulation time 335403257 ps
CPU time 1 seconds
Started Oct 02 10:55:48 PM UTC 24
Finished Oct 02 10:55:51 PM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831527802 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_ctrl_config_regwen.1831527802
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2248989817
Short name T821
Test name
Test status
Simulation time 835847915 ps
CPU time 3.22 seconds
Started Oct 02 10:55:47 PM UTC 24
Finished Oct 02 10:55:52 PM UTC 24
Peak memory 211636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248989817 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2248989817
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2284384779
Short name T824
Test name
Test status
Simulation time 1011100555 ps
CPU time 2.78 seconds
Started Oct 02 10:55:48 PM UTC 24
Finished Oct 02 10:55:53 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284384779 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2284384779
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.4039382075
Short name T811
Test name
Test status
Simulation time 244533329 ps
CPU time 0.77 seconds
Started Oct 02 10:55:48 PM UTC 24
Finished Oct 02 10:55:51 PM UTC 24
Peak memory 209472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039382075 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig_mubi.4039382075
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.1168257266
Short name T815
Test name
Test status
Simulation time 32560947 ps
CPU time 0.62 seconds
Started Oct 02 10:55:47 PM UTC 24
Finished Oct 02 10:55:51 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168257266 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.1168257266
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.3126816729
Short name T823
Test name
Test status
Simulation time 4813739452 ps
CPU time 3.56 seconds
Started Oct 02 10:55:48 PM UTC 24
Finished Oct 02 10:55:53 PM UTC 24
Peak memory 211544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126816729 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.3126816729
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.2314197283
Short name T819
Test name
Test status
Simulation time 338089874 ps
CPU time 0.88 seconds
Started Oct 02 10:55:47 PM UTC 24
Finished Oct 02 10:55:52 PM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314197283 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.2314197283
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.4021678788
Short name T799
Test name
Test status
Simulation time 253171723 ps
CPU time 1.27 seconds
Started Oct 02 10:55:47 PM UTC 24
Finished Oct 02 10:55:50 PM UTC 24
Peak memory 210180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021678788 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.4021678788
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/43.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.3785619929
Short name T805
Test name
Test status
Simulation time 22736704 ps
CPU time 0.72 seconds
Started Oct 02 10:55:49 PM UTC 24
Finished Oct 02 10:55:50 PM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785619929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.3785619929
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.3219117663
Short name T818
Test name
Test status
Simulation time 28963335 ps
CPU time 0.61 seconds
Started Oct 02 10:55:50 PM UTC 24
Finished Oct 02 10:55:52 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219117663 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_malfunc.3219117663
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.2381880465
Short name T829
Test name
Test status
Simulation time 204060132 ps
CPU time 0.83 seconds
Started Oct 02 10:55:50 PM UTC 24
Finished Oct 02 10:55:55 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381880465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.2381880465
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.1448806633
Short name T828
Test name
Test status
Simulation time 51810922 ps
CPU time 0.6 seconds
Started Oct 02 10:55:50 PM UTC 24
Finished Oct 02 10:55:55 PM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448806633 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.1448806633
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.289020608
Short name T816
Test name
Test status
Simulation time 83572932 ps
CPU time 0.55 seconds
Started Oct 02 10:55:50 PM UTC 24
Finished Oct 02 10:55:52 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289020608 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.289020608
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.1825375895
Short name T804
Test name
Test status
Simulation time 59623387 ps
CPU time 0.77 seconds
Started Oct 02 10:55:49 PM UTC 24
Finished Oct 02 10:55:50 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825375895 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_wakeup_race.1825375895
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.2184464270
Short name T800
Test name
Test status
Simulation time 20966635 ps
CPU time 0.6 seconds
Started Oct 02 10:55:48 PM UTC 24
Finished Oct 02 10:55:50 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184464270 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.2184464270
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.3160866714
Short name T817
Test name
Test status
Simulation time 63128604 ps
CPU time 0.61 seconds
Started Oct 02 10:55:50 PM UTC 24
Finished Oct 02 10:55:52 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160866714 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_ctrl_config_regwen.3160866714
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.694981147
Short name T825
Test name
Test status
Simulation time 1039680089 ps
CPU time 2.01 seconds
Started Oct 02 10:55:50 PM UTC 24
Finished Oct 02 10:55:53 PM UTC 24
Peak memory 211696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694981147 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.694981147
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3277911351
Short name T827
Test name
Test status
Simulation time 921798795 ps
CPU time 3.25 seconds
Started Oct 02 10:55:50 PM UTC 24
Finished Oct 02 10:55:54 PM UTC 24
Peak memory 211508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277911351 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3277911351
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.2907887726
Short name T820
Test name
Test status
Simulation time 192847145 ps
CPU time 0.85 seconds
Started Oct 02 10:55:50 PM UTC 24
Finished Oct 02 10:55:52 PM UTC 24
Peak memory 209148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907887726 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_mubi.2907887726
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.3288498717
Short name T801
Test name
Test status
Simulation time 61142324 ps
CPU time 0.62 seconds
Started Oct 02 10:55:48 PM UTC 24
Finished Oct 02 10:55:50 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288498717 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.3288498717
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.449035252
Short name T808
Test name
Test status
Simulation time 291764822 ps
CPU time 1.18 seconds
Started Oct 02 10:55:49 PM UTC 24
Finished Oct 02 10:55:51 PM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449035252 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.449035252
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.3400239250
Short name T806
Test name
Test status
Simulation time 480572378 ps
CPU time 1.02 seconds
Started Oct 02 10:55:49 PM UTC 24
Finished Oct 02 10:55:51 PM UTC 24
Peak memory 209856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400239250 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.3400239250
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/44.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.1062863630
Short name T850
Test name
Test status
Simulation time 17767912 ps
CPU time 0.61 seconds
Started Oct 02 10:55:52 PM UTC 24
Finished Oct 02 10:56:21 PM UTC 24
Peak memory 208324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062863630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.1062863630
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/45.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.211070069
Short name T826
Test name
Test status
Simulation time 86857186 ps
CPU time 0.65 seconds
Started Oct 02 10:55:52 PM UTC 24
Finished Oct 02 10:56:21 PM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211070069 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disable_rom_integrity_check.211070069
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.2000695262
Short name T849
Test name
Test status
Simulation time 30199607 ps
CPU time 0.59 seconds
Started Oct 02 10:55:52 PM UTC 24
Finished Oct 02 10:56:21 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000695262 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst_malfunc.2000695262
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.3849295513
Short name T791
Test name
Test status
Simulation time 125627767 ps
CPU time 0.76 seconds
Started Oct 02 10:55:52 PM UTC 24
Finished Oct 02 10:56:21 PM UTC 24
Peak memory 220360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849295513 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.3849295513
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/45.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3738945141
Short name T854
Test name
Test status
Simulation time 2068571440 ps
CPU time 1.9 seconds
Started Oct 02 10:55:52 PM UTC 24
Finished Oct 02 10:56:22 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738945141 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3738945141
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2144712912
Short name T834
Test name
Test status
Simulation time 130343545 ps
CPU time 0.78 seconds
Started Oct 02 10:55:52 PM UTC 24
Finished Oct 02 10:56:05 PM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144712912 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2144712912
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.3402495825
Short name T831
Test name
Test status
Simulation time 2106247494 ps
CPU time 3.73 seconds
Started Oct 02 10:55:52 PM UTC 24
Finished Oct 02 10:55:58 PM UTC 24
Peak memory 211668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402495825 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.3402495825
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/45.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.2080410339
Short name T838
Test name
Test status
Simulation time 3230046345 ps
CPU time 3.42 seconds
Started Oct 02 10:55:52 PM UTC 24
Finished Oct 02 10:56:08 PM UTC 24
Peak memory 211552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2080410339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmg
r_stress_all_with_rand_reset.2080410339
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/45.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.1959326650
Short name T852
Test name
Test status
Simulation time 175554158 ps
CPU time 0.87 seconds
Started Oct 02 10:55:52 PM UTC 24
Finished Oct 02 10:56:21 PM UTC 24
Peak memory 209468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959326650 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.1959326650
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/45.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.1419210284
Short name T796
Test name
Test status
Simulation time 508724404 ps
CPU time 1.06 seconds
Started Oct 02 10:55:52 PM UTC 24
Finished Oct 02 10:56:21 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419210284 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.1419210284
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/45.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.3915736425
Short name T837
Test name
Test status
Simulation time 286412586 ps
CPU time 1.23 seconds
Started Oct 02 10:55:52 PM UTC 24
Finished Oct 02 10:56:06 PM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915736425 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_wakeup_race.3915736425
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.3833887355
Short name T844
Test name
Test status
Simulation time 2318994482 ps
CPU time 6.66 seconds
Started Oct 02 10:55:55 PM UTC 24
Finished Oct 02 10:56:16 PM UTC 24
Peak memory 211608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833887355 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.3833887355
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/46.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.3665452174
Short name T835
Test name
Test status
Simulation time 4962783858 ps
CPU time 6.03 seconds
Started Oct 02 10:55:55 PM UTC 24
Finished Oct 02 10:56:05 PM UTC 24
Peak memory 211752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3665452174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmg
r_stress_all_with_rand_reset.3665452174
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.2837304146
Short name T840
Test name
Test status
Simulation time 17296025 ps
CPU time 0.56 seconds
Started Oct 02 10:55:59 PM UTC 24
Finished Oct 02 10:56:10 PM UTC 24
Peak memory 208864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837304146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.2837304146
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/47.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.1528627644
Short name T842
Test name
Test status
Simulation time 83579500 ps
CPU time 0.59 seconds
Started Oct 02 10:56:08 PM UTC 24
Finished Oct 02 10:56:10 PM UTC 24
Peak memory 208620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528627644 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_disable_rom_integrity_check.1528627644
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.2658032275
Short name T851
Test name
Test status
Simulation time 29484511 ps
CPU time 0.57 seconds
Started Oct 02 10:56:06 PM UTC 24
Finished Oct 02 10:56:21 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658032275 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_malfunc.2658032275
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.3148709642
Short name T853
Test name
Test status
Simulation time 37135811 ps
CPU time 0.58 seconds
Started Oct 02 10:56:06 PM UTC 24
Finished Oct 02 10:56:21 PM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148709642 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.3148709642
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/47.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.3690235475
Short name T841
Test name
Test status
Simulation time 88632132 ps
CPU time 0.59 seconds
Started Oct 02 10:55:55 PM UTC 24
Finished Oct 02 10:56:10 PM UTC 24
Peak memory 208640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690235475 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.3690235475
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/47.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.3904438005
Short name T846
Test name
Test status
Simulation time 159647029 ps
CPU time 0.7 seconds
Started Oct 02 10:56:11 PM UTC 24
Finished Oct 02 10:56:20 PM UTC 24
Peak memory 220304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904438005 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.3904438005
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/47.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4065569571
Short name T860
Test name
Test status
Simulation time 1359083211 ps
CPU time 1.89 seconds
Started Oct 02 10:56:00 PM UTC 24
Finished Oct 02 10:56:26 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065569571 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4065569571
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1521402645
Short name T883
Test name
Test status
Simulation time 1074192265 ps
CPU time 1.8 seconds
Started Oct 02 10:56:00 PM UTC 24
Finished Oct 02 10:56:56 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521402645 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1521402645
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.286663522
Short name T839
Test name
Test status
Simulation time 40762700 ps
CPU time 0.57 seconds
Started Oct 02 10:55:55 PM UTC 24
Finished Oct 02 10:56:10 PM UTC 24
Peak memory 208788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286663522 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.286663522
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/47.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.1588252063
Short name T855
Test name
Test status
Simulation time 3559654783 ps
CPU time 3.64 seconds
Started Oct 02 10:56:11 PM UTC 24
Finished Oct 02 10:56:23 PM UTC 24
Peak memory 211544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588252063 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.1588252063
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/47.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.2548052897
Short name T862
Test name
Test status
Simulation time 5778161232 ps
CPU time 10.24 seconds
Started Oct 02 10:56:11 PM UTC 24
Finished Oct 02 10:56:30 PM UTC 24
Peak memory 211772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2548052897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmg
r_stress_all_with_rand_reset.2548052897
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/47.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.3118727218
Short name T843
Test name
Test status
Simulation time 96516266 ps
CPU time 0.74 seconds
Started Oct 02 10:55:59 PM UTC 24
Finished Oct 02 10:56:10 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118727218 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.3118727218
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/47.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.2294088909
Short name T880
Test name
Test status
Simulation time 64376763 ps
CPU time 0.73 seconds
Started Oct 02 10:56:22 PM UTC 24
Finished Oct 02 10:56:51 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294088909 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disable_rom_integrity_check.2294088909
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2460918581
Short name T875
Test name
Test status
Simulation time 29276815 ps
CPU time 0.63 seconds
Started Oct 02 10:56:22 PM UTC 24
Finished Oct 02 10:56:41 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460918581 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_malfunc.2460918581
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.1240390037
Short name T879
Test name
Test status
Simulation time 110430032 ps
CPU time 0.81 seconds
Started Oct 02 10:56:22 PM UTC 24
Finished Oct 02 10:56:51 PM UTC 24
Peak memory 208440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240390037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.1240390037
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.3142837711
Short name T873
Test name
Test status
Simulation time 55506432 ps
CPU time 0.6 seconds
Started Oct 02 10:56:22 PM UTC 24
Finished Oct 02 10:56:41 PM UTC 24
Peak memory 208620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142837711 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.3142837711
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.2877608433
Short name T856
Test name
Test status
Simulation time 51514218 ps
CPU time 0.54 seconds
Started Oct 02 10:56:22 PM UTC 24
Finished Oct 02 10:56:24 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877608433 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.2877608433
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.3722272915
Short name T847
Test name
Test status
Simulation time 80159721 ps
CPU time 0.69 seconds
Started Oct 02 10:56:18 PM UTC 24
Finished Oct 02 10:56:20 PM UTC 24
Peak memory 208988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722272915 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_wakeup_race.3722272915
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.2203957956
Short name T848
Test name
Test status
Simulation time 260930798 ps
CPU time 0.77 seconds
Started Oct 02 10:56:16 PM UTC 24
Finished Oct 02 10:56:21 PM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203957956 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.2203957956
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.716923882
Short name T858
Test name
Test status
Simulation time 111113288 ps
CPU time 0.84 seconds
Started Oct 02 10:56:22 PM UTC 24
Finished Oct 02 10:56:25 PM UTC 24
Peak memory 220724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716923882 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.716923882
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.3440270063
Short name T877
Test name
Test status
Simulation time 160952566 ps
CPU time 0.92 seconds
Started Oct 02 10:56:22 PM UTC 24
Finished Oct 02 10:56:41 PM UTC 24
Peak memory 209244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440270063 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_ctrl_config_regwen.3440270063
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.693867465
Short name T857
Test name
Test status
Simulation time 968653156 ps
CPU time 1.93 seconds
Started Oct 02 10:56:21 PM UTC 24
Finished Oct 02 10:56:24 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693867465 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.693867465
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3839578581
Short name T878
Test name
Test status
Simulation time 1074594859 ps
CPU time 1.85 seconds
Started Oct 02 10:56:22 PM UTC 24
Finished Oct 02 10:56:42 PM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839578581 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3839578581
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1436744932
Short name T876
Test name
Test status
Simulation time 50825298 ps
CPU time 0.84 seconds
Started Oct 02 10:56:22 PM UTC 24
Finished Oct 02 10:56:41 PM UTC 24
Peak memory 209148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436744932 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1436744932
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.1872362028
Short name T845
Test name
Test status
Simulation time 30098129 ps
CPU time 0.61 seconds
Started Oct 02 10:56:12 PM UTC 24
Finished Oct 02 10:56:20 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872362028 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.1872362028
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.539858669
Short name T886
Test name
Test status
Simulation time 801903525 ps
CPU time 1.25 seconds
Started Oct 02 10:56:24 PM UTC 24
Finished Oct 02 10:57:14 PM UTC 24
Peak memory 210656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539858669 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.539858669
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.792982126
Short name T859
Test name
Test status
Simulation time 495613767 ps
CPU time 0.86 seconds
Started Oct 02 10:56:21 PM UTC 24
Finished Oct 02 10:56:26 PM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792982126 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.792982126
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/48.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.2404051031
Short name T868
Test name
Test status
Simulation time 33313450 ps
CPU time 0.62 seconds
Started Oct 02 10:56:26 PM UTC 24
Finished Oct 02 10:56:40 PM UTC 24
Peak memory 208324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404051031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.2404051031
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.1556954686
Short name T884
Test name
Test status
Simulation time 58065107 ps
CPU time 0.64 seconds
Started Oct 02 10:56:31 PM UTC 24
Finished Oct 02 10:57:10 PM UTC 24
Peak memory 208648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556954686 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_disable_rom_integrity_check.1556954686
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.2889023076
Short name T866
Test name
Test status
Simulation time 31041499 ps
CPU time 0.59 seconds
Started Oct 02 10:56:26 PM UTC 24
Finished Oct 02 10:56:40 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889023076 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_malfunc.2889023076
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.819420706
Short name T872
Test name
Test status
Simulation time 565979305 ps
CPU time 0.76 seconds
Started Oct 02 10:56:29 PM UTC 24
Finished Oct 02 10:56:41 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819420706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.819420706
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.1551546481
Short name T882
Test name
Test status
Simulation time 50280740 ps
CPU time 0.62 seconds
Started Oct 02 10:56:30 PM UTC 24
Finished Oct 02 10:56:55 PM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551546481 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.1551546481
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.306810649
Short name T865
Test name
Test status
Simulation time 44104388 ps
CPU time 0.65 seconds
Started Oct 02 10:56:26 PM UTC 24
Finished Oct 02 10:56:40 PM UTC 24
Peak memory 208980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306810649 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_wakeup_race.306810649
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.2528857678
Short name T869
Test name
Test status
Simulation time 66666466 ps
CPU time 0.82 seconds
Started Oct 02 10:56:26 PM UTC 24
Finished Oct 02 10:56:40 PM UTC 24
Peak memory 210012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528857678 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.2528857678
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.774656634
Short name T881
Test name
Test status
Simulation time 118485831 ps
CPU time 0.79 seconds
Started Oct 02 10:56:32 PM UTC 24
Finished Oct 02 10:56:51 PM UTC 24
Peak memory 220368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774656634 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.774656634
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4054826136
Short name T861
Test name
Test status
Simulation time 1069623369 ps
CPU time 1.78 seconds
Started Oct 02 10:56:26 PM UTC 24
Finished Oct 02 10:56:28 PM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054826136 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4054826136
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2837351511
Short name T863
Test name
Test status
Simulation time 1064554520 ps
CPU time 1.87 seconds
Started Oct 02 10:56:26 PM UTC 24
Finished Oct 02 10:56:36 PM UTC 24
Peak memory 210564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837351511 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2837351511
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.2018204949
Short name T871
Test name
Test status
Simulation time 180812459 ps
CPU time 0.8 seconds
Started Oct 02 10:56:26 PM UTC 24
Finished Oct 02 10:56:41 PM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018204949 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_mubi.2018204949
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.947947215
Short name T885
Test name
Test status
Simulation time 35642212 ps
CPU time 0.58 seconds
Started Oct 02 10:56:24 PM UTC 24
Finished Oct 02 10:57:13 PM UTC 24
Peak memory 208860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947947215 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.947947215
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.2683487053
Short name T864
Test name
Test status
Simulation time 1109960782 ps
CPU time 4.32 seconds
Started Oct 02 10:56:32 PM UTC 24
Finished Oct 02 10:56:39 PM UTC 24
Peak memory 211664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683487053 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.2683487053
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.133957847
Short name T874
Test name
Test status
Simulation time 2076573872 ps
CPU time 6.37 seconds
Started Oct 02 10:56:32 PM UTC 24
Finished Oct 02 10:56:41 PM UTC 24
Peak memory 211636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=133957847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr
_stress_all_with_rand_reset.133957847
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.4158753828
Short name T870
Test name
Test status
Simulation time 174167382 ps
CPU time 0.89 seconds
Started Oct 02 10:56:26 PM UTC 24
Finished Oct 02 10:56:40 PM UTC 24
Peak memory 209468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158753828 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.4158753828
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.1179649642
Short name T867
Test name
Test status
Simulation time 38051475 ps
CPU time 0.64 seconds
Started Oct 02 10:56:26 PM UTC 24
Finished Oct 02 10:56:40 PM UTC 24
Peak memory 210540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179649642 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.1179649642
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/49.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.2376045265
Short name T102
Test name
Test status
Simulation time 100168253 ps
CPU time 1.01 seconds
Started Oct 02 10:53:16 PM UTC 24
Finished Oct 02 10:53:19 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376045265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.2376045265
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.3566026922
Short name T154
Test name
Test status
Simulation time 62538998 ps
CPU time 1.07 seconds
Started Oct 02 10:53:18 PM UTC 24
Finished Oct 02 10:53:20 PM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566026922 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disable_rom_integrity_check.3566026922
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1517466869
Short name T96
Test name
Test status
Simulation time 32659732 ps
CPU time 0.84 seconds
Started Oct 02 10:53:18 PM UTC 24
Finished Oct 02 10:53:20 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517466869 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_malfunc.1517466869
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.3846539358
Short name T147
Test name
Test status
Simulation time 398762729 ps
CPU time 1.12 seconds
Started Oct 02 10:53:18 PM UTC 24
Finished Oct 02 10:53:20 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846539358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.3846539358
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.736649962
Short name T204
Test name
Test status
Simulation time 56479723 ps
CPU time 1.02 seconds
Started Oct 02 10:53:18 PM UTC 24
Finished Oct 02 10:53:20 PM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736649962 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.736649962
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.312973634
Short name T95
Test name
Test status
Simulation time 45533262 ps
CPU time 0.75 seconds
Started Oct 02 10:53:18 PM UTC 24
Finished Oct 02 10:53:20 PM UTC 24
Peak memory 208848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312973634 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.312973634
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.217684629
Short name T99
Test name
Test status
Simulation time 111725960 ps
CPU time 0.91 seconds
Started Oct 02 10:53:16 PM UTC 24
Finished Oct 02 10:53:18 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217684629 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wakeup_race.217684629
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.1461887181
Short name T103
Test name
Test status
Simulation time 169751930 ps
CPU time 1.21 seconds
Started Oct 02 10:53:16 PM UTC 24
Finished Oct 02 10:53:19 PM UTC 24
Peak memory 209468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461887181 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.1461887181
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.3496482992
Short name T207
Test name
Test status
Simulation time 110486721 ps
CPU time 1.49 seconds
Started Oct 02 10:53:18 PM UTC 24
Finished Oct 02 10:53:21 PM UTC 24
Peak memory 220308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496482992 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.3496482992
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.2561777776
Short name T92
Test name
Test status
Simulation time 49348881 ps
CPU time 0.83 seconds
Started Oct 02 10:53:18 PM UTC 24
Finished Oct 02 10:53:20 PM UTC 24
Peak memory 208744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561777776 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_ctrl_config_regwen.2561777776
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.810920767
Short name T91
Test name
Test status
Simulation time 1168233155 ps
CPU time 2.37 seconds
Started Oct 02 10:53:16 PM UTC 24
Finished Oct 02 10:53:20 PM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810920767 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig
_mubi.810920767
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2722935510
Short name T208
Test name
Test status
Simulation time 802685529 ps
CPU time 3.63 seconds
Started Oct 02 10:53:17 PM UTC 24
Finished Oct 02 10:53:21 PM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722935510 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.2722935510
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2132019062
Short name T205
Test name
Test status
Simulation time 104224207 ps
CPU time 1.18 seconds
Started Oct 02 10:53:18 PM UTC 24
Finished Oct 02 10:53:20 PM UTC 24
Peak memory 209100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132019062 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_mubi.2132019062
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.675271289
Short name T81
Test name
Test status
Simulation time 29967919 ps
CPU time 0.88 seconds
Started Oct 02 10:53:15 PM UTC 24
Finished Oct 02 10:53:17 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675271289 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0
2/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.675271289
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.2530551777
Short name T241
Test name
Test status
Simulation time 1955967434 ps
CPU time 7.09 seconds
Started Oct 02 10:53:18 PM UTC 24
Finished Oct 02 10:53:27 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530551777 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.2530551777
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.2442347855
Short name T127
Test name
Test status
Simulation time 3068366958 ps
CPU time 4.36 seconds
Started Oct 02 10:53:18 PM UTC 24
Finished Oct 02 10:53:24 PM UTC 24
Peak memory 211760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2442347855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr
_stress_all_with_rand_reset.2442347855
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.1996572546
Short name T101
Test name
Test status
Simulation time 262745288 ps
CPU time 1.1 seconds
Started Oct 02 10:53:16 PM UTC 24
Finished Oct 02 10:53:18 PM UTC 24
Peak memory 209852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996572546 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.1996572546
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.2748061709
Short name T100
Test name
Test status
Simulation time 78708741 ps
CPU time 0.95 seconds
Started Oct 02 10:53:16 PM UTC 24
Finished Oct 02 10:53:18 PM UTC 24
Peak memory 208740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748061709 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.2748061709
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/5.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.1023506229
Short name T209
Test name
Test status
Simulation time 58201470 ps
CPU time 0.75 seconds
Started Oct 02 10:53:20 PM UTC 24
Finished Oct 02 10:53:22 PM UTC 24
Peak memory 208740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023506229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.1023506229
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.1829486467
Short name T180
Test name
Test status
Simulation time 71462794 ps
CPU time 0.9 seconds
Started Oct 02 10:53:21 PM UTC 24
Finished Oct 02 10:53:23 PM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829486467 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disable_rom_integrity_check.1829486467
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.3148880042
Short name T213
Test name
Test status
Simulation time 30957008 ps
CPU time 0.74 seconds
Started Oct 02 10:53:20 PM UTC 24
Finished Oct 02 10:53:22 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148880042 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_malfunc.3148880042
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.1940805326
Short name T148
Test name
Test status
Simulation time 365109789 ps
CPU time 1.17 seconds
Started Oct 02 10:53:21 PM UTC 24
Finished Oct 02 10:53:24 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940805326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.1940805326
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.3810570849
Short name T218
Test name
Test status
Simulation time 48241649 ps
CPU time 0.64 seconds
Started Oct 02 10:53:21 PM UTC 24
Finished Oct 02 10:53:23 PM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810570849 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3810570849
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.478211975
Short name T212
Test name
Test status
Simulation time 61971199 ps
CPU time 0.71 seconds
Started Oct 02 10:53:20 PM UTC 24
Finished Oct 02 10:53:22 PM UTC 24
Peak memory 208860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478211975 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.478211975
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.2621925110
Short name T214
Test name
Test status
Simulation time 232684718 ps
CPU time 1.19 seconds
Started Oct 02 10:53:20 PM UTC 24
Finished Oct 02 10:53:22 PM UTC 24
Peak memory 209532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621925110 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wakeup_race.2621925110
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.2460493706
Short name T211
Test name
Test status
Simulation time 49952702 ps
CPU time 0.88 seconds
Started Oct 02 10:53:20 PM UTC 24
Finished Oct 02 10:53:22 PM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460493706 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.2460493706
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.2651414402
Short name T224
Test name
Test status
Simulation time 114217041 ps
CPU time 1.21 seconds
Started Oct 02 10:53:21 PM UTC 24
Finished Oct 02 10:53:24 PM UTC 24
Peak memory 220544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651414402 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.2651414402
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1056287761
Short name T217
Test name
Test status
Simulation time 157222160 ps
CPU time 1.04 seconds
Started Oct 02 10:53:20 PM UTC 24
Finished Oct 02 10:53:22 PM UTC 24
Peak memory 208744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056287761 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_ctrl_config_regwen.1056287761
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.779842498
Short name T228
Test name
Test status
Simulation time 825214410 ps
CPU time 3.03 seconds
Started Oct 02 10:53:20 PM UTC 24
Finished Oct 02 10:53:24 PM UTC 24
Peak memory 211440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779842498 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig
_mubi.779842498
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3236149494
Short name T230
Test name
Test status
Simulation time 864804166 ps
CPU time 3.31 seconds
Started Oct 02 10:53:20 PM UTC 24
Finished Oct 02 10:53:24 PM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236149494 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.3236149494
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2323772515
Short name T215
Test name
Test status
Simulation time 140844391 ps
CPU time 0.95 seconds
Started Oct 02 10:53:20 PM UTC 24
Finished Oct 02 10:53:22 PM UTC 24
Peak memory 209212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323772515 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2323772515
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.2350834379
Short name T206
Test name
Test status
Simulation time 93190344 ps
CPU time 0.88 seconds
Started Oct 02 10:53:18 PM UTC 24
Finished Oct 02 10:53:21 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350834379 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.2350834379
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.1672595928
Short name T223
Test name
Test status
Simulation time 58133142 ps
CPU time 1.05 seconds
Started Oct 02 10:53:22 PM UTC 24
Finished Oct 02 10:53:24 PM UTC 24
Peak memory 208860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672595928 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.1672595928
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.1846339686
Short name T210
Test name
Test status
Simulation time 150274981 ps
CPU time 0.82 seconds
Started Oct 02 10:53:20 PM UTC 24
Finished Oct 02 10:53:22 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846339686 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.1846339686
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.2600415840
Short name T216
Test name
Test status
Simulation time 366613255 ps
CPU time 1.25 seconds
Started Oct 02 10:53:20 PM UTC 24
Finished Oct 02 10:53:22 PM UTC 24
Peak memory 209616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600415840 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.2600415840
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/6.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.1238229203
Short name T221
Test name
Test status
Simulation time 31684862 ps
CPU time 0.74 seconds
Started Oct 02 10:53:22 PM UTC 24
Finished Oct 02 10:53:24 PM UTC 24
Peak memory 208320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238229203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.1238229203
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.2383239834
Short name T173
Test name
Test status
Simulation time 72946045 ps
CPU time 0.83 seconds
Started Oct 02 10:53:23 PM UTC 24
Finished Oct 02 10:53:25 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383239834 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disable_rom_integrity_check.2383239834
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2845064672
Short name T231
Test name
Test status
Simulation time 30291425 ps
CPU time 0.94 seconds
Started Oct 02 10:53:23 PM UTC 24
Finished Oct 02 10:53:25 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845064672 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_malfunc.2845064672
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.3175243664
Short name T237
Test name
Test status
Simulation time 416744897 ps
CPU time 1.19 seconds
Started Oct 02 10:53:23 PM UTC 24
Finished Oct 02 10:53:26 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175243664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.3175243664
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.2784272722
Short name T234
Test name
Test status
Simulation time 65832087 ps
CPU time 0.91 seconds
Started Oct 02 10:53:23 PM UTC 24
Finished Oct 02 10:53:25 PM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784272722 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.2784272722
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.4110956123
Short name T232
Test name
Test status
Simulation time 58734712 ps
CPU time 0.84 seconds
Started Oct 02 10:53:23 PM UTC 24
Finished Oct 02 10:53:25 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110956123 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.4110956123
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.462181156
Short name T225
Test name
Test status
Simulation time 218270812 ps
CPU time 1.04 seconds
Started Oct 02 10:53:22 PM UTC 24
Finished Oct 02 10:53:24 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462181156 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wakeup_race.462181156
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.3345009830
Short name T227
Test name
Test status
Simulation time 183606114 ps
CPU time 1.2 seconds
Started Oct 02 10:53:22 PM UTC 24
Finished Oct 02 10:53:24 PM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345009830 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.3345009830
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.3450253793
Short name T236
Test name
Test status
Simulation time 149792072 ps
CPU time 0.87 seconds
Started Oct 02 10:53:23 PM UTC 24
Finished Oct 02 10:53:26 PM UTC 24
Peak memory 220664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450253793 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.3450253793
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.3094361869
Short name T235
Test name
Test status
Simulation time 339410254 ps
CPU time 0.98 seconds
Started Oct 02 10:53:23 PM UTC 24
Finished Oct 02 10:53:26 PM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094361869 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_ctrl_config_regwen.3094361869
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1317396290
Short name T247
Test name
Test status
Simulation time 890416229 ps
CPU time 3.32 seconds
Started Oct 02 10:53:23 PM UTC 24
Finished Oct 02 10:53:28 PM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317396290 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.1317396290
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2700235387
Short name T246
Test name
Test status
Simulation time 823789944 ps
CPU time 3.12 seconds
Started Oct 02 10:53:23 PM UTC 24
Finished Oct 02 10:53:28 PM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700235387 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.2700235387
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3291170306
Short name T233
Test name
Test status
Simulation time 79629414 ps
CPU time 1.08 seconds
Started Oct 02 10:53:23 PM UTC 24
Finished Oct 02 10:53:25 PM UTC 24
Peak memory 209956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291170306 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3291170306
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.3640443686
Short name T222
Test name
Test status
Simulation time 28208878 ps
CPU time 0.92 seconds
Started Oct 02 10:53:22 PM UTC 24
Finished Oct 02 10:53:24 PM UTC 24
Peak memory 208316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640443686 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.3640443686
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.2599796680
Short name T253
Test name
Test status
Simulation time 1651950550 ps
CPU time 2.99 seconds
Started Oct 02 10:53:25 PM UTC 24
Finished Oct 02 10:53:29 PM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599796680 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.2599796680
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.2162786635
Short name T49
Test name
Test status
Simulation time 3118437467 ps
CPU time 9.25 seconds
Started Oct 02 10:53:25 PM UTC 24
Finished Oct 02 10:53:35 PM UTC 24
Peak memory 211684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2162786635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr
_stress_all_with_rand_reset.2162786635
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.1059489171
Short name T226
Test name
Test status
Simulation time 196743578 ps
CPU time 0.93 seconds
Started Oct 02 10:53:22 PM UTC 24
Finished Oct 02 10:53:24 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059489171 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.1059489171
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2625437011
Short name T229
Test name
Test status
Simulation time 323800661 ps
CPU time 1.11 seconds
Started Oct 02 10:53:22 PM UTC 24
Finished Oct 02 10:53:24 PM UTC 24
Peak memory 210180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625437011 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.2625437011
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/7.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.366434020
Short name T94
Test name
Test status
Simulation time 42542740 ps
CPU time 1.06 seconds
Started Oct 02 10:53:25 PM UTC 24
Finished Oct 02 10:53:27 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366434020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.366434020
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.106739796
Short name T249
Test name
Test status
Simulation time 73624189 ps
CPU time 0.94 seconds
Started Oct 02 10:53:27 PM UTC 24
Finished Oct 02 10:53:28 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106739796 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disable_rom_integrity_check.106739796
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.4145313821
Short name T104
Test name
Test status
Simulation time 30293617 ps
CPU time 0.85 seconds
Started Oct 02 10:53:25 PM UTC 24
Finished Oct 02 10:53:27 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145313821 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_malfunc.4145313821
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2205546640
Short name T248
Test name
Test status
Simulation time 109628446 ps
CPU time 0.99 seconds
Started Oct 02 10:53:26 PM UTC 24
Finished Oct 02 10:53:28 PM UTC 24
Peak memory 208440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205546640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.2205546640
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.1216879150
Short name T203
Test name
Test status
Simulation time 40056274 ps
CPU time 0.76 seconds
Started Oct 02 10:53:26 PM UTC 24
Finished Oct 02 10:53:28 PM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216879150 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.1216879150
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.27229280
Short name T219
Test name
Test status
Simulation time 78287793 ps
CPU time 0.81 seconds
Started Oct 02 10:53:25 PM UTC 24
Finished Oct 02 10:53:27 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27229280 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.27229280
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.3096479790
Short name T245
Test name
Test status
Simulation time 250267042 ps
CPU time 1.35 seconds
Started Oct 02 10:53:25 PM UTC 24
Finished Oct 02 10:53:27 PM UTC 24
Peak memory 209856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096479790 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wakeup_race.3096479790
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.1818038883
Short name T199
Test name
Test status
Simulation time 104462386 ps
CPU time 1.18 seconds
Started Oct 02 10:53:25 PM UTC 24
Finished Oct 02 10:53:27 PM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818038883 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.1818038883
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.3671017366
Short name T242
Test name
Test status
Simulation time 109737451 ps
CPU time 1.24 seconds
Started Oct 02 10:53:27 PM UTC 24
Finished Oct 02 10:53:29 PM UTC 24
Peak memory 220304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671017366 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.3671017366
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.62212139
Short name T244
Test name
Test status
Simulation time 141278757 ps
CPU time 1.01 seconds
Started Oct 02 10:53:25 PM UTC 24
Finished Oct 02 10:53:27 PM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62212139 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_ctrl_config_regwen.62212139
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1991471016
Short name T250
Test name
Test status
Simulation time 1181673037 ps
CPU time 2.35 seconds
Started Oct 02 10:53:25 PM UTC 24
Finished Oct 02 10:53:29 PM UTC 24
Peak memory 211508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991471016 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.1991471016
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.823789706
Short name T252
Test name
Test status
Simulation time 935683306 ps
CPU time 2.65 seconds
Started Oct 02 10:53:25 PM UTC 24
Finished Oct 02 10:53:29 PM UTC 24
Peak memory 211464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823789706 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_inters
ig_mubi.823789706
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.503604562
Short name T243
Test name
Test status
Simulation time 154568753 ps
CPU time 1 seconds
Started Oct 02 10:53:25 PM UTC 24
Finished Oct 02 10:53:27 PM UTC 24
Peak memory 209208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503604562 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_mubi.503604562
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.1610228914
Short name T238
Test name
Test status
Simulation time 33039828 ps
CPU time 0.68 seconds
Started Oct 02 10:53:25 PM UTC 24
Finished Oct 02 10:53:27 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610228914 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.1610228914
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1495096862
Short name T254
Test name
Test status
Simulation time 440142025 ps
CPU time 1.38 seconds
Started Oct 02 10:53:27 PM UTC 24
Finished Oct 02 10:53:29 PM UTC 24
Peak memory 210588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495096862 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.1495096862
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.2807295585
Short name T51
Test name
Test status
Simulation time 6742103391 ps
CPU time 8.95 seconds
Started Oct 02 10:53:27 PM UTC 24
Finished Oct 02 10:53:37 PM UTC 24
Peak memory 211816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2807295585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr
_stress_all_with_rand_reset.2807295585
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.685686459
Short name T240
Test name
Test status
Simulation time 51998606 ps
CPU time 0.89 seconds
Started Oct 02 10:53:25 PM UTC 24
Finished Oct 02 10:53:27 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685686459 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.685686459
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.2628606912
Short name T90
Test name
Test status
Simulation time 141364812 ps
CPU time 0.9 seconds
Started Oct 02 10:53:25 PM UTC 24
Finished Oct 02 10:53:27 PM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628606912 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.2628606912
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/8.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.284243068
Short name T256
Test name
Test status
Simulation time 173492483 ps
CPU time 0.99 seconds
Started Oct 02 10:53:28 PM UTC 24
Finished Oct 02 10:53:30 PM UTC 24
Peak memory 210004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284243068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.284243068
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.1427527068
Short name T265
Test name
Test status
Simulation time 47549333 ps
CPU time 0.98 seconds
Started Oct 02 10:53:29 PM UTC 24
Finished Oct 02 10:53:31 PM UTC 24
Peak memory 209036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427527068 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disable_rom_integrity_check.1427527068
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3316923843
Short name T255
Test name
Test status
Simulation time 31785351 ps
CPU time 0.73 seconds
Started Oct 02 10:53:28 PM UTC 24
Finished Oct 02 10:53:30 PM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316923843 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_malfunc.3316923843
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.656032986
Short name T266
Test name
Test status
Simulation time 107465635 ps
CPU time 1.06 seconds
Started Oct 02 10:53:29 PM UTC 24
Finished Oct 02 10:53:31 PM UTC 24
Peak memory 208444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656032986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.656032986
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.2693601559
Short name T260
Test name
Test status
Simulation time 23145405 ps
CPU time 0.71 seconds
Started Oct 02 10:53:29 PM UTC 24
Finished Oct 02 10:53:30 PM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693601559 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.2693601559
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.3445235032
Short name T259
Test name
Test status
Simulation time 27231163 ps
CPU time 0.73 seconds
Started Oct 02 10:53:29 PM UTC 24
Finished Oct 02 10:53:30 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445235032 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.3445235032
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.1360385453
Short name T251
Test name
Test status
Simulation time 34011329 ps
CPU time 0.79 seconds
Started Oct 02 10:53:27 PM UTC 24
Finished Oct 02 10:53:29 PM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360385453 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wakeup_race.1360385453
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2964169434
Short name T202
Test name
Test status
Simulation time 295207689 ps
CPU time 1.13 seconds
Started Oct 02 10:53:27 PM UTC 24
Finished Oct 02 10:53:29 PM UTC 24
Peak memory 208640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964169434 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.2964169434
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.1843278146
Short name T267
Test name
Test status
Simulation time 106446368 ps
CPU time 1.05 seconds
Started Oct 02 10:53:29 PM UTC 24
Finished Oct 02 10:53:31 PM UTC 24
Peak memory 220292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843278146 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.1843278146
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3052051572
Short name T263
Test name
Test status
Simulation time 175730394 ps
CPU time 1.07 seconds
Started Oct 02 10:53:28 PM UTC 24
Finished Oct 02 10:53:31 PM UTC 24
Peak memory 208744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052051572 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_ctrl_config_regwen.3052051572
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1400769429
Short name T268
Test name
Test status
Simulation time 1708894440 ps
CPU time 1.71 seconds
Started Oct 02 10:53:28 PM UTC 24
Finished Oct 02 10:53:31 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400769429 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.1400769429
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1322744688
Short name T279
Test name
Test status
Simulation time 986575795 ps
CPU time 3.43 seconds
Started Oct 02 10:53:28 PM UTC 24
Finished Oct 02 10:53:33 PM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322744688 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.1322744688
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1991785940
Short name T261
Test name
Test status
Simulation time 100512724 ps
CPU time 1.07 seconds
Started Oct 02 10:53:28 PM UTC 24
Finished Oct 02 10:53:30 PM UTC 24
Peak memory 209572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991785940 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1991785940
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.4218002265
Short name T239
Test name
Test status
Simulation time 76679883 ps
CPU time 0.81 seconds
Started Oct 02 10:53:27 PM UTC 24
Finished Oct 02 10:53:29 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218002265 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.4218002265
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.2010750146
Short name T264
Test name
Test status
Simulation time 3307368140 ps
CPU time 7.16 seconds
Started Oct 02 10:53:30 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 211668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010750146 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.2010750146
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1953701840
Short name T129
Test name
Test status
Simulation time 14631652370 ps
CPU time 7.72 seconds
Started Oct 02 10:53:29 PM UTC 24
Finished Oct 02 10:53:38 PM UTC 24
Peak memory 211564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1953701840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr
_stress_all_with_rand_reset.1953701840
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.2910891552
Short name T220
Test name
Test status
Simulation time 360225586 ps
CPU time 0.83 seconds
Started Oct 02 10:53:28 PM UTC 24
Finished Oct 02 10:53:30 PM UTC 24
Peak memory 208916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910891552 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.2910891552
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.4056208026
Short name T262
Test name
Test status
Simulation time 236398522 ps
CPU time 1.22 seconds
Started Oct 02 10:53:28 PM UTC 24
Finished Oct 02 10:53:30 PM UTC 24
Peak memory 209856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056208026 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_02/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.4056208026
Directory /workspaces/repo/scratch/os_regression_2024_10_02/pwrmgr-sim-vcs/9.pwrmgr_wakeup_reset/latest
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