| T329 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.2950186900 |
|
|
Oct 15 12:53:55 PM UTC 24 |
Oct 15 12:53:57 PM UTC 24 |
25996781 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.1667896232 |
|
|
Oct 15 12:53:55 PM UTC 24 |
Oct 15 12:53:57 PM UTC 24 |
368073780 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all.3442779883 |
|
|
Oct 15 12:53:54 PM UTC 24 |
Oct 15 12:53:57 PM UTC 24 |
353137038 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.1921197810 |
|
|
Oct 15 12:53:55 PM UTC 24 |
Oct 15 12:53:57 PM UTC 24 |
136297428 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.4003985700 |
|
|
Oct 15 12:53:55 PM UTC 24 |
Oct 15 12:53:57 PM UTC 24 |
55130320 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.1716508999 |
|
|
Oct 15 12:53:55 PM UTC 24 |
Oct 15 12:53:58 PM UTC 24 |
251836832 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_global_esc.4049638220 |
|
|
Oct 15 12:53:56 PM UTC 24 |
Oct 15 12:53:58 PM UTC 24 |
68097923 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.2489304996 |
|
|
Oct 15 12:53:56 PM UTC 24 |
Oct 15 12:53:58 PM UTC 24 |
29364154 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3554070759 |
|
|
Oct 15 12:53:55 PM UTC 24 |
Oct 15 12:53:58 PM UTC 24 |
795295788 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.3063159503 |
|
|
Oct 15 12:53:56 PM UTC 24 |
Oct 15 12:53:58 PM UTC 24 |
50987634 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.762953659 |
|
|
Oct 15 12:53:56 PM UTC 24 |
Oct 15 12:53:58 PM UTC 24 |
174881512 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2744282631 |
|
|
Oct 15 12:53:55 PM UTC 24 |
Oct 15 12:53:58 PM UTC 24 |
1215316087 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.2290565872 |
|
|
Oct 15 12:53:56 PM UTC 24 |
Oct 15 12:53:59 PM UTC 24 |
383256980 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_smoke.2479367704 |
|
|
Oct 15 12:53:58 PM UTC 24 |
Oct 15 12:54:00 PM UTC 24 |
33735539 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_disable_rom_integrity_check.669611678 |
|
|
Oct 15 12:53:58 PM UTC 24 |
Oct 15 12:54:00 PM UTC 24 |
79408323 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset.4278986668 |
|
|
Oct 15 12:53:58 PM UTC 24 |
Oct 15 12:54:00 PM UTC 24 |
62693034 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_invalid.293200853 |
|
|
Oct 15 12:53:58 PM UTC 24 |
Oct 15 12:54:01 PM UTC 24 |
94599588 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset_invalid.3213101133 |
|
|
Oct 15 12:53:58 PM UTC 24 |
Oct 15 12:54:01 PM UTC 24 |
109492436 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.2423858494 |
|
|
Oct 15 12:53:59 PM UTC 24 |
Oct 15 12:54:02 PM UTC 24 |
311829101 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_wakeup_race.2181758115 |
|
|
Oct 15 12:53:58 PM UTC 24 |
Oct 15 12:54:02 PM UTC 24 |
340390909 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup.2338452349 |
|
|
Oct 15 12:53:58 PM UTC 24 |
Oct 15 12:54:02 PM UTC 24 |
277643404 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.3319429725 |
|
|
Oct 15 12:54:00 PM UTC 24 |
Oct 15 12:54:02 PM UTC 24 |
36211915 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.2392723321 |
|
|
Oct 15 12:54:00 PM UTC 24 |
Oct 15 12:54:02 PM UTC 24 |
37616987 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_global_esc.2990009756 |
|
|
Oct 15 12:54:00 PM UTC 24 |
Oct 15 12:54:02 PM UTC 24 |
29453503 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3216733255 |
|
|
Oct 15 12:54:00 PM UTC 24 |
Oct 15 12:54:02 PM UTC 24 |
145817429 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_escalation_timeout.1943876469 |
|
|
Oct 15 12:54:00 PM UTC 24 |
Oct 15 12:54:02 PM UTC 24 |
110094350 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.983569347 |
|
|
Oct 15 12:54:00 PM UTC 24 |
Oct 15 12:54:03 PM UTC 24 |
353486203 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.3669640733 |
|
|
Oct 15 12:54:01 PM UTC 24 |
Oct 15 12:54:03 PM UTC 24 |
38688113 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.2568933701 |
|
|
Oct 15 12:54:01 PM UTC 24 |
Oct 15 12:54:04 PM UTC 24 |
94721684 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_invalid.2667353643 |
|
|
Oct 15 12:54:01 PM UTC 24 |
Oct 15 12:54:04 PM UTC 24 |
75225860 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.1914590814 |
|
|
Oct 15 12:54:01 PM UTC 24 |
Oct 15 12:54:04 PM UTC 24 |
103235665 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3698096446 |
|
|
Oct 15 12:54:00 PM UTC 24 |
Oct 15 12:54:04 PM UTC 24 |
947439396 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.57481330 |
|
|
Oct 15 12:54:00 PM UTC 24 |
Oct 15 12:54:04 PM UTC 24 |
1211907975 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all.1905813242 |
|
|
Oct 15 12:53:58 PM UTC 24 |
Oct 15 12:54:05 PM UTC 24 |
1503224646 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.4186716545 |
|
|
Oct 15 12:54:03 PM UTC 24 |
Oct 15 12:54:05 PM UTC 24 |
39550494 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup.790424015 |
|
|
Oct 15 12:54:03 PM UTC 24 |
Oct 15 12:54:05 PM UTC 24 |
71646423 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup_reset.2620277740 |
|
|
Oct 15 12:54:03 PM UTC 24 |
Oct 15 12:54:06 PM UTC 24 |
119767436 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_wakeup_race.2876132303 |
|
|
Oct 15 12:54:03 PM UTC 24 |
Oct 15 12:54:06 PM UTC 24 |
131703770 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset.2287903553 |
|
|
Oct 15 12:54:03 PM UTC 24 |
Oct 15 12:54:06 PM UTC 24 |
88213962 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.3379063265 |
|
|
Oct 15 12:53:49 PM UTC 24 |
Oct 15 12:54:06 PM UTC 24 |
3545686824 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all.1748480229 |
|
|
Oct 15 12:54:03 PM UTC 24 |
Oct 15 12:54:06 PM UTC 24 |
935220596 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all_with_rand_reset.1638013223 |
|
|
Oct 15 12:53:53 PM UTC 24 |
Oct 15 12:54:07 PM UTC 24 |
3374171971 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_aborted_low_power.999056961 |
|
|
Oct 15 12:54:04 PM UTC 24 |
Oct 15 12:54:07 PM UTC 24 |
29784130 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2787810891 |
|
|
Oct 15 12:54:04 PM UTC 24 |
Oct 15 12:54:07 PM UTC 24 |
52508990 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.1351760537 |
|
|
Oct 15 12:54:04 PM UTC 24 |
Oct 15 12:54:07 PM UTC 24 |
29413086 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_global_esc.1563252614 |
|
|
Oct 15 12:54:06 PM UTC 24 |
Oct 15 12:54:08 PM UTC 24 |
57670010 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2556547863 |
|
|
Oct 15 12:54:04 PM UTC 24 |
Oct 15 12:54:08 PM UTC 24 |
1050747782 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.2881177549 |
|
|
Oct 15 12:54:06 PM UTC 24 |
Oct 15 12:54:08 PM UTC 24 |
297436118 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.12745516 |
|
|
Oct 15 12:54:06 PM UTC 24 |
Oct 15 12:54:08 PM UTC 24 |
93940256 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1764327189 |
|
|
Oct 15 12:54:04 PM UTC 24 |
Oct 15 12:54:08 PM UTC 24 |
1069742871 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.2751848185 |
|
|
Oct 15 12:54:06 PM UTC 24 |
Oct 15 12:54:08 PM UTC 24 |
58094368 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.519610573 |
|
|
Oct 15 12:54:06 PM UTC 24 |
Oct 15 12:54:08 PM UTC 24 |
407622227 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.1298636720 |
|
|
Oct 15 12:53:58 PM UTC 24 |
Oct 15 12:54:08 PM UTC 24 |
4067118571 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.373819558 |
|
|
Oct 15 12:54:07 PM UTC 24 |
Oct 15 12:54:10 PM UTC 24 |
89835501 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.2808087168 |
|
|
Oct 15 12:54:07 PM UTC 24 |
Oct 15 12:54:10 PM UTC 24 |
40444960 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_aborted_low_power.87686260 |
|
|
Oct 15 12:54:08 PM UTC 24 |
Oct 15 12:54:10 PM UTC 24 |
30606420 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.1996886494 |
|
|
Oct 15 12:54:07 PM UTC 24 |
Oct 15 12:54:10 PM UTC 24 |
278760794 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_wakeup_race.1044877853 |
|
|
Oct 15 12:54:07 PM UTC 24 |
Oct 15 12:54:10 PM UTC 24 |
201551844 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset.3903173878 |
|
|
Oct 15 12:54:24 PM UTC 24 |
Oct 15 12:54:26 PM UTC 24 |
137776766 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.208340126 |
|
|
Oct 15 12:54:09 PM UTC 24 |
Oct 15 12:54:11 PM UTC 24 |
32441359 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_glitch.2663044869 |
|
|
Oct 15 12:54:09 PM UTC 24 |
Oct 15 12:54:11 PM UTC 24 |
70718938 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2261022252 |
|
|
Oct 15 12:54:09 PM UTC 24 |
Oct 15 12:54:11 PM UTC 24 |
54375259 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_global_esc.2071471626 |
|
|
Oct 15 12:54:09 PM UTC 24 |
Oct 15 12:54:11 PM UTC 24 |
101436473 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup_reset.1832705602 |
|
|
Oct 15 12:54:08 PM UTC 24 |
Oct 15 12:54:11 PM UTC 24 |
299294162 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.4133362808 |
|
|
Oct 15 12:54:09 PM UTC 24 |
Oct 15 12:54:11 PM UTC 24 |
75573782 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_invalid.1680132971 |
|
|
Oct 15 12:54:09 PM UTC 24 |
Oct 15 12:54:12 PM UTC 24 |
75011799 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.3132189019 |
|
|
Oct 15 12:54:09 PM UTC 24 |
Oct 15 12:54:12 PM UTC 24 |
321301631 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset_invalid.4022250868 |
|
|
Oct 15 12:54:09 PM UTC 24 |
Oct 15 12:54:12 PM UTC 24 |
107466984 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_escalation_timeout.222549645 |
|
|
Oct 15 12:54:09 PM UTC 24 |
Oct 15 12:54:12 PM UTC 24 |
199958353 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3260928822 |
|
|
Oct 15 12:54:08 PM UTC 24 |
Oct 15 12:54:12 PM UTC 24 |
809039597 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3707117726 |
|
|
Oct 15 12:54:09 PM UTC 24 |
Oct 15 12:54:13 PM UTC 24 |
876747056 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.4222815700 |
|
|
Oct 15 12:54:11 PM UTC 24 |
Oct 15 12:54:13 PM UTC 24 |
43345845 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup.2269476834 |
|
|
Oct 15 12:54:12 PM UTC 24 |
Oct 15 12:54:14 PM UTC 24 |
139854863 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset.4036561799 |
|
|
Oct 15 12:54:12 PM UTC 24 |
Oct 15 12:54:14 PM UTC 24 |
84647285 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.456246737 |
|
|
Oct 15 12:54:12 PM UTC 24 |
Oct 15 12:54:14 PM UTC 24 |
102464389 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup_reset.954512769 |
|
|
Oct 15 12:54:12 PM UTC 24 |
Oct 15 12:54:14 PM UTC 24 |
89271305 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_wakeup_race.1266563742 |
|
|
Oct 15 12:54:12 PM UTC 24 |
Oct 15 12:54:14 PM UTC 24 |
206653828 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_aborted_low_power.389050773 |
|
|
Oct 15 12:54:12 PM UTC 24 |
Oct 15 12:54:14 PM UTC 24 |
160181719 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.1356707591 |
|
|
Oct 15 12:54:07 PM UTC 24 |
Oct 15 12:54:15 PM UTC 24 |
2594795806 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all.1249438496 |
|
|
Oct 15 12:54:10 PM UTC 24 |
Oct 15 12:54:15 PM UTC 24 |
529975014 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.315382050 |
|
|
Oct 15 12:54:14 PM UTC 24 |
Oct 15 12:54:15 PM UTC 24 |
31969649 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1443629941 |
|
|
Oct 15 12:54:12 PM UTC 24 |
Oct 15 12:54:16 PM UTC 24 |
1019535523 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_glitch.57828701 |
|
|
Oct 15 12:54:14 PM UTC 24 |
Oct 15 12:54:16 PM UTC 24 |
78243041 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_global_esc.2388221424 |
|
|
Oct 15 12:54:14 PM UTC 24 |
Oct 15 12:54:16 PM UTC 24 |
33143440 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.3097042760 |
|
|
Oct 15 12:54:14 PM UTC 24 |
Oct 15 12:54:16 PM UTC 24 |
58450228 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_invalid.2277731976 |
|
|
Oct 15 12:54:14 PM UTC 24 |
Oct 15 12:54:16 PM UTC 24 |
80189872 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset_invalid.425477639 |
|
|
Oct 15 12:54:14 PM UTC 24 |
Oct 15 12:54:16 PM UTC 24 |
106258991 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.2037441287 |
|
|
Oct 15 12:54:14 PM UTC 24 |
Oct 15 12:54:16 PM UTC 24 |
135297373 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_escalation_timeout.2532501044 |
|
|
Oct 15 12:54:14 PM UTC 24 |
Oct 15 12:54:16 PM UTC 24 |
408088400 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4192092283 |
|
|
Oct 15 12:54:12 PM UTC 24 |
Oct 15 12:54:17 PM UTC 24 |
938962668 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.1313476005 |
|
|
Oct 15 12:54:07 PM UTC 24 |
Oct 15 12:54:17 PM UTC 24 |
1697341451 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_smoke.1572383921 |
|
|
Oct 15 12:54:15 PM UTC 24 |
Oct 15 12:54:17 PM UTC 24 |
62361902 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all.617892834 |
|
|
Oct 15 12:54:15 PM UTC 24 |
Oct 15 12:54:17 PM UTC 24 |
226267508 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset.3136576381 |
|
|
Oct 15 12:54:15 PM UTC 24 |
Oct 15 12:54:18 PM UTC 24 |
189036416 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup.1514049934 |
|
|
Oct 15 12:54:15 PM UTC 24 |
Oct 15 12:54:18 PM UTC 24 |
509897276 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all_with_rand_reset.3701114563 |
|
|
Oct 15 12:54:01 PM UTC 24 |
Oct 15 12:54:18 PM UTC 24 |
4091637627 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_wakeup_race.1980759698 |
|
|
Oct 15 12:54:15 PM UTC 24 |
Oct 15 12:54:18 PM UTC 24 |
184834558 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup_reset.1780744842 |
|
|
Oct 15 12:54:15 PM UTC 24 |
Oct 15 12:54:18 PM UTC 24 |
220989346 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.3912811627 |
|
|
Oct 15 12:54:17 PM UTC 24 |
Oct 15 12:54:19 PM UTC 24 |
45950124 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_global_esc.1630701816 |
|
|
Oct 15 12:54:17 PM UTC 24 |
Oct 15 12:54:19 PM UTC 24 |
31413226 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_aborted_low_power.4054306316 |
|
|
Oct 15 12:54:17 PM UTC 24 |
Oct 15 12:54:19 PM UTC 24 |
42222219 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_glitch.2162061815 |
|
|
Oct 15 12:54:17 PM UTC 24 |
Oct 15 12:54:19 PM UTC 24 |
49874453 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1244112138 |
|
|
Oct 15 12:54:17 PM UTC 24 |
Oct 15 12:54:20 PM UTC 24 |
167696241 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_escalation_timeout.2822220358 |
|
|
Oct 15 12:54:17 PM UTC 24 |
Oct 15 12:54:20 PM UTC 24 |
401475630 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.1169639806 |
|
|
Oct 15 12:54:17 PM UTC 24 |
Oct 15 12:54:20 PM UTC 24 |
138440838 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_disable_rom_integrity_check.1163478814 |
|
|
Oct 15 12:54:18 PM UTC 24 |
Oct 15 12:54:20 PM UTC 24 |
67681751 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset_invalid.737704503 |
|
|
Oct 15 12:54:18 PM UTC 24 |
Oct 15 12:54:20 PM UTC 24 |
169022033 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_invalid.2724570212 |
|
|
Oct 15 12:54:19 PM UTC 24 |
Oct 15 12:54:21 PM UTC 24 |
85085282 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_smoke.4127375165 |
|
|
Oct 15 12:54:19 PM UTC 24 |
Oct 15 12:54:21 PM UTC 24 |
38454316 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset.2969461181 |
|
|
Oct 15 12:54:19 PM UTC 24 |
Oct 15 12:54:21 PM UTC 24 |
35569267 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_aborted_low_power.1462493849 |
|
|
Oct 15 12:54:19 PM UTC 24 |
Oct 15 12:54:21 PM UTC 24 |
50128614 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_wakeup_race.769050007 |
|
|
Oct 15 12:54:19 PM UTC 24 |
Oct 15 12:54:21 PM UTC 24 |
235226918 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1883688382 |
|
|
Oct 15 12:54:17 PM UTC 24 |
Oct 15 12:54:22 PM UTC 24 |
859004223 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4108924832 |
|
|
Oct 15 12:54:17 PM UTC 24 |
Oct 15 12:54:22 PM UTC 24 |
888651295 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup_reset.2674854136 |
|
|
Oct 15 12:54:19 PM UTC 24 |
Oct 15 12:54:22 PM UTC 24 |
352597504 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all_with_rand_reset.1153469854 |
|
|
Oct 15 12:54:10 PM UTC 24 |
Oct 15 12:54:22 PM UTC 24 |
10180361979 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup.196210577 |
|
|
Oct 15 12:54:19 PM UTC 24 |
Oct 15 12:54:22 PM UTC 24 |
156506259 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.1004727460 |
|
|
Oct 15 12:54:20 PM UTC 24 |
Oct 15 12:54:22 PM UTC 24 |
64287222 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.1700360866 |
|
|
Oct 15 12:54:21 PM UTC 24 |
Oct 15 12:54:22 PM UTC 24 |
55809072 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_global_esc.975085615 |
|
|
Oct 15 12:54:21 PM UTC 24 |
Oct 15 12:54:23 PM UTC 24 |
87101329 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_glitch.1533663847 |
|
|
Oct 15 12:54:21 PM UTC 24 |
Oct 15 12:54:23 PM UTC 24 |
60802110 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_escalation_timeout.646020496 |
|
|
Oct 15 12:54:21 PM UTC 24 |
Oct 15 12:54:23 PM UTC 24 |
420469995 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_disable_rom_integrity_check.84979334 |
|
|
Oct 15 12:54:21 PM UTC 24 |
Oct 15 12:54:23 PM UTC 24 |
55295461 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.3293729692 |
|
|
Oct 15 12:54:21 PM UTC 24 |
Oct 15 12:54:23 PM UTC 24 |
212592976 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_smoke.1655898555 |
|
|
Oct 15 12:54:22 PM UTC 24 |
Oct 15 12:54:24 PM UTC 24 |
37909460 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_invalid.3855997253 |
|
|
Oct 15 12:54:22 PM UTC 24 |
Oct 15 12:54:24 PM UTC 24 |
66107157 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all.2748572009 |
|
|
Oct 15 12:54:19 PM UTC 24 |
Oct 15 12:54:24 PM UTC 24 |
1184982073 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset_invalid.2834008272 |
|
|
Oct 15 12:54:22 PM UTC 24 |
Oct 15 12:54:24 PM UTC 24 |
123214299 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1510240871 |
|
|
Oct 15 12:54:20 PM UTC 24 |
Oct 15 12:54:25 PM UTC 24 |
826837003 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all.3780559887 |
|
|
Oct 15 12:54:22 PM UTC 24 |
Oct 15 12:54:25 PM UTC 24 |
546298144 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3148425655 |
|
|
Oct 15 12:54:20 PM UTC 24 |
Oct 15 12:54:25 PM UTC 24 |
782127912 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_aborted_low_power.596351208 |
|
|
Oct 15 12:54:24 PM UTC 24 |
Oct 15 12:54:26 PM UTC 24 |
32448715 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.3153148910 |
|
|
Oct 15 12:54:24 PM UTC 24 |
Oct 15 12:54:26 PM UTC 24 |
44687342 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_wakeup_race.1010149518 |
|
|
Oct 15 12:54:24 PM UTC 24 |
Oct 15 12:54:26 PM UTC 24 |
136049831 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup.2923776905 |
|
|
Oct 15 12:54:24 PM UTC 24 |
Oct 15 12:54:26 PM UTC 24 |
170469713 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_glitch.1902132723 |
|
|
Oct 15 12:54:24 PM UTC 24 |
Oct 15 12:54:26 PM UTC 24 |
29260080 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.934972662 |
|
|
Oct 15 12:54:24 PM UTC 24 |
Oct 15 12:54:26 PM UTC 24 |
54794483 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.1202014563 |
|
|
Oct 15 12:54:24 PM UTC 24 |
Oct 15 12:54:26 PM UTC 24 |
104910861 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_global_esc.3422433217 |
|
|
Oct 15 12:54:24 PM UTC 24 |
Oct 15 12:54:26 PM UTC 24 |
50054381 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_escalation_timeout.1932611965 |
|
|
Oct 15 12:54:24 PM UTC 24 |
Oct 15 12:54:26 PM UTC 24 |
204836262 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.2188239163 |
|
|
Oct 15 12:54:24 PM UTC 24 |
Oct 15 12:54:26 PM UTC 24 |
74168944 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup_reset.2189563850 |
|
|
Oct 15 12:54:24 PM UTC 24 |
Oct 15 12:54:26 PM UTC 24 |
401103879 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset.1659315780 |
|
|
Oct 15 12:54:36 PM UTC 24 |
Oct 15 12:54:38 PM UTC 24 |
270983232 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1003997513 |
|
|
Oct 15 12:54:24 PM UTC 24 |
Oct 15 12:54:27 PM UTC 24 |
872263116 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_invalid.220730189 |
|
|
Oct 15 12:54:26 PM UTC 24 |
Oct 15 12:54:28 PM UTC 24 |
45670681 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all_with_rand_reset.990114214 |
|
|
Oct 15 12:54:15 PM UTC 24 |
Oct 15 12:54:28 PM UTC 24 |
7881456454 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_smoke.3471392984 |
|
|
Oct 15 12:54:26 PM UTC 24 |
Oct 15 12:54:28 PM UTC 24 |
30708736 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.471243436 |
|
|
Oct 15 12:54:24 PM UTC 24 |
Oct 15 12:54:28 PM UTC 24 |
789794951 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset.3788315832 |
|
|
Oct 15 12:54:26 PM UTC 24 |
Oct 15 12:54:28 PM UTC 24 |
26523660 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset_invalid.3810117410 |
|
|
Oct 15 12:54:26 PM UTC 24 |
Oct 15 12:54:28 PM UTC 24 |
103665615 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup_reset.3360307506 |
|
|
Oct 15 12:54:36 PM UTC 24 |
Oct 15 12:54:38 PM UTC 24 |
99295960 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_aborted_low_power.997288577 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:30 PM UTC 24 |
19494240 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_wakeup_race.721920047 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:30 PM UTC 24 |
310223462 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_global_esc.266851673 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:30 PM UTC 24 |
53068801 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.798668255 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:30 PM UTC 24 |
40166187 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup.1221888471 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:30 PM UTC 24 |
131233058 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_glitch.1818917213 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:30 PM UTC 24 |
50607471 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup_reset.817887513 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:30 PM UTC 24 |
290243328 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.2170172217 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:30 PM UTC 24 |
63392950 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.2776869634 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:30 PM UTC 24 |
92075796 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_escalation_timeout.126585325 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:30 PM UTC 24 |
199454649 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_invalid.1500344833 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:30 PM UTC 24 |
70040903 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.1118930489 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:30 PM UTC 24 |
90720641 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset_invalid.412591185 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:31 PM UTC 24 |
110918950 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all.3497022087 |
|
|
Oct 15 12:54:26 PM UTC 24 |
Oct 15 12:54:31 PM UTC 24 |
4692717899 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_smoke.1226115485 |
|
|
Oct 15 12:54:30 PM UTC 24 |
Oct 15 12:54:31 PM UTC 24 |
33105026 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3668053593 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:31 PM UTC 24 |
1202729103 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3423282908 |
|
|
Oct 15 12:54:28 PM UTC 24 |
Oct 15 12:54:32 PM UTC 24 |
820454533 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup.45598133 |
|
|
Oct 15 12:54:30 PM UTC 24 |
Oct 15 12:54:32 PM UTC 24 |
179349271 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset.1219729141 |
|
|
Oct 15 12:54:30 PM UTC 24 |
Oct 15 12:54:32 PM UTC 24 |
97410071 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_wakeup_race.86789088 |
|
|
Oct 15 12:54:30 PM UTC 24 |
Oct 15 12:54:32 PM UTC 24 |
193299832 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup_reset.3633028756 |
|
|
Oct 15 12:54:30 PM UTC 24 |
Oct 15 12:54:32 PM UTC 24 |
275369694 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_escalation_timeout.3130643277 |
|
|
Oct 15 12:54:34 PM UTC 24 |
Oct 15 12:54:37 PM UTC 24 |
202563521 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.1953345740 |
|
|
Oct 15 12:54:31 PM UTC 24 |
Oct 15 12:54:33 PM UTC 24 |
39644836 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_aborted_low_power.4256708472 |
|
|
Oct 15 12:54:31 PM UTC 24 |
Oct 15 12:54:33 PM UTC 24 |
21362132 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3779105918 |
|
|
Oct 15 12:54:31 PM UTC 24 |
Oct 15 12:54:33 PM UTC 24 |
107351406 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_global_esc.3055648822 |
|
|
Oct 15 12:54:31 PM UTC 24 |
Oct 15 12:54:33 PM UTC 24 |
22339907 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_glitch.2653172493 |
|
|
Oct 15 12:54:31 PM UTC 24 |
Oct 15 12:54:33 PM UTC 24 |
121116626 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_escalation_timeout.178689290 |
|
|
Oct 15 12:54:31 PM UTC 24 |
Oct 15 12:54:33 PM UTC 24 |
404049374 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset_invalid.1786485831 |
|
|
Oct 15 12:54:31 PM UTC 24 |
Oct 15 12:54:33 PM UTC 24 |
171232926 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_invalid.707127855 |
|
|
Oct 15 12:54:31 PM UTC 24 |
Oct 15 12:54:33 PM UTC 24 |
40710563 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.3008754935 |
|
|
Oct 15 12:54:31 PM UTC 24 |
Oct 15 12:54:33 PM UTC 24 |
166647373 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_disable_rom_integrity_check.3962600784 |
|
|
Oct 15 12:54:31 PM UTC 24 |
Oct 15 12:54:33 PM UTC 24 |
67011857 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all_with_rand_reset.2783968686 |
|
|
Oct 15 12:54:26 PM UTC 24 |
Oct 15 12:54:34 PM UTC 24 |
5164195799 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_smoke.739219405 |
|
|
Oct 15 12:54:33 PM UTC 24 |
Oct 15 12:54:35 PM UTC 24 |
49825260 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup.3463757223 |
|
|
Oct 15 12:54:36 PM UTC 24 |
Oct 15 12:54:38 PM UTC 24 |
144044347 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2849298122 |
|
|
Oct 15 12:54:31 PM UTC 24 |
Oct 15 12:54:35 PM UTC 24 |
1126138015 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset.1592420688 |
|
|
Oct 15 12:54:33 PM UTC 24 |
Oct 15 12:54:35 PM UTC 24 |
27610470 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_wakeup_race.2048273624 |
|
|
Oct 15 12:54:33 PM UTC 24 |
Oct 15 12:54:35 PM UTC 24 |
138332183 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all.1405120814 |
|
|
Oct 15 12:54:29 PM UTC 24 |
Oct 15 12:54:35 PM UTC 24 |
1012660602 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_aborted_low_power.1255779226 |
|
|
Oct 15 12:54:33 PM UTC 24 |
Oct 15 12:54:35 PM UTC 24 |
69031432 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup.947624609 |
|
|
Oct 15 12:54:33 PM UTC 24 |
Oct 15 12:54:35 PM UTC 24 |
181362889 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all_with_rand_reset.394783086 |
|
|
Oct 15 12:54:22 PM UTC 24 |
Oct 15 12:54:36 PM UTC 24 |
3117742411 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3988474914 |
|
|
Oct 15 12:54:31 PM UTC 24 |
Oct 15 12:54:36 PM UTC 24 |
802458387 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup_reset.1683505717 |
|
|
Oct 15 12:54:33 PM UTC 24 |
Oct 15 12:54:36 PM UTC 24 |
268863713 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_smoke.2372790055 |
|
|
Oct 15 12:54:36 PM UTC 24 |
Oct 15 12:54:38 PM UTC 24 |
40158424 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all.922467526 |
|
|
Oct 15 12:54:33 PM UTC 24 |
Oct 15 12:54:36 PM UTC 24 |
548797693 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_global_esc.2164951605 |
|
|
Oct 15 12:54:34 PM UTC 24 |
Oct 15 12:54:36 PM UTC 24 |
49220225 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.1951150525 |
|
|
Oct 15 12:54:34 PM UTC 24 |
Oct 15 12:54:36 PM UTC 24 |
31316679 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_glitch.964582210 |
|
|
Oct 15 12:54:34 PM UTC 24 |
Oct 15 12:54:36 PM UTC 24 |
50326022 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_disable_rom_integrity_check.3390771388 |
|
|
Oct 15 12:54:34 PM UTC 24 |
Oct 15 12:54:37 PM UTC 24 |
64734342 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset_invalid.1486461314 |
|
|
Oct 15 12:54:34 PM UTC 24 |
Oct 15 12:54:37 PM UTC 24 |
175861715 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_invalid.3907515770 |
|
|
Oct 15 12:54:34 PM UTC 24 |
Oct 15 12:54:37 PM UTC 24 |
57229627 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.1011487909 |
|
|
Oct 15 12:54:34 PM UTC 24 |
Oct 15 12:54:37 PM UTC 24 |
289421917 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.4216853236 |
|
|
Oct 15 12:54:34 PM UTC 24 |
Oct 15 12:54:37 PM UTC 24 |
96986994 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_glitch.404739792 |
|
|
Oct 15 12:54:38 PM UTC 24 |
Oct 15 12:54:40 PM UTC 24 |
48412923 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all_with_rand_reset.2114734239 |
|
|
Oct 15 12:54:29 PM UTC 24 |
Oct 15 12:54:37 PM UTC 24 |
10565583284 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3108860502 |
|
|
Oct 15 12:54:34 PM UTC 24 |
Oct 15 12:54:37 PM UTC 24 |
1064271451 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4010973308 |
|
|
Oct 15 12:54:33 PM UTC 24 |
Oct 15 12:54:38 PM UTC 24 |
860769093 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_aborted_low_power.723550503 |
|
|
Oct 15 12:54:36 PM UTC 24 |
Oct 15 12:54:38 PM UTC 24 |
38552071 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_wakeup_race.1556443335 |
|
|
Oct 15 12:54:36 PM UTC 24 |
Oct 15 12:54:39 PM UTC 24 |
286821957 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.2938041580 |
|
|
Oct 15 12:54:37 PM UTC 24 |
Oct 15 12:54:40 PM UTC 24 |
28752897 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_global_esc.2116024607 |
|
|
Oct 15 12:54:37 PM UTC 24 |
Oct 15 12:54:40 PM UTC 24 |
58514698 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_disable_rom_integrity_check.1340204156 |
|
|
Oct 15 12:54:38 PM UTC 24 |
Oct 15 12:54:40 PM UTC 24 |
60378586 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_invalid.1768833343 |
|
|
Oct 15 12:54:38 PM UTC 24 |
Oct 15 12:54:40 PM UTC 24 |
78461280 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.3903072139 |
|
|
Oct 15 12:54:37 PM UTC 24 |
Oct 15 12:54:40 PM UTC 24 |
164101450 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset_invalid.3585220415 |
|
|
Oct 15 12:54:38 PM UTC 24 |
Oct 15 12:54:40 PM UTC 24 |
101063500 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_escalation_timeout.1939601829 |
|
|
Oct 15 12:54:38 PM UTC 24 |
Oct 15 12:54:40 PM UTC 24 |
198472523 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.372757488 |
|
|
Oct 15 12:54:37 PM UTC 24 |
Oct 15 12:54:40 PM UTC 24 |
110044037 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2970011219 |
|
|
Oct 15 12:54:37 PM UTC 24 |
Oct 15 12:54:41 PM UTC 24 |
1505439357 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all_with_rand_reset.2058771533 |
|
|
Oct 15 12:54:19 PM UTC 24 |
Oct 15 12:54:41 PM UTC 24 |
5183134786 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all.2980647439 |
|
|
Oct 15 12:54:36 PM UTC 24 |
Oct 15 12:54:41 PM UTC 24 |
3100165653 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_smoke.2988800022 |
|
|
Oct 15 12:54:39 PM UTC 24 |
Oct 15 12:54:41 PM UTC 24 |
29552416 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all.2322902948 |
|
|
Oct 15 12:54:38 PM UTC 24 |
Oct 15 12:54:41 PM UTC 24 |
717862550 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset.3683082119 |
|
|
Oct 15 12:54:39 PM UTC 24 |
Oct 15 12:54:41 PM UTC 24 |
135476834 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup_reset.1023133188 |
|
|
Oct 15 12:54:39 PM UTC 24 |
Oct 15 12:54:41 PM UTC 24 |
252767783 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup.2104014936 |
|
|
Oct 15 12:54:39 PM UTC 24 |
Oct 15 12:54:41 PM UTC 24 |
287247232 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_aborted_low_power.2929041434 |
|
|
Oct 15 12:54:39 PM UTC 24 |
Oct 15 12:54:41 PM UTC 24 |
68340271 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4063439534 |
|
|
Oct 15 12:54:37 PM UTC 24 |
Oct 15 12:54:41 PM UTC 24 |
831644074 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.99805224 |
|
|
Oct 15 12:54:39 PM UTC 24 |
Oct 15 12:54:42 PM UTC 24 |
66176699 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_wakeup_race.3913784989 |
|
|
Oct 15 12:54:39 PM UTC 24 |
Oct 15 12:54:42 PM UTC 24 |
305325531 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2054708101 |
|
|
Oct 15 12:54:39 PM UTC 24 |
Oct 15 12:54:43 PM UTC 24 |
839560423 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2989847964 |
|
|
Oct 15 12:54:39 PM UTC 24 |
Oct 15 12:54:44 PM UTC 24 |
925888688 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all_with_rand_reset.4167430014 |
|
|
Oct 15 12:54:36 PM UTC 24 |
Oct 15 12:54:45 PM UTC 24 |
6948934578 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all_with_rand_reset.1959304809 |
|
|
Oct 15 12:54:38 PM UTC 24 |
Oct 15 12:54:45 PM UTC 24 |
5045626293 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_glitch.3910257786 |
|
|
Oct 15 12:54:41 PM UTC 24 |
Oct 15 12:54:46 PM UTC 24 |
59467386 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_global_esc.551032527 |
|
|
Oct 15 12:54:41 PM UTC 24 |
Oct 15 12:54:46 PM UTC 24 |
113573467 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_escalation_timeout.4268704993 |
|
|
Oct 15 12:54:41 PM UTC 24 |
Oct 15 12:54:46 PM UTC 24 |
402917264 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_disable_rom_integrity_check.475124210 |
|
|
Oct 15 12:54:41 PM UTC 24 |
Oct 15 12:54:46 PM UTC 24 |
66208004 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all_with_rand_reset.3949989710 |
|
|
Oct 15 12:54:31 PM UTC 24 |
Oct 15 12:54:47 PM UTC 24 |
10525663823 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.1341988593 |
|
|
Oct 15 12:54:44 PM UTC 24 |
Oct 15 12:54:47 PM UTC 24 |
34939836 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.2690827675 |
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Oct 15 12:54:44 PM UTC 24 |
Oct 15 12:54:47 PM UTC 24 |
112404606 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.3978982382 |
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Oct 15 12:55:04 PM UTC 24 |
Oct 15 12:55:06 PM UTC 24 |
31709056 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.987932648 |
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Oct 15 12:54:43 PM UTC 24 |
Oct 15 12:54:52 PM UTC 24 |
28912039 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.330687340 |
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Oct 15 12:54:43 PM UTC 24 |
Oct 15 12:54:52 PM UTC 24 |
30175290 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_aborted_low_power.1779720649 |
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Oct 15 12:54:43 PM UTC 24 |
Oct 15 12:54:52 PM UTC 24 |
45409376 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.3865940883 |
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Oct 15 12:54:43 PM UTC 24 |
Oct 15 12:54:52 PM UTC 24 |
430055088 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.2746545907 |
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Oct 15 12:54:43 PM UTC 24 |
Oct 15 12:54:52 PM UTC 24 |
296297970 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2367411372 |
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Oct 15 12:54:43 PM UTC 24 |
Oct 15 12:54:52 PM UTC 24 |
84986482 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1641397911 |
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Oct 15 12:54:43 PM UTC 24 |
Oct 15 12:54:53 PM UTC 24 |
937381471 ps |