| T561 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2902963614 |
|
|
Oct 15 12:54:43 PM UTC 24 |
Oct 15 12:54:54 PM UTC 24 |
884537207 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.526089247 |
|
|
Oct 15 12:54:48 PM UTC 24 |
Oct 15 12:54:56 PM UTC 24 |
28535361 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.3515767542 |
|
|
Oct 15 12:54:48 PM UTC 24 |
Oct 15 12:54:57 PM UTC 24 |
33349604 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.3876780783 |
|
|
Oct 15 12:54:48 PM UTC 24 |
Oct 15 12:54:57 PM UTC 24 |
125931837 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.3436798091 |
|
|
Oct 15 12:54:52 PM UTC 24 |
Oct 15 12:54:57 PM UTC 24 |
52040775 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1617302583 |
|
|
Oct 15 12:54:52 PM UTC 24 |
Oct 15 12:54:57 PM UTC 24 |
30399351 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.29080829 |
|
|
Oct 15 12:54:48 PM UTC 24 |
Oct 15 12:54:57 PM UTC 24 |
290332242 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_glitch.3093912203 |
|
|
Oct 15 12:54:55 PM UTC 24 |
Oct 15 12:54:57 PM UTC 24 |
76938639 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.2635386969 |
|
|
Oct 15 12:54:52 PM UTC 24 |
Oct 15 12:54:57 PM UTC 24 |
244567888 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_smoke.1129443179 |
|
|
Oct 15 12:54:43 PM UTC 24 |
Oct 15 12:54:57 PM UTC 24 |
139512639 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2906865947 |
|
|
Oct 15 12:54:52 PM UTC 24 |
Oct 15 12:54:59 PM UTC 24 |
1270248631 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3296787852 |
|
|
Oct 15 12:54:52 PM UTC 24 |
Oct 15 12:54:59 PM UTC 24 |
919466489 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.1229273695 |
|
|
Oct 15 12:54:57 PM UTC 24 |
Oct 15 12:55:01 PM UTC 24 |
66283458 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.2181281905 |
|
|
Oct 15 12:54:59 PM UTC 24 |
Oct 15 12:55:02 PM UTC 24 |
34842071 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_global_esc.588811560 |
|
|
Oct 15 12:54:53 PM UTC 24 |
Oct 15 12:55:02 PM UTC 24 |
51883379 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_escalation_timeout.1718368847 |
|
|
Oct 15 12:54:53 PM UTC 24 |
Oct 15 12:55:02 PM UTC 24 |
1840498662 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.1817296209 |
|
|
Oct 15 12:54:48 PM UTC 24 |
Oct 15 12:55:03 PM UTC 24 |
31294677 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2407543989 |
|
|
Oct 15 12:55:00 PM UTC 24 |
Oct 15 12:55:03 PM UTC 24 |
1732116533 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_invalid.2403385803 |
|
|
Oct 15 12:54:58 PM UTC 24 |
Oct 15 12:55:03 PM UTC 24 |
44597541 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup.858525312 |
|
|
Oct 15 12:54:58 PM UTC 24 |
Oct 15 12:55:03 PM UTC 24 |
106788975 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup_reset.980206848 |
|
|
Oct 15 12:54:58 PM UTC 24 |
Oct 15 12:55:03 PM UTC 24 |
50066620 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_smoke.717413761 |
|
|
Oct 15 12:54:58 PM UTC 24 |
Oct 15 12:55:03 PM UTC 24 |
30243067 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset.4083589990 |
|
|
Oct 15 12:54:58 PM UTC 24 |
Oct 15 12:55:03 PM UTC 24 |
292679455 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset_invalid.1671649875 |
|
|
Oct 15 12:54:58 PM UTC 24 |
Oct 15 12:55:03 PM UTC 24 |
104957256 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset_invalid.222986022 |
|
|
Oct 15 12:54:41 PM UTC 24 |
Oct 15 12:55:03 PM UTC 24 |
101955817 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_invalid.3633378362 |
|
|
Oct 15 12:54:41 PM UTC 24 |
Oct 15 12:55:03 PM UTC 24 |
43075917 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_wakeup_race.426634729 |
|
|
Oct 15 12:54:58 PM UTC 24 |
Oct 15 12:55:03 PM UTC 24 |
334946815 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.4206168649 |
|
|
Oct 15 12:54:48 PM UTC 24 |
Oct 15 12:55:03 PM UTC 24 |
274293432 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.4084412111 |
|
|
Oct 15 12:54:48 PM UTC 24 |
Oct 15 12:55:04 PM UTC 24 |
525791755 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_global_esc.3047004745 |
|
|
Oct 15 12:55:04 PM UTC 24 |
Oct 15 12:55:06 PM UTC 24 |
23792575 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.4239991725 |
|
|
Oct 15 12:55:04 PM UTC 24 |
Oct 15 12:55:07 PM UTC 24 |
194039571 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset_invalid.3634818709 |
|
|
Oct 15 12:55:04 PM UTC 24 |
Oct 15 12:55:07 PM UTC 24 |
269245136 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2008969668 |
|
|
Oct 15 12:55:04 PM UTC 24 |
Oct 15 12:55:07 PM UTC 24 |
297023420 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.1343736871 |
|
|
Oct 15 12:54:41 PM UTC 24 |
Oct 15 12:55:08 PM UTC 24 |
1570703179 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all.3196420228 |
|
|
Oct 15 12:54:58 PM UTC 24 |
Oct 15 12:55:08 PM UTC 24 |
1552017330 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2543558705 |
|
|
Oct 15 12:55:07 PM UTC 24 |
Oct 15 12:55:12 PM UTC 24 |
47980777 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_global_esc.2806560106 |
|
|
Oct 15 12:55:07 PM UTC 24 |
Oct 15 12:55:12 PM UTC 24 |
44214688 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.80675072 |
|
|
Oct 15 12:55:07 PM UTC 24 |
Oct 15 12:55:12 PM UTC 24 |
87668542 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.2789304569 |
|
|
Oct 15 12:55:07 PM UTC 24 |
Oct 15 12:55:13 PM UTC 24 |
229277646 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_glitch.2274124653 |
|
|
Oct 15 12:55:09 PM UTC 24 |
Oct 15 12:55:13 PM UTC 24 |
55139671 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_escalation_timeout.1062776783 |
|
|
Oct 15 12:55:09 PM UTC 24 |
Oct 15 12:55:14 PM UTC 24 |
110117280 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2952166615 |
|
|
Oct 15 12:55:07 PM UTC 24 |
Oct 15 12:55:14 PM UTC 24 |
1352498223 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_glitch.2261478490 |
|
|
Oct 15 12:55:04 PM UTC 24 |
Oct 15 12:55:14 PM UTC 24 |
108108036 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset.2014254759 |
|
|
Oct 15 12:55:04 PM UTC 24 |
Oct 15 12:55:14 PM UTC 24 |
34775556 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.3115994437 |
|
|
Oct 15 12:55:04 PM UTC 24 |
Oct 15 12:55:14 PM UTC 24 |
89386042 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_invalid.2460832648 |
|
|
Oct 15 12:55:04 PM UTC 24 |
Oct 15 12:55:14 PM UTC 24 |
145580617 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_escalation_timeout.1650201347 |
|
|
Oct 15 12:55:04 PM UTC 24 |
Oct 15 12:55:14 PM UTC 24 |
483704645 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_smoke.4206991532 |
|
|
Oct 15 12:55:04 PM UTC 24 |
Oct 15 12:55:14 PM UTC 24 |
61394428 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all_with_rand_reset.3476499542 |
|
|
Oct 15 12:54:41 PM UTC 24 |
Oct 15 12:55:16 PM UTC 24 |
3505914088 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all_with_rand_reset.1511884908 |
|
|
Oct 15 12:54:58 PM UTC 24 |
Oct 15 12:55:16 PM UTC 24 |
8897650945 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_smoke.1773404460 |
|
|
Oct 15 12:55:14 PM UTC 24 |
Oct 15 12:55:17 PM UTC 24 |
52908699 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_wakeup_race.1074576471 |
|
|
Oct 15 12:55:14 PM UTC 24 |
Oct 15 12:55:17 PM UTC 24 |
123973726 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup_reset.2720435470 |
|
|
Oct 15 12:55:14 PM UTC 24 |
Oct 15 12:55:17 PM UTC 24 |
203858672 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all.2279795759 |
|
|
Oct 15 12:55:04 PM UTC 24 |
Oct 15 12:55:17 PM UTC 24 |
490657291 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset.3245121174 |
|
|
Oct 15 12:55:14 PM UTC 24 |
Oct 15 12:55:17 PM UTC 24 |
90422414 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup_reset.2874911780 |
|
|
Oct 15 12:55:05 PM UTC 24 |
Oct 15 12:55:17 PM UTC 24 |
225540445 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup.234404018 |
|
|
Oct 15 12:55:14 PM UTC 24 |
Oct 15 12:55:17 PM UTC 24 |
236449709 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_aborted_low_power.2315272720 |
|
|
Oct 15 12:55:15 PM UTC 24 |
Oct 15 12:55:17 PM UTC 24 |
100834346 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_aborted_low_power.4060955421 |
|
|
Oct 15 12:55:05 PM UTC 24 |
Oct 15 12:55:17 PM UTC 24 |
38905331 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.4199544001 |
|
|
Oct 15 12:55:15 PM UTC 24 |
Oct 15 12:55:17 PM UTC 24 |
140202152 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup.2605647721 |
|
|
Oct 15 12:55:05 PM UTC 24 |
Oct 15 12:55:18 PM UTC 24 |
128963698 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_wakeup_race.1744879154 |
|
|
Oct 15 12:55:05 PM UTC 24 |
Oct 15 12:55:18 PM UTC 24 |
272738388 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2389355382 |
|
|
Oct 15 12:55:15 PM UTC 24 |
Oct 15 12:55:18 PM UTC 24 |
964734218 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2697818844 |
|
|
Oct 15 12:55:05 PM UTC 24 |
Oct 15 12:55:19 PM UTC 24 |
1092322398 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.252752080 |
|
|
Oct 15 12:55:02 PM UTC 24 |
Oct 15 12:55:19 PM UTC 24 |
846976494 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1394640145 |
|
|
Oct 15 12:55:15 PM UTC 24 |
Oct 15 12:55:19 PM UTC 24 |
851869194 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3145259637 |
|
|
Oct 15 12:55:17 PM UTC 24 |
Oct 15 12:55:21 PM UTC 24 |
31927219 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.4246251590 |
|
|
Oct 15 12:55:17 PM UTC 24 |
Oct 15 12:55:22 PM UTC 24 |
223939727 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_wakeup_race.1708069644 |
|
|
Oct 15 12:55:19 PM UTC 24 |
Oct 15 12:55:22 PM UTC 24 |
347545988 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_aborted_low_power.3875322004 |
|
|
Oct 15 12:55:19 PM UTC 24 |
Oct 15 12:55:22 PM UTC 24 |
117073182 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup.2442042473 |
|
|
Oct 15 12:55:19 PM UTC 24 |
Oct 15 12:55:22 PM UTC 24 |
222521211 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup_reset.3750870837 |
|
|
Oct 15 12:55:19 PM UTC 24 |
Oct 15 12:55:22 PM UTC 24 |
222421298 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_global_esc.2292486561 |
|
|
Oct 15 12:55:18 PM UTC 24 |
Oct 15 12:55:23 PM UTC 24 |
54606317 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all.960944866 |
|
|
Oct 15 12:55:13 PM UTC 24 |
Oct 15 12:55:23 PM UTC 24 |
657210273 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.4102292149 |
|
|
Oct 15 12:55:18 PM UTC 24 |
Oct 15 12:55:23 PM UTC 24 |
73189766 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.482919499 |
|
|
Oct 15 12:55:20 PM UTC 24 |
Oct 15 12:55:23 PM UTC 24 |
1332962068 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.327939464 |
|
|
Oct 15 12:55:20 PM UTC 24 |
Oct 15 12:55:24 PM UTC 24 |
1152426404 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_invalid.2600738400 |
|
|
Oct 15 12:55:18 PM UTC 24 |
Oct 15 12:55:26 PM UTC 24 |
77603849 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset.456069554 |
|
|
Oct 15 12:55:18 PM UTC 24 |
Oct 15 12:55:26 PM UTC 24 |
53195301 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_smoke.1450095267 |
|
|
Oct 15 12:55:18 PM UTC 24 |
Oct 15 12:55:26 PM UTC 24 |
31921520 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all_with_rand_reset.68997661 |
|
|
Oct 15 12:55:04 PM UTC 24 |
Oct 15 12:55:26 PM UTC 24 |
6830358569 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset_invalid.3982651232 |
|
|
Oct 15 12:55:18 PM UTC 24 |
Oct 15 12:55:26 PM UTC 24 |
133468856 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_escalation_timeout.11780371 |
|
|
Oct 15 12:55:18 PM UTC 24 |
Oct 15 12:55:26 PM UTC 24 |
132696281 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all.3760675978 |
|
|
Oct 15 12:55:18 PM UTC 24 |
Oct 15 12:55:26 PM UTC 24 |
229774293 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_escalation_timeout.664564793 |
|
|
Oct 15 12:55:24 PM UTC 24 |
Oct 15 12:55:27 PM UTC 24 |
382601604 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset_invalid.3145459360 |
|
|
Oct 15 12:55:24 PM UTC 24 |
Oct 15 12:55:27 PM UTC 24 |
458716921 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_glitch.64861285 |
|
|
Oct 15 12:55:24 PM UTC 24 |
Oct 15 12:55:27 PM UTC 24 |
40130670 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_global_esc.3726196605 |
|
|
Oct 15 12:55:24 PM UTC 24 |
Oct 15 12:55:27 PM UTC 24 |
35924194 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_invalid.3339850698 |
|
|
Oct 15 12:55:24 PM UTC 24 |
Oct 15 12:55:27 PM UTC 24 |
41413931 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_disable_rom_integrity_check.446620318 |
|
|
Oct 15 12:55:24 PM UTC 24 |
Oct 15 12:55:27 PM UTC 24 |
57958012 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all_with_rand_reset.4178772155 |
|
|
Oct 15 12:55:13 PM UTC 24 |
Oct 15 12:55:27 PM UTC 24 |
5293348124 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.3445438697 |
|
|
Oct 15 12:55:22 PM UTC 24 |
Oct 15 12:55:28 PM UTC 24 |
39865911 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.2086249532 |
|
|
Oct 15 12:55:22 PM UTC 24 |
Oct 15 12:55:28 PM UTC 24 |
149851076 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset_invalid.508934962 |
|
|
Oct 15 12:55:13 PM UTC 24 |
Oct 15 12:55:28 PM UTC 24 |
157242433 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_disable_rom_integrity_check.1133671361 |
|
|
Oct 15 12:55:13 PM UTC 24 |
Oct 15 12:55:28 PM UTC 24 |
76192052 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_invalid.4107408515 |
|
|
Oct 15 12:55:13 PM UTC 24 |
Oct 15 12:55:28 PM UTC 24 |
73505141 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3894624833 |
|
|
Oct 15 12:55:22 PM UTC 24 |
Oct 15 12:55:28 PM UTC 24 |
142746377 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all.3128262337 |
|
|
Oct 15 12:55:25 PM UTC 24 |
Oct 15 12:55:29 PM UTC 24 |
710834694 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_invalid.1624338460 |
|
|
Oct 15 12:54:46 PM UTC 24 |
Oct 15 12:55:31 PM UTC 24 |
56802931 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_glitch.2430269120 |
|
|
Oct 15 12:55:29 PM UTC 24 |
Oct 15 12:55:32 PM UTC 24 |
29295619 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.2097988610 |
|
|
Oct 15 12:54:46 PM UTC 24 |
Oct 15 12:55:32 PM UTC 24 |
114633989 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.4207977076 |
|
|
Oct 15 12:54:46 PM UTC 24 |
Oct 15 12:55:32 PM UTC 24 |
58589922 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset_invalid.293269619 |
|
|
Oct 15 12:55:29 PM UTC 24 |
Oct 15 12:55:32 PM UTC 24 |
171588256 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.2401117949 |
|
|
Oct 15 12:55:29 PM UTC 24 |
Oct 15 12:55:32 PM UTC 24 |
82131142 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_invalid.107986986 |
|
|
Oct 15 12:55:29 PM UTC 24 |
Oct 15 12:55:32 PM UTC 24 |
79803798 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_smoke.1184838118 |
|
|
Oct 15 12:55:29 PM UTC 24 |
Oct 15 12:55:32 PM UTC 24 |
128210016 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset_invalid.1833497133 |
|
|
Oct 15 12:55:36 PM UTC 24 |
Oct 15 12:55:48 PM UTC 24 |
122933732 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset.237205449 |
|
|
Oct 15 12:55:29 PM UTC 24 |
Oct 15 12:55:32 PM UTC 24 |
54552912 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup.692288930 |
|
|
Oct 15 12:55:30 PM UTC 24 |
Oct 15 12:55:32 PM UTC 24 |
39221462 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup_reset.339457279 |
|
|
Oct 15 12:55:44 PM UTC 24 |
Oct 15 12:55:48 PM UTC 24 |
323659895 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup_reset.3376194873 |
|
|
Oct 15 12:55:30 PM UTC 24 |
Oct 15 12:55:32 PM UTC 24 |
63758098 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_smoke.4276689422 |
|
|
Oct 15 12:55:27 PM UTC 24 |
Oct 15 12:55:32 PM UTC 24 |
163592243 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_wakeup_race.2934789798 |
|
|
Oct 15 12:55:29 PM UTC 24 |
Oct 15 12:55:32 PM UTC 24 |
304840438 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.990508401 |
|
|
Oct 15 12:55:27 PM UTC 24 |
Oct 15 12:55:32 PM UTC 24 |
31889298 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset.3984077239 |
|
|
Oct 15 12:55:27 PM UTC 24 |
Oct 15 12:55:32 PM UTC 24 |
366157349 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2327046626 |
|
|
Oct 15 12:55:27 PM UTC 24 |
Oct 15 12:55:33 PM UTC 24 |
181792422 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup_reset.2123536140 |
|
|
Oct 15 12:55:27 PM UTC 24 |
Oct 15 12:55:33 PM UTC 24 |
81188196 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_wakeup_race.1558010295 |
|
|
Oct 15 12:55:27 PM UTC 24 |
Oct 15 12:55:33 PM UTC 24 |
212652420 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup.901804241 |
|
|
Oct 15 12:55:27 PM UTC 24 |
Oct 15 12:55:33 PM UTC 24 |
226385818 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.874584851 |
|
|
Oct 15 12:55:27 PM UTC 24 |
Oct 15 12:55:33 PM UTC 24 |
69879316 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_glitch.1015029768 |
|
|
Oct 15 12:55:18 PM UTC 24 |
Oct 15 12:55:33 PM UTC 24 |
62671906 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all_with_rand_reset.4099822225 |
|
|
Oct 15 12:55:18 PM UTC 24 |
Oct 15 12:55:34 PM UTC 24 |
3178768144 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_global_esc.1720626141 |
|
|
Oct 15 12:55:29 PM UTC 24 |
Oct 15 12:55:34 PM UTC 24 |
85038661 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.948168621 |
|
|
Oct 15 12:55:27 PM UTC 24 |
Oct 15 12:55:34 PM UTC 24 |
1067338636 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_disable_rom_integrity_check.4212168706 |
|
|
Oct 15 12:55:36 PM UTC 24 |
Oct 15 12:55:48 PM UTC 24 |
55618996 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.1420257208 |
|
|
Oct 15 12:55:29 PM UTC 24 |
Oct 15 12:55:34 PM UTC 24 |
200990431 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_escalation_timeout.1135950767 |
|
|
Oct 15 12:55:29 PM UTC 24 |
Oct 15 12:55:34 PM UTC 24 |
113636032 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_aborted_low_power.3849929649 |
|
|
Oct 15 12:55:32 PM UTC 24 |
Oct 15 12:55:34 PM UTC 24 |
27501561 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all_with_rand_reset.3097176504 |
|
|
Oct 15 12:55:24 PM UTC 24 |
Oct 15 12:55:34 PM UTC 24 |
2579357989 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2806791872 |
|
|
Oct 15 12:55:32 PM UTC 24 |
Oct 15 12:55:34 PM UTC 24 |
66460033 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.2426086976 |
|
|
Oct 15 12:55:32 PM UTC 24 |
Oct 15 12:55:34 PM UTC 24 |
74567406 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1590167342 |
|
|
Oct 15 12:55:27 PM UTC 24 |
Oct 15 12:55:35 PM UTC 24 |
731274923 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2292416658 |
|
|
Oct 15 12:55:32 PM UTC 24 |
Oct 15 12:55:35 PM UTC 24 |
1165033497 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2053396505 |
|
|
Oct 15 12:55:32 PM UTC 24 |
Oct 15 12:55:35 PM UTC 24 |
2230159834 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all.2665837923 |
|
|
Oct 15 12:55:29 PM UTC 24 |
Oct 15 12:55:36 PM UTC 24 |
2147132743 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.1066448466 |
|
|
Oct 15 12:54:46 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
5186512140 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_global_esc.1980821942 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
37263203 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_invalid.2757536201 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
42701581 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_escalation_timeout.3383793578 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
422657039 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_glitch.910882296 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
40899445 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.1550884762 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
154790991 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.2668482799 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
72584803 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset.3364829839 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
59131367 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.1341073137 |
|
|
Oct 15 12:55:33 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
333422268 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_smoke.3873864876 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
157256135 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_aborted_low_power.2053217828 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
33882704 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_global_esc.3115922873 |
|
|
Oct 15 12:55:35 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
44683227 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.330938585 |
|
|
Oct 15 12:55:35 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
38345739 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_wakeup_race.3592581906 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
249293254 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup_reset.1901302401 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:55:37 PM UTC 24 |
503417873 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup.997079438 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:55:38 PM UTC 24 |
184839982 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1694587903 |
|
|
Oct 15 12:55:35 PM UTC 24 |
Oct 15 12:55:39 PM UTC 24 |
1248458841 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1532345340 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:55:40 PM UTC 24 |
839157363 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all.148018554 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:55:40 PM UTC 24 |
1708236177 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_invalid.4198106891 |
|
|
Oct 15 12:55:39 PM UTC 24 |
Oct 15 12:55:42 PM UTC 24 |
42849412 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_smoke.2613886960 |
|
|
Oct 15 12:55:37 PM UTC 24 |
Oct 15 12:55:42 PM UTC 24 |
32611642 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_smoke.975186750 |
|
|
Oct 15 12:55:41 PM UTC 24 |
Oct 15 12:55:43 PM UTC 24 |
45800123 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset.3250861428 |
|
|
Oct 15 12:55:38 PM UTC 24 |
Oct 15 12:55:43 PM UTC 24 |
76768608 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup.2290509784 |
|
|
Oct 15 12:55:38 PM UTC 24 |
Oct 15 12:55:43 PM UTC 24 |
794530539 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all.2581965913 |
|
|
Oct 15 12:55:41 PM UTC 24 |
Oct 15 12:55:44 PM UTC 24 |
903498534 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_wakeup_race.211970738 |
|
|
Oct 15 12:55:38 PM UTC 24 |
Oct 15 12:55:44 PM UTC 24 |
201940754 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.3190965767 |
|
|
Oct 15 12:55:29 PM UTC 24 |
Oct 15 12:55:44 PM UTC 24 |
21646172092 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all.1080089882 |
|
|
Oct 15 12:55:37 PM UTC 24 |
Oct 15 12:55:45 PM UTC 24 |
1701932620 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.3270023827 |
|
|
Oct 15 12:55:38 PM UTC 24 |
Oct 15 12:55:46 PM UTC 24 |
237033775 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup_reset.2996947903 |
|
|
Oct 15 12:55:38 PM UTC 24 |
Oct 15 12:55:46 PM UTC 24 |
92677231 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.2187028045 |
|
|
Oct 15 12:55:38 PM UTC 24 |
Oct 15 12:55:46 PM UTC 24 |
439633772 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_aborted_low_power.4109795342 |
|
|
Oct 15 12:55:38 PM UTC 24 |
Oct 15 12:55:46 PM UTC 24 |
40117849 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.1095927675 |
|
|
Oct 15 12:55:38 PM UTC 24 |
Oct 15 12:55:47 PM UTC 24 |
28799737 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_glitch.4020881412 |
|
|
Oct 15 12:55:39 PM UTC 24 |
Oct 15 12:55:47 PM UTC 24 |
35382383 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_disable_rom_integrity_check.2936657076 |
|
|
Oct 15 12:55:39 PM UTC 24 |
Oct 15 12:55:47 PM UTC 24 |
99788259 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_global_esc.4207625307 |
|
|
Oct 15 12:55:38 PM UTC 24 |
Oct 15 12:55:47 PM UTC 24 |
50762659 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_escalation_timeout.1293414665 |
|
|
Oct 15 12:55:38 PM UTC 24 |
Oct 15 12:55:47 PM UTC 24 |
398904819 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup.1869436664 |
|
|
Oct 15 12:55:44 PM UTC 24 |
Oct 15 12:55:47 PM UTC 24 |
46609976 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_aborted_low_power.2580211463 |
|
|
Oct 15 12:55:44 PM UTC 24 |
Oct 15 12:55:47 PM UTC 24 |
99601810 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset_invalid.75269054 |
|
|
Oct 15 12:55:39 PM UTC 24 |
Oct 15 12:55:47 PM UTC 24 |
92432786 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.647558614 |
|
|
Oct 15 12:55:45 PM UTC 24 |
Oct 15 12:55:47 PM UTC 24 |
40024559 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.3043039944 |
|
|
Oct 15 12:55:45 PM UTC 24 |
Oct 15 12:55:48 PM UTC 24 |
647194040 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.4255409624 |
|
|
Oct 15 12:55:35 PM UTC 24 |
Oct 15 12:55:48 PM UTC 24 |
87546524 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_glitch.3747278235 |
|
|
Oct 15 12:55:36 PM UTC 24 |
Oct 15 12:55:48 PM UTC 24 |
51109768 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_escalation_timeout.3070395037 |
|
|
Oct 15 12:55:35 PM UTC 24 |
Oct 15 12:55:48 PM UTC 24 |
210702816 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.4035681558 |
|
|
Oct 15 12:55:35 PM UTC 24 |
Oct 15 12:55:48 PM UTC 24 |
102468369 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_invalid.2524625962 |
|
|
Oct 15 12:55:36 PM UTC 24 |
Oct 15 12:55:48 PM UTC 24 |
131866276 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1262554493 |
|
|
Oct 15 12:55:38 PM UTC 24 |
Oct 15 12:55:48 PM UTC 24 |
1289048798 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset.2731959132 |
|
|
Oct 15 12:55:43 PM UTC 24 |
Oct 15 12:55:48 PM UTC 24 |
53985873 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_wakeup_race.2629258326 |
|
|
Oct 15 12:55:43 PM UTC 24 |
Oct 15 12:55:48 PM UTC 24 |
104672677 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all_with_rand_reset.86251997 |
|
|
Oct 15 12:55:37 PM UTC 24 |
Oct 15 12:55:49 PM UTC 24 |
1756027578 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3614542722 |
|
|
Oct 15 12:55:45 PM UTC 24 |
Oct 15 12:55:49 PM UTC 24 |
1455838396 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3266288076 |
|
|
Oct 15 12:55:45 PM UTC 24 |
Oct 15 12:55:49 PM UTC 24 |
1133865370 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1441967152 |
|
|
Oct 15 12:55:38 PM UTC 24 |
Oct 15 12:55:49 PM UTC 24 |
848953450 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_glitch.3087211850 |
|
|
Oct 15 12:55:50 PM UTC 24 |
Oct 15 12:55:51 PM UTC 24 |
35263588 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_invalid.4205475650 |
|
|
Oct 15 12:55:50 PM UTC 24 |
Oct 15 12:55:51 PM UTC 24 |
137951359 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset_invalid.2735115639 |
|
|
Oct 15 12:55:50 PM UTC 24 |
Oct 15 12:55:51 PM UTC 24 |
203921117 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup.14271735 |
|
|
Oct 15 12:55:49 PM UTC 24 |
Oct 15 12:55:52 PM UTC 24 |
85737814 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_wakeup_race.3771826052 |
|
|
Oct 15 12:55:49 PM UTC 24 |
Oct 15 12:55:52 PM UTC 24 |
228023166 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_aborted_low_power.2972996876 |
|
|
Oct 15 12:55:49 PM UTC 24 |
Oct 15 12:55:52 PM UTC 24 |
54820491 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup_reset.279681902 |
|
|
Oct 15 12:55:49 PM UTC 24 |
Oct 15 12:55:52 PM UTC 24 |
222538123 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.3536030453 |
|
|
Oct 15 12:55:49 PM UTC 24 |
Oct 15 12:55:52 PM UTC 24 |
76345021 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2509151659 |
|
|
Oct 15 12:55:49 PM UTC 24 |
Oct 15 12:55:54 PM UTC 24 |
991711299 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2716415942 |
|
|
Oct 15 12:55:49 PM UTC 24 |
Oct 15 12:55:54 PM UTC 24 |
811179807 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all.2579202707 |
|
|
Oct 15 12:55:50 PM UTC 24 |
Oct 15 12:55:56 PM UTC 24 |
2270168040 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.703866227 |
|
|
Oct 15 12:55:48 PM UTC 24 |
Oct 15 12:55:56 PM UTC 24 |
94055059 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.812275691 |
|
|
Oct 15 12:56:03 PM UTC 24 |
Oct 15 12:56:05 PM UTC 24 |
100525048 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup.4147497136 |
|
|
Oct 15 12:55:52 PM UTC 24 |
Oct 15 12:55:57 PM UTC 24 |
283460296 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset.3714994549 |
|
|
Oct 15 12:55:52 PM UTC 24 |
Oct 15 12:55:57 PM UTC 24 |
111185292 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset.210105866 |
|
|
Oct 15 12:55:48 PM UTC 24 |
Oct 15 12:55:57 PM UTC 24 |
64128907 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_wakeup_race.273886412 |
|
|
Oct 15 12:55:52 PM UTC 24 |
Oct 15 12:55:57 PM UTC 24 |
245388258 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.2287064551 |
|
|
Oct 15 12:55:54 PM UTC 24 |
Oct 15 12:55:57 PM UTC 24 |
40651238 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.2743734711 |
|
|
Oct 15 12:55:55 PM UTC 24 |
Oct 15 12:55:57 PM UTC 24 |
197865892 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_aborted_low_power.952505137 |
|
|
Oct 15 12:55:53 PM UTC 24 |
Oct 15 12:55:58 PM UTC 24 |
55386332 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_global_esc.381892704 |
|
|
Oct 15 12:55:56 PM UTC 24 |
Oct 15 12:55:58 PM UTC 24 |
114043104 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup_reset.3683194020 |
|
|
Oct 15 12:55:53 PM UTC 24 |
Oct 15 12:55:58 PM UTC 24 |
192980286 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.2679909447 |
|
|
Oct 15 12:55:53 PM UTC 24 |
Oct 15 12:55:58 PM UTC 24 |
50339861 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_glitch.3102395736 |
|
|
Oct 15 12:55:58 PM UTC 24 |
Oct 15 12:55:59 PM UTC 24 |
135051183 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1612011623 |
|
|
Oct 15 12:55:53 PM UTC 24 |
Oct 15 12:55:59 PM UTC 24 |
1089914603 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_disable_rom_integrity_check.1421543028 |
|
|
Oct 15 12:55:58 PM UTC 24 |
Oct 15 12:56:00 PM UTC 24 |
51254473 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2157174843 |
|
|
Oct 15 12:55:53 PM UTC 24 |
Oct 15 12:56:00 PM UTC 24 |
1062041526 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_escalation_timeout.3599165529 |
|
|
Oct 15 12:55:58 PM UTC 24 |
Oct 15 12:56:00 PM UTC 24 |
212117813 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all_with_rand_reset.3060675884 |
|
|
Oct 15 12:55:40 PM UTC 24 |
Oct 15 12:56:00 PM UTC 24 |
12701822970 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset.19631559 |
|
|
Oct 15 12:55:59 PM UTC 24 |
Oct 15 12:56:02 PM UTC 24 |
35740682 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.4060517581 |
|
|
Oct 15 12:56:00 PM UTC 24 |
Oct 15 12:56:02 PM UTC 24 |
33181750 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.3790997877 |
|
|
Oct 15 12:55:59 PM UTC 24 |
Oct 15 12:56:02 PM UTC 24 |
113533719 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_aborted_low_power.2307544016 |
|
|
Oct 15 12:56:00 PM UTC 24 |
Oct 15 12:56:02 PM UTC 24 |
33542242 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all_with_rand_reset.3690437631 |
|
|
Oct 15 12:55:34 PM UTC 24 |
Oct 15 12:56:02 PM UTC 24 |
7877359780 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_wakeup_race.705935808 |
|
|
Oct 15 12:55:59 PM UTC 24 |
Oct 15 12:56:02 PM UTC 24 |
316243868 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.4008978958 |
|
|
Oct 15 12:55:58 PM UTC 24 |
Oct 15 12:56:05 PM UTC 24 |
1588957397 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.598347812 |
|
|
Oct 15 12:56:00 PM UTC 24 |
Oct 15 12:56:02 PM UTC 24 |
70051534 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_global_esc.3200404937 |
|
|
Oct 15 12:55:50 PM UTC 24 |
Oct 15 12:56:02 PM UTC 24 |
27600803 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.839540313 |
|
|
Oct 15 12:55:49 PM UTC 24 |
Oct 15 12:56:02 PM UTC 24 |
30746915 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup_reset.3313554455 |
|
|
Oct 15 12:55:59 PM UTC 24 |
Oct 15 12:56:02 PM UTC 24 |
281474145 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_glitch.3988454948 |
|
|
Oct 15 12:55:48 PM UTC 24 |
Oct 15 12:56:02 PM UTC 24 |
61897203 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_invalid.647456626 |
|
|
Oct 15 12:55:58 PM UTC 24 |
Oct 15 12:56:03 PM UTC 24 |
38708702 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_disable_rom_integrity_check.2414847911 |
|
|
Oct 15 12:55:48 PM UTC 24 |
Oct 15 12:56:03 PM UTC 24 |
64315858 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_disable_rom_integrity_check.1767544693 |
|
|
Oct 15 12:55:50 PM UTC 24 |
Oct 15 12:56:03 PM UTC 24 |
58136076 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_invalid.3387583977 |
|
|
Oct 15 12:56:03 PM UTC 24 |
Oct 15 12:56:05 PM UTC 24 |
43962722 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.112099245 |
|
|
Oct 15 12:56:03 PM UTC 24 |
Oct 15 12:56:05 PM UTC 24 |
274788661 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset_invalid.3436370517 |
|
|
Oct 15 12:55:58 PM UTC 24 |
Oct 15 12:56:03 PM UTC 24 |
167206328 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_smoke.3353246235 |
|
|
Oct 15 12:55:51 PM UTC 24 |
Oct 15 12:56:03 PM UTC 24 |
38482281 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_global_esc.3610284356 |
|
|
Oct 15 12:55:48 PM UTC 24 |
Oct 15 12:56:03 PM UTC 24 |
77403559 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_escalation_timeout.1367693941 |
|
|
Oct 15 12:55:50 PM UTC 24 |
Oct 15 12:56:03 PM UTC 24 |
200018348 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.3556844111 |
|
|
Oct 15 12:55:49 PM UTC 24 |
Oct 15 12:56:03 PM UTC 24 |
260609396 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_invalid.1420603306 |
|
|
Oct 15 12:55:48 PM UTC 24 |
Oct 15 12:56:03 PM UTC 24 |
66830907 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3792905004 |
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|
Oct 15 12:56:00 PM UTC 24 |
Oct 15 12:56:03 PM UTC 24 |
2015428756 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_smoke.431515376 |
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|
Oct 15 12:55:48 PM UTC 24 |
Oct 15 12:56:03 PM UTC 24 |
29383181 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.974463183 |
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|
Oct 15 12:55:58 PM UTC 24 |
Oct 15 12:56:03 PM UTC 24 |
63135766 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset_invalid.3089280198 |
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|
Oct 15 12:55:48 PM UTC 24 |
Oct 15 12:56:03 PM UTC 24 |
118571135 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.207424323 |
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|
Oct 15 12:56:00 PM UTC 24 |
Oct 15 12:56:03 PM UTC 24 |
2864018886 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.2376187392 |
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|
Oct 15 12:56:01 PM UTC 24 |
Oct 15 12:56:04 PM UTC 24 |
360591011 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.1835985984 |
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|
Oct 15 12:55:50 PM UTC 24 |
Oct 15 12:56:04 PM UTC 24 |
26825825040 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_glitch.2866028952 |
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|
Oct 15 12:56:03 PM UTC 24 |
Oct 15 12:56:04 PM UTC 24 |
55887100 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_global_esc.3325361242 |
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|
Oct 15 12:56:03 PM UTC 24 |
Oct 15 12:56:04 PM UTC 24 |
44444237 ps |