| T801 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.1645090049 |
|
|
Oct 15 12:56:03 PM UTC 24 |
Oct 15 12:56:05 PM UTC 24 |
49132718 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_disable_rom_integrity_check.1929496000 |
|
|
Oct 15 12:56:03 PM UTC 24 |
Oct 15 12:56:05 PM UTC 24 |
61551036 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_escalation_timeout.2860455073 |
|
|
Oct 15 12:56:03 PM UTC 24 |
Oct 15 12:56:05 PM UTC 24 |
204298449 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.1004830736 |
|
|
Oct 15 12:56:04 PM UTC 24 |
Oct 15 12:56:06 PM UTC 24 |
50972820 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.2912411446 |
|
|
Oct 15 12:56:04 PM UTC 24 |
Oct 15 12:56:06 PM UTC 24 |
70245484 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.2923610356 |
|
|
Oct 15 12:56:04 PM UTC 24 |
Oct 15 12:56:06 PM UTC 24 |
333099134 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.2323221888 |
|
|
Oct 15 12:56:04 PM UTC 24 |
Oct 15 12:56:06 PM UTC 24 |
34710336 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.1064253654 |
|
|
Oct 15 12:56:04 PM UTC 24 |
Oct 15 12:56:06 PM UTC 24 |
88772692 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.2649890786 |
|
|
Oct 15 12:56:05 PM UTC 24 |
Oct 15 12:56:07 PM UTC 24 |
39054301 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.4003240887 |
|
|
Oct 15 12:56:04 PM UTC 24 |
Oct 15 12:56:07 PM UTC 24 |
134312977 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_invalid.293728743 |
|
|
Oct 15 12:56:05 PM UTC 24 |
Oct 15 12:56:07 PM UTC 24 |
45139681 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.4217807899 |
|
|
Oct 15 12:56:04 PM UTC 24 |
Oct 15 12:56:07 PM UTC 24 |
289170917 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.981927287 |
|
|
Oct 15 12:56:05 PM UTC 24 |
Oct 15 12:56:07 PM UTC 24 |
65974290 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.1466965453 |
|
|
Oct 15 12:56:04 PM UTC 24 |
Oct 15 12:56:07 PM UTC 24 |
42981417 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.936724783 |
|
|
Oct 15 12:56:05 PM UTC 24 |
Oct 15 12:56:07 PM UTC 24 |
202256436 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.14790901 |
|
|
Oct 15 12:56:05 PM UTC 24 |
Oct 15 12:56:07 PM UTC 24 |
100432268 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all.1683989634 |
|
|
Oct 15 12:55:48 PM UTC 24 |
Oct 15 12:56:07 PM UTC 24 |
2001107236 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.2682680633 |
|
|
Oct 15 12:56:14 PM UTC 24 |
Oct 15 12:56:22 PM UTC 24 |
250347469 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.453207813 |
|
|
Oct 15 12:56:04 PM UTC 24 |
Oct 15 12:56:08 PM UTC 24 |
1258471710 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.3381007571 |
|
|
Oct 15 12:56:06 PM UTC 24 |
Oct 15 12:56:08 PM UTC 24 |
31981138 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.538026814 |
|
|
Oct 15 12:56:06 PM UTC 24 |
Oct 15 12:56:08 PM UTC 24 |
36708238 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.2396690632 |
|
|
Oct 15 12:56:06 PM UTC 24 |
Oct 15 12:56:08 PM UTC 24 |
205901385 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.3546475082 |
|
|
Oct 15 12:56:03 PM UTC 24 |
Oct 15 12:56:08 PM UTC 24 |
4879306537 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.4193090770 |
|
|
Oct 15 12:56:06 PM UTC 24 |
Oct 15 12:56:08 PM UTC 24 |
193409581 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.2119637782 |
|
|
Oct 15 12:56:06 PM UTC 24 |
Oct 15 12:56:08 PM UTC 24 |
322457172 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.1710396632 |
|
|
Oct 15 12:56:06 PM UTC 24 |
Oct 15 12:56:09 PM UTC 24 |
303381819 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.896796072 |
|
|
Oct 15 12:56:04 PM UTC 24 |
Oct 15 12:56:09 PM UTC 24 |
802470704 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.1203405647 |
|
|
Oct 15 12:55:48 PM UTC 24 |
Oct 15 12:56:09 PM UTC 24 |
11356127293 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.722344287 |
|
|
Oct 15 12:56:06 PM UTC 24 |
Oct 15 12:56:10 PM UTC 24 |
501640347 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2029006808 |
|
|
Oct 15 12:56:06 PM UTC 24 |
Oct 15 12:56:10 PM UTC 24 |
1061450723 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2432997040 |
|
|
Oct 15 12:56:06 PM UTC 24 |
Oct 15 12:56:11 PM UTC 24 |
854978393 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3374554019 |
|
|
Oct 15 12:56:06 PM UTC 24 |
Oct 15 12:56:11 PM UTC 24 |
54421423 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.1089479102 |
|
|
Oct 15 12:56:19 PM UTC 24 |
Oct 15 12:56:21 PM UTC 24 |
48709193 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.2893670387 |
|
|
Oct 15 12:56:09 PM UTC 24 |
Oct 15 12:56:12 PM UTC 24 |
37158710 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.3769325190 |
|
|
Oct 15 12:56:09 PM UTC 24 |
Oct 15 12:56:12 PM UTC 24 |
34779055 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.1386821357 |
|
|
Oct 15 12:56:09 PM UTC 24 |
Oct 15 12:56:12 PM UTC 24 |
29000570 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.2548838610 |
|
|
Oct 15 12:56:09 PM UTC 24 |
Oct 15 12:56:12 PM UTC 24 |
23188504 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.1431322017 |
|
|
Oct 15 12:56:11 PM UTC 24 |
Oct 15 12:56:12 PM UTC 24 |
115773185 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.387444395 |
|
|
Oct 15 12:56:10 PM UTC 24 |
Oct 15 12:56:12 PM UTC 24 |
361374594 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.2694934305 |
|
|
Oct 15 12:56:08 PM UTC 24 |
Oct 15 12:56:13 PM UTC 24 |
26189781 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.4257040844 |
|
|
Oct 15 12:56:10 PM UTC 24 |
Oct 15 12:56:13 PM UTC 24 |
134084296 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.3963192725 |
|
|
Oct 15 12:56:10 PM UTC 24 |
Oct 15 12:56:13 PM UTC 24 |
332592570 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.1874966483 |
|
|
Oct 15 12:56:08 PM UTC 24 |
Oct 15 12:56:13 PM UTC 24 |
38362391 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.1608553261 |
|
|
Oct 15 12:56:11 PM UTC 24 |
Oct 15 12:56:13 PM UTC 24 |
72397766 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.820447856 |
|
|
Oct 15 12:56:09 PM UTC 24 |
Oct 15 12:56:13 PM UTC 24 |
100622898 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.4124256913 |
|
|
Oct 15 12:56:08 PM UTC 24 |
Oct 15 12:56:13 PM UTC 24 |
95171244 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_invalid.2870212894 |
|
|
Oct 15 12:56:08 PM UTC 24 |
Oct 15 12:56:13 PM UTC 24 |
56055754 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.1489910989 |
|
|
Oct 15 12:56:11 PM UTC 24 |
Oct 15 12:56:13 PM UTC 24 |
171107620 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.2155418231 |
|
|
Oct 15 12:56:08 PM UTC 24 |
Oct 15 12:56:13 PM UTC 24 |
51166680 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.518753039 |
|
|
Oct 15 12:56:08 PM UTC 24 |
Oct 15 12:56:13 PM UTC 24 |
490413369 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.208852335 |
|
|
Oct 15 12:56:08 PM UTC 24 |
Oct 15 12:56:13 PM UTC 24 |
157626777 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.2070038003 |
|
|
Oct 15 12:56:08 PM UTC 24 |
Oct 15 12:56:13 PM UTC 24 |
252853259 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.2478819812 |
|
|
Oct 15 12:56:13 PM UTC 24 |
Oct 15 12:56:21 PM UTC 24 |
65014977 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.113423497 |
|
|
Oct 15 12:56:09 PM UTC 24 |
Oct 15 12:56:14 PM UTC 24 |
980027058 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.183593710 |
|
|
Oct 15 12:56:09 PM UTC 24 |
Oct 15 12:56:14 PM UTC 24 |
1436934769 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.1349660788 |
|
|
Oct 15 12:56:08 PM UTC 24 |
Oct 15 12:56:16 PM UTC 24 |
161377987 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.4207288707 |
|
|
Oct 15 12:56:08 PM UTC 24 |
Oct 15 12:56:16 PM UTC 24 |
31697923 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.4234170976 |
|
|
Oct 15 12:56:15 PM UTC 24 |
Oct 15 12:56:17 PM UTC 24 |
55691902 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.4272678985 |
|
|
Oct 15 12:56:15 PM UTC 24 |
Oct 15 12:56:17 PM UTC 24 |
92881281 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_invalid.2506308696 |
|
|
Oct 15 12:56:15 PM UTC 24 |
Oct 15 12:56:17 PM UTC 24 |
42802247 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.3922652926 |
|
|
Oct 15 12:56:15 PM UTC 24 |
Oct 15 12:56:17 PM UTC 24 |
51549159 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.4084944040 |
|
|
Oct 15 12:56:15 PM UTC 24 |
Oct 15 12:56:17 PM UTC 24 |
109625860 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.3418532698 |
|
|
Oct 15 12:56:15 PM UTC 24 |
Oct 15 12:56:17 PM UTC 24 |
113134217 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_invalid.3026943852 |
|
|
Oct 15 12:56:12 PM UTC 24 |
Oct 15 12:56:17 PM UTC 24 |
45481574 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.2539513010 |
|
|
Oct 15 12:56:05 PM UTC 24 |
Oct 15 12:56:17 PM UTC 24 |
4401233363 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.1418589207 |
|
|
Oct 15 12:55:58 PM UTC 24 |
Oct 15 12:56:18 PM UTC 24 |
5346957381 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.888937450 |
|
|
Oct 15 12:56:13 PM UTC 24 |
Oct 15 12:56:18 PM UTC 24 |
69554639 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.481032808 |
|
|
Oct 15 12:56:15 PM UTC 24 |
Oct 15 12:56:19 PM UTC 24 |
1361343029 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.3413335865 |
|
|
Oct 15 12:56:13 PM UTC 24 |
Oct 15 12:56:21 PM UTC 24 |
62964379 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.1093967379 |
|
|
Oct 15 12:56:13 PM UTC 24 |
Oct 15 12:56:21 PM UTC 24 |
37538748 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.495763559 |
|
|
Oct 15 12:56:13 PM UTC 24 |
Oct 15 12:56:21 PM UTC 24 |
178650914 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.2113727735 |
|
|
Oct 15 12:56:19 PM UTC 24 |
Oct 15 12:56:21 PM UTC 24 |
60412571 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.307348375 |
|
|
Oct 15 12:56:13 PM UTC 24 |
Oct 15 12:56:21 PM UTC 24 |
111770780 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.1192787480 |
|
|
Oct 15 12:56:13 PM UTC 24 |
Oct 15 12:56:21 PM UTC 24 |
29824496 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.827002068 |
|
|
Oct 15 12:56:14 PM UTC 24 |
Oct 15 12:56:22 PM UTC 24 |
25082809 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.3422922007 |
|
|
Oct 15 12:56:20 PM UTC 24 |
Oct 15 12:56:22 PM UTC 24 |
70165619 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.877891470 |
|
|
Oct 15 12:56:19 PM UTC 24 |
Oct 15 12:56:22 PM UTC 24 |
1020161130 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.892962561 |
|
|
Oct 15 12:56:13 PM UTC 24 |
Oct 15 12:56:22 PM UTC 24 |
594048588 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.880771692 |
|
|
Oct 15 12:56:13 PM UTC 24 |
Oct 15 12:56:22 PM UTC 24 |
173102800 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.4263845957 |
|
|
Oct 15 12:56:14 PM UTC 24 |
Oct 15 12:56:22 PM UTC 24 |
213513567 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.3698444531 |
|
|
Oct 15 12:56:17 PM UTC 24 |
Oct 15 12:56:22 PM UTC 24 |
95142505 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.1156526404 |
|
|
Oct 15 12:56:17 PM UTC 24 |
Oct 15 12:56:22 PM UTC 24 |
57945040 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.744379165 |
|
|
Oct 15 12:56:17 PM UTC 24 |
Oct 15 12:56:22 PM UTC 24 |
63284478 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.773565488 |
|
|
Oct 15 12:56:17 PM UTC 24 |
Oct 15 12:56:22 PM UTC 24 |
132280038 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.1996121983 |
|
|
Oct 15 12:56:17 PM UTC 24 |
Oct 15 12:56:22 PM UTC 24 |
69190563 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.3056190028 |
|
|
Oct 15 12:56:17 PM UTC 24 |
Oct 15 12:56:22 PM UTC 24 |
144481185 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1637550756 |
|
|
Oct 15 12:56:13 PM UTC 24 |
Oct 15 12:56:23 PM UTC 24 |
1219652732 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.1101376310 |
|
|
Oct 15 12:56:08 PM UTC 24 |
Oct 15 12:56:23 PM UTC 24 |
54425054 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.717990709 |
|
|
Oct 15 12:56:17 PM UTC 24 |
Oct 15 12:56:23 PM UTC 24 |
181221505 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2711722861 |
|
|
Oct 15 12:56:13 PM UTC 24 |
Oct 15 12:56:23 PM UTC 24 |
1277490246 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.423988280 |
|
|
Oct 15 12:56:17 PM UTC 24 |
Oct 15 12:56:24 PM UTC 24 |
920288825 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3661419274 |
|
|
Oct 15 12:56:17 PM UTC 24 |
Oct 15 12:56:25 PM UTC 24 |
828981908 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.1845658583 |
|
|
Oct 15 12:56:08 PM UTC 24 |
Oct 15 12:56:26 PM UTC 24 |
1389889589 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_global_esc.3895259776 |
|
|
Oct 15 12:56:24 PM UTC 24 |
Oct 15 12:56:26 PM UTC 24 |
81353145 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.2106665955 |
|
|
Oct 15 12:56:24 PM UTC 24 |
Oct 15 12:56:26 PM UTC 24 |
31052176 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1159297425 |
|
|
Oct 15 12:56:24 PM UTC 24 |
Oct 15 12:56:27 PM UTC 24 |
378118574 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.201521221 |
|
|
Oct 15 12:56:24 PM UTC 24 |
Oct 15 12:56:27 PM UTC 24 |
30568593 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_invalid.687169021 |
|
|
Oct 15 12:56:22 PM UTC 24 |
Oct 15 12:56:27 PM UTC 24 |
80784997 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.1987110480 |
|
|
Oct 15 12:56:12 PM UTC 24 |
Oct 15 12:56:27 PM UTC 24 |
8956758925 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.2685703826 |
|
|
Oct 15 12:56:24 PM UTC 24 |
Oct 15 12:56:27 PM UTC 24 |
353792353 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.2867184033 |
|
|
Oct 15 12:56:24 PM UTC 24 |
Oct 15 12:56:27 PM UTC 24 |
136142791 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_invalid.965945645 |
|
|
Oct 15 12:56:24 PM UTC 24 |
Oct 15 12:56:27 PM UTC 24 |
120097747 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.3529947287 |
|
|
Oct 15 12:56:24 PM UTC 24 |
Oct 15 12:56:27 PM UTC 24 |
38598111 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.388989072 |
|
|
Oct 15 12:56:24 PM UTC 24 |
Oct 15 12:56:27 PM UTC 24 |
64913077 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.2055561762 |
|
|
Oct 15 12:56:24 PM UTC 24 |
Oct 15 12:56:27 PM UTC 24 |
103254275 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset.3354479009 |
|
|
Oct 15 12:56:24 PM UTC 24 |
Oct 15 12:56:27 PM UTC 24 |
58636539 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.4139683948 |
|
|
Oct 15 12:56:15 PM UTC 24 |
Oct 15 12:56:27 PM UTC 24 |
8048905980 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset_invalid.2401026580 |
|
|
Oct 15 12:56:22 PM UTC 24 |
Oct 15 12:56:27 PM UTC 24 |
113252149 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.808352622 |
|
|
Oct 15 12:56:24 PM UTC 24 |
Oct 15 12:56:28 PM UTC 24 |
430958087 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.456949130 |
|
|
Oct 15 12:56:08 PM UTC 24 |
Oct 15 12:56:31 PM UTC 24 |
4507055405 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.1243622926 |
|
|
Oct 15 12:56:29 PM UTC 24 |
Oct 15 12:56:32 PM UTC 24 |
28112105 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.1640660105 |
|
|
Oct 15 12:56:29 PM UTC 24 |
Oct 15 12:56:32 PM UTC 24 |
48673006 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.4114208899 |
|
|
Oct 15 12:56:28 PM UTC 24 |
Oct 15 12:56:33 PM UTC 24 |
46595539 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_glitch.2941087719 |
|
|
Oct 15 12:56:28 PM UTC 24 |
Oct 15 12:56:33 PM UTC 24 |
68431275 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.2019048717 |
|
|
Oct 15 12:56:28 PM UTC 24 |
Oct 15 12:56:33 PM UTC 24 |
78298016 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.363405850 |
|
|
Oct 15 12:56:28 PM UTC 24 |
Oct 15 12:56:33 PM UTC 24 |
151776599 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1656127554 |
|
|
Oct 15 12:56:28 PM UTC 24 |
Oct 15 12:56:33 PM UTC 24 |
168504850 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.1669894676 |
|
|
Oct 15 12:56:28 PM UTC 24 |
Oct 15 12:56:33 PM UTC 24 |
24425784 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.1506587350 |
|
|
Oct 15 12:56:28 PM UTC 24 |
Oct 15 12:56:33 PM UTC 24 |
464924069 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_invalid.2970151094 |
|
|
Oct 15 12:56:28 PM UTC 24 |
Oct 15 12:56:33 PM UTC 24 |
77843719 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.3188422951 |
|
|
Oct 15 12:56:28 PM UTC 24 |
Oct 15 12:56:33 PM UTC 24 |
205536528 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.3836064076 |
|
|
Oct 15 12:56:28 PM UTC 24 |
Oct 15 12:56:33 PM UTC 24 |
101747590 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1184763200 |
|
|
Oct 15 12:56:28 PM UTC 24 |
Oct 15 12:56:34 PM UTC 24 |
1009524044 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3082024631 |
|
|
Oct 15 12:56:28 PM UTC 24 |
Oct 15 12:56:34 PM UTC 24 |
1746063523 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_smoke.3259034889 |
|
|
Oct 15 12:56:22 PM UTC 24 |
Oct 15 12:56:34 PM UTC 24 |
29237785 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all.4254489891 |
|
|
Oct 15 12:56:22 PM UTC 24 |
Oct 15 12:56:37 PM UTC 24 |
1470497710 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset.4038363430 |
|
|
Oct 15 12:56:22 PM UTC 24 |
Oct 15 12:56:34 PM UTC 24 |
38383424 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.2255022968 |
|
|
Oct 15 12:56:32 PM UTC 24 |
Oct 15 12:56:34 PM UTC 24 |
33668125 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all_with_rand_reset.1552198518 |
|
|
Oct 15 12:56:22 PM UTC 24 |
Oct 15 12:56:36 PM UTC 24 |
4624570523 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.3737054588 |
|
|
Oct 15 12:56:32 PM UTC 24 |
Oct 15 12:56:34 PM UTC 24 |
252444518 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.1729358840 |
|
|
Oct 15 12:56:22 PM UTC 24 |
Oct 15 12:56:34 PM UTC 24 |
64131820 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.1243418842 |
|
|
Oct 15 12:56:32 PM UTC 24 |
Oct 15 12:56:34 PM UTC 24 |
280927785 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.1320076552 |
|
|
Oct 15 12:56:25 PM UTC 24 |
Oct 15 12:56:35 PM UTC 24 |
144152035 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.1757154664 |
|
|
Oct 15 12:56:22 PM UTC 24 |
Oct 15 12:56:35 PM UTC 24 |
276987505 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_wakeup_race.1303493783 |
|
|
Oct 15 12:56:22 PM UTC 24 |
Oct 15 12:56:35 PM UTC 24 |
273716746 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.603549491 |
|
|
Oct 15 12:56:25 PM UTC 24 |
Oct 15 12:56:35 PM UTC 24 |
339956374 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.3524038121 |
|
|
Oct 15 12:56:22 PM UTC 24 |
Oct 15 12:56:35 PM UTC 24 |
262484551 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.997755298 |
|
|
Oct 15 12:56:34 PM UTC 24 |
Oct 15 12:56:35 PM UTC 24 |
93482524 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.541900827 |
|
|
Oct 15 12:56:33 PM UTC 24 |
Oct 15 12:56:35 PM UTC 24 |
28977250 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.4294442427 |
|
|
Oct 15 12:56:34 PM UTC 24 |
Oct 15 12:56:35 PM UTC 24 |
312813277 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.1542988258 |
|
|
Oct 15 12:56:34 PM UTC 24 |
Oct 15 12:56:35 PM UTC 24 |
39850290 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.1707949082 |
|
|
Oct 15 12:56:34 PM UTC 24 |
Oct 15 12:56:36 PM UTC 24 |
406821612 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.810563983 |
|
|
Oct 15 12:56:34 PM UTC 24 |
Oct 15 12:56:36 PM UTC 24 |
22780588 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.2804919774 |
|
|
Oct 15 12:56:26 PM UTC 24 |
Oct 15 12:56:36 PM UTC 24 |
159561608 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.2332674273 |
|
|
Oct 15 12:56:34 PM UTC 24 |
Oct 15 12:56:36 PM UTC 24 |
61669021 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.2705662215 |
|
|
Oct 15 12:56:24 PM UTC 24 |
Oct 15 12:56:36 PM UTC 24 |
6803870570 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.854732178 |
|
|
Oct 15 12:56:34 PM UTC 24 |
Oct 15 12:56:36 PM UTC 24 |
65713862 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1175712129 |
|
|
Oct 15 12:56:22 PM UTC 24 |
Oct 15 12:56:36 PM UTC 24 |
1490236844 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3561502030 |
|
|
Oct 15 12:56:22 PM UTC 24 |
Oct 15 12:56:37 PM UTC 24 |
1051396754 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.1739331265 |
|
|
Oct 15 12:56:35 PM UTC 24 |
Oct 15 12:56:37 PM UTC 24 |
117065143 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.2739965905 |
|
|
Oct 15 12:56:35 PM UTC 24 |
Oct 15 12:56:37 PM UTC 24 |
273210952 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.3936589801 |
|
|
Oct 15 12:56:35 PM UTC 24 |
Oct 15 12:56:37 PM UTC 24 |
88297154 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.1265269835 |
|
|
Oct 15 12:56:35 PM UTC 24 |
Oct 15 12:56:37 PM UTC 24 |
86161777 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.3292001431 |
|
|
Oct 15 12:56:35 PM UTC 24 |
Oct 15 12:56:37 PM UTC 24 |
66728249 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1367713304 |
|
|
Oct 15 12:56:33 PM UTC 24 |
Oct 15 12:56:37 PM UTC 24 |
1055377899 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.3915175036 |
|
|
Oct 15 12:56:35 PM UTC 24 |
Oct 15 12:56:37 PM UTC 24 |
38310106 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.325315634 |
|
|
Oct 15 12:56:35 PM UTC 24 |
Oct 15 12:56:37 PM UTC 24 |
87582882 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.3257581606 |
|
|
Oct 15 12:56:35 PM UTC 24 |
Oct 15 12:56:37 PM UTC 24 |
342114518 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2104297693 |
|
|
Oct 15 12:56:33 PM UTC 24 |
Oct 15 12:56:38 PM UTC 24 |
841106294 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.3803822096 |
|
|
Oct 15 12:56:28 PM UTC 24 |
Oct 15 12:56:39 PM UTC 24 |
1810034638 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.1887862344 |
|
|
Oct 15 12:56:37 PM UTC 24 |
Oct 15 12:56:39 PM UTC 24 |
29194331 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3471339023 |
|
|
Oct 15 12:56:37 PM UTC 24 |
Oct 15 12:56:39 PM UTC 24 |
88919454 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.3522463711 |
|
|
Oct 15 12:56:37 PM UTC 24 |
Oct 15 12:56:39 PM UTC 24 |
72212993 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.348022530 |
|
|
Oct 15 12:56:37 PM UTC 24 |
Oct 15 12:56:39 PM UTC 24 |
67514756 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.4104373411 |
|
|
Oct 15 12:56:37 PM UTC 24 |
Oct 15 12:56:39 PM UTC 24 |
94223372 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.3790202549 |
|
|
Oct 15 12:56:37 PM UTC 24 |
Oct 15 12:56:39 PM UTC 24 |
80574370 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.1364027538 |
|
|
Oct 15 12:56:38 PM UTC 24 |
Oct 15 12:56:39 PM UTC 24 |
59211454 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.1479634748 |
|
|
Oct 15 12:56:37 PM UTC 24 |
Oct 15 12:56:39 PM UTC 24 |
108465799 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_invalid.2917430201 |
|
|
Oct 15 12:56:37 PM UTC 24 |
Oct 15 12:56:39 PM UTC 24 |
52917535 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.803137143 |
|
|
Oct 15 12:56:38 PM UTC 24 |
Oct 15 12:56:39 PM UTC 24 |
142947881 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.3841074400 |
|
|
Oct 15 12:56:38 PM UTC 24 |
Oct 15 12:56:39 PM UTC 24 |
43112293 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.1110431919 |
|
|
Oct 15 12:56:37 PM UTC 24 |
Oct 15 12:56:40 PM UTC 24 |
111580035 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1119447861 |
|
|
Oct 15 12:56:37 PM UTC 24 |
Oct 15 12:56:40 PM UTC 24 |
1123829978 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.2262934970 |
|
|
Oct 15 12:56:38 PM UTC 24 |
Oct 15 12:56:40 PM UTC 24 |
84022996 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.3721094430 |
|
|
Oct 15 12:56:35 PM UTC 24 |
Oct 15 12:56:40 PM UTC 24 |
2709543869 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.2613024115 |
|
|
Oct 15 12:56:28 PM UTC 24 |
Oct 15 12:56:40 PM UTC 24 |
2441443318 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.328862740 |
|
|
Oct 15 12:56:37 PM UTC 24 |
Oct 15 12:56:41 PM UTC 24 |
1390851456 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.3720440308 |
|
|
Oct 15 12:56:39 PM UTC 24 |
Oct 15 12:56:41 PM UTC 24 |
165187377 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.934330386 |
|
|
Oct 15 12:56:39 PM UTC 24 |
Oct 15 12:56:41 PM UTC 24 |
425082217 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.1384608795 |
|
|
Oct 15 12:56:39 PM UTC 24 |
Oct 15 12:56:41 PM UTC 24 |
69394799 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.2381340938 |
|
|
Oct 15 12:56:39 PM UTC 24 |
Oct 15 12:56:41 PM UTC 24 |
96257828 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.560077957 |
|
|
Oct 15 12:56:39 PM UTC 24 |
Oct 15 12:56:41 PM UTC 24 |
51839420 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.2181875808 |
|
|
Oct 15 12:56:39 PM UTC 24 |
Oct 15 12:56:41 PM UTC 24 |
110903392 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.666226330 |
|
|
Oct 15 12:56:39 PM UTC 24 |
Oct 15 12:56:41 PM UTC 24 |
171120313 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.791153382 |
|
|
Oct 15 12:56:39 PM UTC 24 |
Oct 15 12:56:41 PM UTC 24 |
47642990 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.855188969 |
|
|
Oct 15 12:56:39 PM UTC 24 |
Oct 15 12:56:41 PM UTC 24 |
405014078 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1518330727 |
|
|
Oct 15 12:56:39 PM UTC 24 |
Oct 15 12:56:42 PM UTC 24 |
52123476 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_invalid.1010029307 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:43 PM UTC 24 |
135042359 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.4118874699 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:43 PM UTC 24 |
105774667 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.232108535 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:43 PM UTC 24 |
228524687 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1362132404 |
|
|
Oct 15 12:56:39 PM UTC 24 |
Oct 15 12:56:43 PM UTC 24 |
840014491 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3584727402 |
|
|
Oct 15 12:56:39 PM UTC 24 |
Oct 15 12:56:44 PM UTC 24 |
869945830 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all_with_rand_reset.3633744323 |
|
|
Oct 15 12:56:37 PM UTC 24 |
Oct 15 12:56:46 PM UTC 24 |
6436660700 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.1623201673 |
|
|
Oct 15 12:56:35 PM UTC 24 |
Oct 15 12:56:49 PM UTC 24 |
3527172335 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.401310054 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:56 PM UTC 24 |
15292955923 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.114275661 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:43 PM UTC 24 |
66085138 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.2793102892 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:43 PM UTC 24 |
26036113 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.3713611579 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:43 PM UTC 24 |
19406672 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.1017808238 |
|
|
Oct 15 12:56:46 PM UTC 24 |
Oct 15 12:57:06 PM UTC 24 |
35148011 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.2089419349 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:43 PM UTC 24 |
34764737 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.1697597724 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:43 PM UTC 24 |
56637410 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3869130590 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:43 PM UTC 24 |
282026325 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3605029171 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:43 PM UTC 24 |
49414947 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2274829983 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:43 PM UTC 24 |
42795298 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3174105069 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:43 PM UTC 24 |
239418184 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.2062816585 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:44 PM UTC 24 |
32419980 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2194057208 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:44 PM UTC 24 |
32215626 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3060720697 |
|
|
Oct 15 12:56:41 PM UTC 24 |
Oct 15 12:56:44 PM UTC 24 |
119753021 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.3802345838 |
|
|
Oct 15 12:56:43 PM UTC 24 |
Oct 15 12:56:44 PM UTC 24 |
40285066 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2574342048 |
|
|
Oct 15 12:56:42 PM UTC 24 |
Oct 15 12:56:44 PM UTC 24 |
66104874 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.1480444226 |
|
|
Oct 15 12:56:43 PM UTC 24 |
Oct 15 12:56:45 PM UTC 24 |
28309469 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1629243246 |
|
|
Oct 15 12:56:43 PM UTC 24 |
Oct 15 12:56:45 PM UTC 24 |
69608796 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2795065393 |
|
|
Oct 15 12:56:43 PM UTC 24 |
Oct 15 12:56:45 PM UTC 24 |
88894218 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.3027453797 |
|
|
Oct 15 12:56:43 PM UTC 24 |
Oct 15 12:56:45 PM UTC 24 |
50608803 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.960725232 |
|
|
Oct 15 12:56:43 PM UTC 24 |
Oct 15 12:56:45 PM UTC 24 |
59162527 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3940825935 |
|
|
Oct 15 12:56:43 PM UTC 24 |
Oct 15 12:56:45 PM UTC 24 |
89622765 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2080984123 |
|
|
Oct 15 12:56:43 PM UTC 24 |
Oct 15 12:56:45 PM UTC 24 |
157125670 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2077321573 |
|
|
Oct 15 12:56:43 PM UTC 24 |
Oct 15 12:56:45 PM UTC 24 |
380727308 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.1515432964 |
|
|
Oct 15 12:56:43 PM UTC 24 |
Oct 15 12:56:46 PM UTC 24 |
157098048 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.338076760 |
|
|
Oct 15 12:56:44 PM UTC 24 |
Oct 15 12:56:46 PM UTC 24 |
25490814 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.5143723 |
|
|
Oct 15 12:56:44 PM UTC 24 |
Oct 15 12:56:46 PM UTC 24 |
45588958 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.1327967499 |
|
|
Oct 15 12:56:44 PM UTC 24 |
Oct 15 12:56:46 PM UTC 24 |
102667318 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.1283980162 |
|
|
Oct 15 12:56:45 PM UTC 24 |
Oct 15 12:56:46 PM UTC 24 |
23733863 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.4241299490 |
|
|
Oct 15 12:56:45 PM UTC 24 |
Oct 15 12:56:46 PM UTC 24 |
31599839 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.384359564 |
|
|
Oct 15 12:56:43 PM UTC 24 |
Oct 15 12:56:46 PM UTC 24 |
215722012 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.1684090331 |
|
|
Oct 15 12:56:50 PM UTC 24 |
Oct 15 12:56:52 PM UTC 24 |
29724441 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2413097442 |
|
|
Oct 15 12:56:45 PM UTC 24 |
Oct 15 12:57:05 PM UTC 24 |
210395365 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.1121341324 |
|
|
Oct 15 12:56:46 PM UTC 24 |
Oct 15 12:57:06 PM UTC 24 |
36913939 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.1727265933 |
|
|
Oct 15 12:56:48 PM UTC 24 |
Oct 15 12:56:56 PM UTC 24 |
54087618 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.3036078251 |
|
|
Oct 15 12:56:46 PM UTC 24 |
Oct 15 12:57:07 PM UTC 24 |
417613088 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.415336058 |
|
|
Oct 15 12:56:48 PM UTC 24 |
Oct 15 12:56:57 PM UTC 24 |
66735076 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.578661537 |
|
|
Oct 15 12:56:52 PM UTC 24 |
Oct 15 12:56:57 PM UTC 24 |
33815841 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.1253993971 |
|
|
Oct 15 12:56:44 PM UTC 24 |
Oct 15 12:56:57 PM UTC 24 |
21107897 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2604876752 |
|
|
Oct 15 12:56:48 PM UTC 24 |
Oct 15 12:56:58 PM UTC 24 |
203950066 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.3909928460 |
|
|
Oct 15 12:56:48 PM UTC 24 |
Oct 15 12:56:58 PM UTC 24 |
45528609 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.3714818456 |
|
|
Oct 15 12:56:44 PM UTC 24 |
Oct 15 12:56:58 PM UTC 24 |
232853122 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.1102544402 |
|
|
Oct 15 12:57:03 PM UTC 24 |
Oct 15 12:57:05 PM UTC 24 |
72790717 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.3212316012 |
|
|
Oct 15 12:57:03 PM UTC 24 |
Oct 15 12:57:05 PM UTC 24 |
32667751 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.3855808789 |
|
|
Oct 15 12:56:59 PM UTC 24 |
Oct 15 12:57:01 PM UTC 24 |
18388933 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.233296665 |
|
|
Oct 15 12:56:59 PM UTC 24 |
Oct 15 12:57:02 PM UTC 24 |
30329984 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.349159132 |
|
|
Oct 15 12:56:59 PM UTC 24 |
Oct 15 12:57:02 PM UTC 24 |
85897770 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.3152402690 |
|
|
Oct 15 12:56:58 PM UTC 24 |
Oct 15 12:57:02 PM UTC 24 |
60749644 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.2676899044 |
|
|
Oct 15 12:56:58 PM UTC 24 |
Oct 15 12:57:02 PM UTC 24 |
40229119 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.929181878 |
|
|
Oct 15 12:56:48 PM UTC 24 |
Oct 15 12:57:02 PM UTC 24 |
44374335 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2414442796 |
|
|
Oct 15 12:56:48 PM UTC 24 |
Oct 15 12:57:03 PM UTC 24 |
452053500 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.190791079 |
|
|
Oct 15 12:56:58 PM UTC 24 |
Oct 15 12:57:03 PM UTC 24 |
203274638 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.3461213136 |
|
|
Oct 15 12:56:58 PM UTC 24 |
Oct 15 12:57:03 PM UTC 24 |
117934502 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2688611450 |
|
|
Oct 15 12:56:48 PM UTC 24 |
Oct 15 12:57:03 PM UTC 24 |
221280857 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.1847341454 |
|
|
Oct 15 12:56:58 PM UTC 24 |
Oct 15 12:57:04 PM UTC 24 |
318894465 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2391989230 |
|
|
Oct 15 12:57:02 PM UTC 24 |
Oct 15 12:57:04 PM UTC 24 |
413226542 ps |