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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.96 98.21 96.58 99.62 96.00 96.32 100.00 99.02


Total test records in report: 1110
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1008 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.1733262000 Oct 15 12:57:02 PM UTC 24 Oct 15 12:57:04 PM UTC 24 50977132 ps
T1009 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2855412657 Oct 15 12:56:44 PM UTC 24 Oct 15 12:57:04 PM UTC 24 76383672 ps
T1010 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.1150824915 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:17 PM UTC 24 52980811 ps
T1011 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.797773177 Oct 15 12:56:44 PM UTC 24 Oct 15 12:57:05 PM UTC 24 49629327 ps
T1012 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.975383146 Oct 15 12:56:44 PM UTC 24 Oct 15 12:57:05 PM UTC 24 54374769 ps
T1013 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.962735212 Oct 15 12:56:44 PM UTC 24 Oct 15 12:57:05 PM UTC 24 83866009 ps
T1014 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2114889779 Oct 15 12:57:04 PM UTC 24 Oct 15 12:57:06 PM UTC 24 229745546 ps
T1015 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.4088446236 Oct 15 12:56:46 PM UTC 24 Oct 15 12:57:05 PM UTC 24 60298299 ps
T1016 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.422882979 Oct 15 12:56:45 PM UTC 24 Oct 15 12:57:05 PM UTC 24 106346124 ps
T1017 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.4210960007 Oct 15 12:56:44 PM UTC 24 Oct 15 12:57:05 PM UTC 24 196175609 ps
T1018 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1019837417 Oct 15 12:56:44 PM UTC 24 Oct 15 12:57:05 PM UTC 24 61662227 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.3543961404 Oct 15 12:57:05 PM UTC 24 Oct 15 12:57:07 PM UTC 24 30098660 ps
T1019 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.21656949 Oct 15 12:56:46 PM UTC 24 Oct 15 12:57:05 PM UTC 24 24881989 ps
T1020 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.4034033914 Oct 15 12:56:46 PM UTC 24 Oct 15 12:57:05 PM UTC 24 26047609 ps
T1021 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2469987249 Oct 15 12:56:46 PM UTC 24 Oct 15 12:57:06 PM UTC 24 43934459 ps
T1022 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2127870755 Oct 15 12:56:46 PM UTC 24 Oct 15 12:57:06 PM UTC 24 122408555 ps
T1023 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1731762621 Oct 15 12:56:46 PM UTC 24 Oct 15 12:57:06 PM UTC 24 69121335 ps
T1024 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.677127236 Oct 15 12:57:04 PM UTC 24 Oct 15 12:57:06 PM UTC 24 19944094 ps
T1025 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.258364653 Oct 15 12:56:45 PM UTC 24 Oct 15 12:57:06 PM UTC 24 40292562 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.4143208341 Oct 15 12:56:46 PM UTC 24 Oct 15 12:57:06 PM UTC 24 24478919 ps
T1026 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.859205001 Oct 15 12:57:03 PM UTC 24 Oct 15 12:57:06 PM UTC 24 48621550 ps
T1027 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.2204559299 Oct 15 12:57:04 PM UTC 24 Oct 15 12:57:06 PM UTC 24 79586207 ps
T1028 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3146143039 Oct 15 12:57:04 PM UTC 24 Oct 15 12:57:06 PM UTC 24 61478808 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2517385532 Oct 15 12:56:46 PM UTC 24 Oct 15 12:57:06 PM UTC 24 189419158 ps
T1029 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.948043286 Oct 15 12:57:05 PM UTC 24 Oct 15 12:57:07 PM UTC 24 110236190 ps
T1030 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1062009158 Oct 15 12:57:05 PM UTC 24 Oct 15 12:57:07 PM UTC 24 83103409 ps
T1031 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1820919975 Oct 15 12:56:46 PM UTC 24 Oct 15 12:57:07 PM UTC 24 72717520 ps
T1032 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.224929398 Oct 15 12:57:05 PM UTC 24 Oct 15 12:57:08 PM UTC 24 288861564 ps
T1033 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.3199172110 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:11 PM UTC 24 44415043 ps
T1034 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.2032591015 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:11 PM UTC 24 54718130 ps
T1035 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.86804481 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:11 PM UTC 24 40559301 ps
T1036 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1526562992 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:11 PM UTC 24 91219802 ps
T1037 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3595569500 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:12 PM UTC 24 268134102 ps
T1038 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3966152072 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:12 PM UTC 24 397830848 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.3348019053 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:17 PM UTC 24 24557140 ps
T1039 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.541245866 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:18 PM UTC 24 147593521 ps
T1040 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.4198680228 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:18 PM UTC 24 22449107 ps
T1041 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.1025488465 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:18 PM UTC 24 25566429 ps
T1042 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1957292468 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:18 PM UTC 24 455743685 ps
T1043 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1995357650 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:18 PM UTC 24 951274641 ps
T1044 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3892574322 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:18 PM UTC 24 403214469 ps
T1045 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.756559063 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:19 PM UTC 24 54098643 ps
T1046 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.982623633 Oct 15 12:57:37 PM UTC 24 Oct 15 12:57:39 PM UTC 24 20973773 ps
T1047 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.1656659620 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:21 PM UTC 24 20060966 ps
T1048 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1091960129 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:21 PM UTC 24 129013350 ps
T1049 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.3781470700 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:21 PM UTC 24 45155438 ps
T1050 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3757869899 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:21 PM UTC 24 20786090 ps
T1051 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.2920506742 Oct 15 12:57:13 PM UTC 24 Oct 15 12:57:21 PM UTC 24 21060516 ps
T1052 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.494883938 Oct 15 12:57:13 PM UTC 24 Oct 15 12:57:21 PM UTC 24 18491966 ps
T1053 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4235108692 Oct 15 12:57:13 PM UTC 24 Oct 15 12:57:21 PM UTC 24 102089816 ps
T1054 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1136630786 Oct 15 12:57:13 PM UTC 24 Oct 15 12:57:22 PM UTC 24 37213721 ps
T1055 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.4057426155 Oct 15 12:57:10 PM UTC 24 Oct 15 12:57:22 PM UTC 24 22364451 ps
T1056 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.1473594976 Oct 15 12:57:13 PM UTC 24 Oct 15 12:57:22 PM UTC 24 90081131 ps
T1057 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.87939915 Oct 15 12:57:13 PM UTC 24 Oct 15 12:57:22 PM UTC 24 342469762 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1021415728 Oct 15 12:57:10 PM UTC 24 Oct 15 12:57:22 PM UTC 24 102972365 ps
T1058 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.4100724116 Oct 15 12:57:10 PM UTC 24 Oct 15 12:57:23 PM UTC 24 86684380 ps
T1059 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.54096212 Oct 15 12:57:24 PM UTC 24 Oct 15 12:57:27 PM UTC 24 21828924 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.2276559760 Oct 15 12:57:24 PM UTC 24 Oct 15 12:57:27 PM UTC 24 24969246 ps
T1060 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.4187807656 Oct 15 12:57:24 PM UTC 24 Oct 15 12:57:27 PM UTC 24 17893392 ps
T1061 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.4241633472 Oct 15 12:57:24 PM UTC 24 Oct 15 12:57:27 PM UTC 24 53876680 ps
T1062 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3015202822 Oct 15 12:57:24 PM UTC 24 Oct 15 12:57:27 PM UTC 24 53279143 ps
T1063 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.78101730 Oct 15 12:57:24 PM UTC 24 Oct 15 12:57:27 PM UTC 24 54135309 ps
T1064 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3650997514 Oct 15 12:57:24 PM UTC 24 Oct 15 12:57:27 PM UTC 24 56344490 ps
T1065 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.957018393 Oct 15 12:57:19 PM UTC 24 Oct 15 12:57:32 PM UTC 24 64442744 ps
T1066 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.40701939 Oct 15 12:57:17 PM UTC 24 Oct 15 12:57:32 PM UTC 24 26809279 ps
T1067 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.3991287617 Oct 15 12:57:20 PM UTC 24 Oct 15 12:57:32 PM UTC 24 46385397 ps
T1068 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2968003154 Oct 15 12:57:20 PM UTC 24 Oct 15 12:57:33 PM UTC 24 79519510 ps
T1069 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.4072861656 Oct 15 12:57:19 PM UTC 24 Oct 15 12:57:33 PM UTC 24 207422119 ps
T1070 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3308336909 Oct 15 12:57:19 PM UTC 24 Oct 15 12:57:33 PM UTC 24 68273430 ps
T1071 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.556247792 Oct 15 12:57:20 PM UTC 24 Oct 15 12:57:33 PM UTC 24 164155839 ps
T1072 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.820541746 Oct 15 12:57:19 PM UTC 24 Oct 15 12:57:33 PM UTC 24 117619383 ps
T1073 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.4121206574 Oct 15 12:57:21 PM UTC 24 Oct 15 12:57:33 PM UTC 24 220422635 ps
T1074 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.2477690394 Oct 15 12:57:28 PM UTC 24 Oct 15 12:57:33 PM UTC 24 62357163 ps
T1075 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.837698457 Oct 15 12:57:38 PM UTC 24 Oct 15 12:57:39 PM UTC 24 26395562 ps
T1076 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.2303974640 Oct 15 12:57:28 PM UTC 24 Oct 15 12:57:34 PM UTC 24 16740401 ps
T1077 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.1637486436 Oct 15 12:57:29 PM UTC 24 Oct 15 12:57:34 PM UTC 24 18459197 ps
T1078 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.3604685101 Oct 15 12:57:28 PM UTC 24 Oct 15 12:57:34 PM UTC 24 23675416 ps
T1079 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.517501288 Oct 15 12:57:28 PM UTC 24 Oct 15 12:57:34 PM UTC 24 22634320 ps
T1080 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.3645714054 Oct 15 12:57:28 PM UTC 24 Oct 15 12:57:34 PM UTC 24 20389606 ps
T1081 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.3251745026 Oct 15 12:57:29 PM UTC 24 Oct 15 12:57:34 PM UTC 24 84766566 ps
T1082 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.426831728 Oct 15 12:57:24 PM UTC 24 Oct 15 12:57:34 PM UTC 24 46956836 ps
T1083 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.4165749057 Oct 15 12:57:21 PM UTC 24 Oct 15 12:57:34 PM UTC 24 182418379 ps
T1084 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.1898874668 Oct 15 12:57:24 PM UTC 24 Oct 15 12:57:34 PM UTC 24 50318194 ps
T1085 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.186667587 Oct 15 12:57:24 PM UTC 24 Oct 15 12:57:34 PM UTC 24 71978966 ps
T1086 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.3494888559 Oct 15 12:57:24 PM UTC 24 Oct 15 12:57:34 PM UTC 24 17844856 ps
T1087 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.4068932574 Oct 15 12:57:25 PM UTC 24 Oct 15 12:57:34 PM UTC 24 24050682 ps
T1088 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.221200598 Oct 15 12:57:24 PM UTC 24 Oct 15 12:57:34 PM UTC 24 83525481 ps
T1089 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.3958184119 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:37 PM UTC 24 221865944 ps
T1090 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.667438030 Oct 15 12:57:14 PM UTC 24 Oct 15 12:57:35 PM UTC 24 35439309 ps
T1091 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.4256939311 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:35 PM UTC 24 25023424 ps
T1092 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.2551663625 Oct 15 12:57:37 PM UTC 24 Oct 15 12:57:39 PM UTC 24 18963045 ps
T1093 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.960804931 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:35 PM UTC 24 38553183 ps
T1094 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.4039992066 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:35 PM UTC 24 62180454 ps
T1095 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.2794553878 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:35 PM UTC 24 27094710 ps
T1096 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.614764731 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:35 PM UTC 24 50618715 ps
T1097 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.745395291 Oct 15 12:57:33 PM UTC 24 Oct 15 12:57:35 PM UTC 24 37367945 ps
T1098 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.922325777 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:35 PM UTC 24 41391492 ps
T1099 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.2071635335 Oct 15 12:57:33 PM UTC 24 Oct 15 12:57:35 PM UTC 24 17252970 ps
T1100 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.239921045 Oct 15 12:57:33 PM UTC 24 Oct 15 12:57:35 PM UTC 24 20293796 ps
T1101 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1338463297 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:36 PM UTC 24 106896754 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1834294055 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:36 PM UTC 24 430676678 ps
T1102 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.3041197326 Oct 15 12:57:08 PM UTC 24 Oct 15 12:57:37 PM UTC 24 244735777 ps
T1103 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.1566479059 Oct 15 12:57:38 PM UTC 24 Oct 15 12:57:39 PM UTC 24 91738089 ps
T1104 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.498408311 Oct 15 12:57:38 PM UTC 24 Oct 15 12:57:40 PM UTC 24 24081766 ps
T1105 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.2163700801 Oct 15 12:57:38 PM UTC 24 Oct 15 12:57:40 PM UTC 24 16630590 ps
T1106 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.3277815657 Oct 15 12:57:38 PM UTC 24 Oct 15 12:57:40 PM UTC 24 48753637 ps
T1107 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.905211027 Oct 15 12:57:38 PM UTC 24 Oct 15 12:57:40 PM UTC 24 51286531 ps
T1108 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.2324786680 Oct 15 12:57:38 PM UTC 24 Oct 15 12:57:40 PM UTC 24 43958133 ps
T1109 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.140138476 Oct 15 12:57:38 PM UTC 24 Oct 15 12:57:40 PM UTC 24 32596472 ps
T1110 /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.4179291405 Oct 15 12:57:38 PM UTC 24 Oct 15 12:57:40 PM UTC 24 46478433 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3150758144
Short name T8
Test name
Test status
Simulation time 986871276 ps
CPU time 3.21 seconds
Started Oct 15 12:52:39 PM UTC 24
Finished Oct 15 12:52:43 PM UTC 24
Peak memory 212740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150758144 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.3150758144
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.27667901
Short name T28
Test name
Test status
Simulation time 148000974 ps
CPU time 1.27 seconds
Started Oct 15 12:52:44 PM UTC 24
Finished Oct 15 12:52:47 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27667901 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.27667901
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.348329285
Short name T23
Test name
Test status
Simulation time 2291597429 ps
CPU time 5.23 seconds
Started Oct 15 12:52:46 PM UTC 24
Finished Oct 15 12:52:52 PM UTC 24
Peak memory 212988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=348329285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_
stress_all_with_rand_reset.348329285
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.3330700738
Short name T21
Test name
Test status
Simulation time 373629230 ps
CPU time 2.06 seconds
Started Oct 15 12:52:55 PM UTC 24
Finished Oct 15 12:52:58 PM UTC 24
Peak memory 240228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330700738 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.3330700738
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3174105069
Short name T57
Test name
Test status
Simulation time 239418184 ps
CPU time 1.16 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:43 PM UTC 24
Peak memory 210680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174105069 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err.3174105069
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.215865059
Short name T40
Test name
Test status
Simulation time 82649483 ps
CPU time 1.07 seconds
Started Oct 15 12:52:46 PM UTC 24
Finished Oct 15 12:52:48 PM UTC 24
Peak memory 210836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215865059 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid.215865059
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all_with_rand_reset.394783086
Short name T49
Test name
Test status
Simulation time 3117742411 ps
CPU time 12.56 seconds
Started Oct 15 12:54:22 PM UTC 24
Finished Oct 15 12:54:36 PM UTC 24
Peak memory 212620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=394783086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr
_stress_all_with_rand_reset.394783086
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.1253993971
Short name T171
Test name
Test status
Simulation time 21107897 ps
CPU time 0.63 seconds
Started Oct 15 12:56:44 PM UTC 24
Finished Oct 15 12:56:57 PM UTC 24
Peak memory 206348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253993971 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.1253993971
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2194057208
Short name T63
Test name
Test status
Simulation time 32215626 ps
CPU time 1.3 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:44 PM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194057208 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2194057208
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2251282945
Short name T9
Test name
Test status
Simulation time 30149131 ps
CPU time 0.96 seconds
Started Oct 15 12:52:41 PM UTC 24
Finished Oct 15 12:52:43 PM UTC 24
Peak memory 209180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251282945 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_malfunc.2251282945
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.3027453797
Short name T120
Test name
Test status
Simulation time 50608803 ps
CPU time 0.83 seconds
Started Oct 15 12:56:43 PM UTC 24
Finished Oct 15 12:56:45 PM UTC 24
Peak memory 208396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027453797 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.3027453797
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.4017376146
Short name T136
Test name
Test status
Simulation time 617860229 ps
CPU time 3.19 seconds
Started Oct 15 12:52:55 PM UTC 24
Finished Oct 15 12:52:59 PM UTC 24
Peak memory 212516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017376146 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.4017376146
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.1492682451
Short name T10
Test name
Test status
Simulation time 150623417 ps
CPU time 1.47 seconds
Started Oct 15 12:52:41 PM UTC 24
Finished Oct 15 12:52:44 PM UTC 24
Peak memory 210416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492682451 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_ctrl_config_regwen.1492682451
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.1676998947
Short name T27
Test name
Test status
Simulation time 69354278 ps
CPU time 1.08 seconds
Started Oct 15 12:52:54 PM UTC 24
Finished Oct 15 12:52:56 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676998947 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disable_rom_integrity_check.1676998947
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.3097042760
Short name T178
Test name
Test status
Simulation time 58450228 ps
CPU time 0.87 seconds
Started Oct 15 12:54:14 PM UTC 24
Finished Oct 15 12:54:16 PM UTC 24
Peak memory 209384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097042760 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_disable_rom_integrity_check.3097042760
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2688611450
Short name T68
Test name
Test status
Simulation time 221280857 ps
CPU time 1.54 seconds
Started Oct 15 12:56:48 PM UTC 24
Finished Oct 15 12:57:03 PM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688611450 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err.2688611450
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.1356707591
Short name T118
Test name
Test status
Simulation time 2594795806 ps
CPU time 5.97 seconds
Started Oct 15 12:54:07 PM UTC 24
Finished Oct 15 12:54:15 PM UTC 24
Peak memory 212664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356707591 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.1356707591
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_disable_rom_integrity_check.669611678
Short name T177
Test name
Test status
Simulation time 79408323 ps
CPU time 1.08 seconds
Started Oct 15 12:53:58 PM UTC 24
Finished Oct 15 12:54:00 PM UTC 24
Peak memory 209060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669611678 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disable_rom_integrity_check.669611678
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_disable_rom_integrity_check.2414847911
Short name T176
Test name
Test status
Simulation time 64315858 ps
CPU time 0.75 seconds
Started Oct 15 12:55:48 PM UTC 24
Finished Oct 15 12:56:03 PM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414847911 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_disable_rom_integrity_check.2414847911
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.1918156904
Short name T17
Test name
Test status
Simulation time 40145717 ps
CPU time 1.03 seconds
Started Oct 15 12:52:44 PM UTC 24
Finished Oct 15 12:52:46 PM UTC 24
Peak memory 208932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918156904 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.1918156904
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2274829983
Short name T61
Test name
Test status
Simulation time 42795298 ps
CPU time 1.16 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:43 PM UTC 24
Peak memory 210748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274829983 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.2274829983
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3060720697
Short name T173
Test name
Test status
Simulation time 119753021 ps
CPU time 1.93 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:44 PM UTC 24
Peak memory 208392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060720697 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.3060720697
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.114275661
Short name T52
Test name
Test status
Simulation time 66085138 ps
CPU time 0.69 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:43 PM UTC 24
Peak memory 210016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114275661 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.114275661
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.3605029171
Short name T51
Test name
Test status
Simulation time 49414947 ps
CPU time 1.05 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:43 PM UTC 24
Peak memory 210756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3605029171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_w
ith_rand_reset.3605029171
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.2089419349
Short name T62
Test name
Test status
Simulation time 34764737 ps
CPU time 0.78 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:43 PM UTC 24
Peak memory 208396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089419349 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.2089419349
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.2793102892
Short name T53
Test name
Test status
Simulation time 26036113 ps
CPU time 0.75 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:43 PM UTC 24
Peak memory 206348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793102892 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.2793102892
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.3713611579
Short name T56
Test name
Test status
Simulation time 19406672 ps
CPU time 0.69 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:43 PM UTC 24
Peak memory 208404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713611579 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_same_csr_outstanding.3713611579
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.2062816585
Short name T74
Test name
Test status
Simulation time 32419980 ps
CPU time 1.63 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:44 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062816585 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.2062816585
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3869130590
Short name T47
Test name
Test status
Simulation time 282026325 ps
CPU time 1.29 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:43 PM UTC 24
Peak memory 210748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869130590 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.3869130590
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3940825935
Short name T174
Test name
Test status
Simulation time 89622765 ps
CPU time 1.3 seconds
Started Oct 15 12:56:43 PM UTC 24
Finished Oct 15 12:56:45 PM UTC 24
Peak memory 208392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940825935 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.3940825935
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2077321573
Short name T129
Test name
Test status
Simulation time 380727308 ps
CPU time 1.79 seconds
Started Oct 15 12:56:43 PM UTC 24
Finished Oct 15 12:56:45 PM UTC 24
Peak memory 210816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077321573 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.2077321573
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2574342048
Short name T992
Test name
Test status
Simulation time 66104874 ps
CPU time 0.73 seconds
Started Oct 15 12:56:42 PM UTC 24
Finished Oct 15 12:56:44 PM UTC 24
Peak memory 208392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574342048 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.2574342048
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.960725232
Short name T175
Test name
Test status
Simulation time 59162527 ps
CPU time 1.11 seconds
Started Oct 15 12:56:43 PM UTC 24
Finished Oct 15 12:56:45 PM UTC 24
Peak memory 210816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=960725232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_wi
th_rand_reset.960725232
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.3802345838
Short name T131
Test name
Test status
Simulation time 40285066 ps
CPU time 0.67 seconds
Started Oct 15 12:56:43 PM UTC 24
Finished Oct 15 12:56:44 PM UTC 24
Peak memory 208396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802345838 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.3802345838
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.1697597724
Short name T54
Test name
Test status
Simulation time 56637410 ps
CPU time 0.8 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:43 PM UTC 24
Peak memory 206348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697597724 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.1697597724
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1629243246
Short name T132
Test name
Test status
Simulation time 69608796 ps
CPU time 0.93 seconds
Started Oct 15 12:56:43 PM UTC 24
Finished Oct 15 12:56:45 PM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629243246 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_same_csr_outstanding.1629243246
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1062009158
Short name T1030
Test name
Test status
Simulation time 83103409 ps
CPU time 1 seconds
Started Oct 15 12:57:05 PM UTC 24
Finished Oct 15 12:57:07 PM UTC 24
Peak memory 210756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1062009158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_
with_rand_reset.1062009158
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.3543961404
Short name T125
Test name
Test status
Simulation time 30098660 ps
CPU time 0.65 seconds
Started Oct 15 12:57:05 PM UTC 24
Finished Oct 15 12:57:07 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543961404 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.3543961404
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.677127236
Short name T1024
Test name
Test status
Simulation time 19944094 ps
CPU time 0.72 seconds
Started Oct 15 12:57:04 PM UTC 24
Finished Oct 15 12:57:06 PM UTC 24
Peak memory 206344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677127236 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.677127236
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.948043286
Short name T1029
Test name
Test status
Simulation time 110236190 ps
CPU time 0.73 seconds
Started Oct 15 12:57:05 PM UTC 24
Finished Oct 15 12:57:07 PM UTC 24
Peak memory 208396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948043286 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_same_csr_outstanding.948043286
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.2204559299
Short name T1027
Test name
Test status
Simulation time 79586207 ps
CPU time 1.18 seconds
Started Oct 15 12:57:04 PM UTC 24
Finished Oct 15 12:57:06 PM UTC 24
Peak memory 210744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204559299 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.2204559299
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2114889779
Short name T1014
Test name
Test status
Simulation time 229745546 ps
CPU time 1.52 seconds
Started Oct 15 12:57:04 PM UTC 24
Finished Oct 15 12:57:06 PM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114889779 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err.2114889779
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.86804481
Short name T1035
Test name
Test status
Simulation time 40559301 ps
CPU time 0.76 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:11 PM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=86804481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_wi
th_rand_reset.86804481
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.1150824915
Short name T1010
Test name
Test status
Simulation time 52980811 ps
CPU time 0.61 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:17 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150824915 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.1150824915
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.3199172110
Short name T1033
Test name
Test status
Simulation time 44415043 ps
CPU time 0.64 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:11 PM UTC 24
Peak memory 206344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199172110 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.3199172110
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1526562992
Short name T1036
Test name
Test status
Simulation time 91219802 ps
CPU time 0.89 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:11 PM UTC 24
Peak memory 210756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526562992 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_same_csr_outstanding.1526562992
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.224929398
Short name T1032
Test name
Test status
Simulation time 288861564 ps
CPU time 1.42 seconds
Started Oct 15 12:57:05 PM UTC 24
Finished Oct 15 12:57:08 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224929398 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.224929398
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1995357650
Short name T1043
Test name
Test status
Simulation time 951274641 ps
CPU time 1.42 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:18 PM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995357650 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_err.1995357650
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1957292468
Short name T1042
Test name
Test status
Simulation time 455743685 ps
CPU time 0.9 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:18 PM UTC 24
Peak memory 210756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1957292468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_
with_rand_reset.1957292468
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.3348019053
Short name T127
Test name
Test status
Simulation time 24557140 ps
CPU time 0.56 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:17 PM UTC 24
Peak memory 206352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348019053 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.3348019053
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.2032591015
Short name T1034
Test name
Test status
Simulation time 54718130 ps
CPU time 0.61 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:11 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032591015 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.2032591015
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.541245866
Short name T1039
Test name
Test status
Simulation time 147593521 ps
CPU time 0.8 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:18 PM UTC 24
Peak memory 210692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541245866 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_same_csr_outstanding.541245866
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3595569500
Short name T1037
Test name
Test status
Simulation time 268134102 ps
CPU time 1.51 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:12 PM UTC 24
Peak memory 210748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595569500 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.3595569500
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3966152072
Short name T1038
Test name
Test status
Simulation time 397830848 ps
CPU time 1.45 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:12 PM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966152072 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err.3966152072
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.960804931
Short name T1093
Test name
Test status
Simulation time 38553183 ps
CPU time 0.91 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:35 PM UTC 24
Peak memory 210820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=960804931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_w
ith_rand_reset.960804931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.1025488465
Short name T1041
Test name
Test status
Simulation time 25566429 ps
CPU time 0.63 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:18 PM UTC 24
Peak memory 206328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025488465 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.1025488465
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.4198680228
Short name T1040
Test name
Test status
Simulation time 22449107 ps
CPU time 0.6 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:18 PM UTC 24
Peak memory 206300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198680228 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.4198680228
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.4256939311
Short name T1091
Test name
Test status
Simulation time 25023424 ps
CPU time 0.72 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:35 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256939311 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_same_csr_outstanding.4256939311
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.756559063
Short name T1045
Test name
Test status
Simulation time 54098643 ps
CPU time 1.98 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:19 PM UTC 24
Peak memory 210740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756559063 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.756559063
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3892574322
Short name T1044
Test name
Test status
Simulation time 403214469 ps
CPU time 1.4 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:18 PM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892574322 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_err.3892574322
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.922325777
Short name T1098
Test name
Test status
Simulation time 41391492 ps
CPU time 0.74 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:35 PM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=922325777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_w
ith_rand_reset.922325777
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.614764731
Short name T1096
Test name
Test status
Simulation time 50618715 ps
CPU time 0.67 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:35 PM UTC 24
Peak memory 208292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614764731 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.614764731
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.2794553878
Short name T1095
Test name
Test status
Simulation time 27094710 ps
CPU time 0.67 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:35 PM UTC 24
Peak memory 206260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794553878 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.2794553878
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3757869899
Short name T1050
Test name
Test status
Simulation time 20786090 ps
CPU time 0.76 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:21 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757869899 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_same_csr_outstanding.3757869899
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.3041197326
Short name T1102
Test name
Test status
Simulation time 244735777 ps
CPU time 2.1 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:37 PM UTC 24
Peak memory 211256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041197326 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.3041197326
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1834294055
Short name T167
Test name
Test status
Simulation time 430676678 ps
CPU time 1.41 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:36 PM UTC 24
Peak memory 210872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834294055 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err.1834294055
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.4039992066
Short name T1094
Test name
Test status
Simulation time 62180454 ps
CPU time 0.62 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:35 PM UTC 24
Peak memory 210756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4039992066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_
with_rand_reset.4039992066
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.1656659620
Short name T1047
Test name
Test status
Simulation time 20060966 ps
CPU time 0.59 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:21 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656659620 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.1656659620
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.3781470700
Short name T1049
Test name
Test status
Simulation time 45155438 ps
CPU time 0.65 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:21 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781470700 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.3781470700
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1091960129
Short name T1048
Test name
Test status
Simulation time 129013350 ps
CPU time 0.62 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:21 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091960129 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_same_csr_outstanding.1091960129
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.3958184119
Short name T1089
Test name
Test status
Simulation time 221865944 ps
CPU time 2.44 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:37 PM UTC 24
Peak memory 211088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958184119 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.3958184119
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1338463297
Short name T1101
Test name
Test status
Simulation time 106896754 ps
CPU time 1.11 seconds
Started Oct 15 12:57:08 PM UTC 24
Finished Oct 15 12:57:36 PM UTC 24
Peak memory 210812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338463297 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_err.1338463297
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4235108692
Short name T1053
Test name
Test status
Simulation time 102089816 ps
CPU time 0.79 seconds
Started Oct 15 12:57:13 PM UTC 24
Finished Oct 15 12:57:21 PM UTC 24
Peak memory 210816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4235108692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_
with_rand_reset.4235108692
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.2920506742
Short name T1051
Test name
Test status
Simulation time 21060516 ps
CPU time 0.63 seconds
Started Oct 15 12:57:13 PM UTC 24
Finished Oct 15 12:57:21 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920506742 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.2920506742
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.4057426155
Short name T1055
Test name
Test status
Simulation time 22364451 ps
CPU time 0.59 seconds
Started Oct 15 12:57:10 PM UTC 24
Finished Oct 15 12:57:22 PM UTC 24
Peak memory 206344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057426155 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.4057426155
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1136630786
Short name T1054
Test name
Test status
Simulation time 37213721 ps
CPU time 0.74 seconds
Started Oct 15 12:57:13 PM UTC 24
Finished Oct 15 12:57:22 PM UTC 24
Peak memory 210816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136630786 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_same_csr_outstanding.1136630786
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.4100724116
Short name T1058
Test name
Test status
Simulation time 86684380 ps
CPU time 1.9 seconds
Started Oct 15 12:57:10 PM UTC 24
Finished Oct 15 12:57:23 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100724116 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.4100724116
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.1021415728
Short name T166
Test name
Test status
Simulation time 102972365 ps
CPU time 1.08 seconds
Started Oct 15 12:57:10 PM UTC 24
Finished Oct 15 12:57:22 PM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021415728 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err.1021415728
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3308336909
Short name T1070
Test name
Test status
Simulation time 68273430 ps
CPU time 1.21 seconds
Started Oct 15 12:57:19 PM UTC 24
Finished Oct 15 12:57:33 PM UTC 24
Peak memory 210748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3308336909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_
with_rand_reset.3308336909
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.667438030
Short name T1090
Test name
Test status
Simulation time 35439309 ps
CPU time 0.59 seconds
Started Oct 15 12:57:14 PM UTC 24
Finished Oct 15 12:57:35 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667438030 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.667438030
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.494883938
Short name T1052
Test name
Test status
Simulation time 18491966 ps
CPU time 0.6 seconds
Started Oct 15 12:57:13 PM UTC 24
Finished Oct 15 12:57:21 PM UTC 24
Peak memory 206344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494883938 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.494883938
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.40701939
Short name T1066
Test name
Test status
Simulation time 26809279 ps
CPU time 0.62 seconds
Started Oct 15 12:57:17 PM UTC 24
Finished Oct 15 12:57:32 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40701939 -assert nopostproc +UV
M_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_same_csr_outstanding.40701939
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.1473594976
Short name T1056
Test name
Test status
Simulation time 90081131 ps
CPU time 1.08 seconds
Started Oct 15 12:57:13 PM UTC 24
Finished Oct 15 12:57:22 PM UTC 24
Peak memory 210740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473594976 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.1473594976
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.87939915
Short name T1057
Test name
Test status
Simulation time 342469762 ps
CPU time 1.27 seconds
Started Oct 15 12:57:13 PM UTC 24
Finished Oct 15 12:57:22 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87939915 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err.87939915
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.556247792
Short name T1071
Test name
Test status
Simulation time 164155839 ps
CPU time 1.03 seconds
Started Oct 15 12:57:20 PM UTC 24
Finished Oct 15 12:57:33 PM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=556247792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_w
ith_rand_reset.556247792
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.3991287617
Short name T1067
Test name
Test status
Simulation time 46385397 ps
CPU time 0.61 seconds
Started Oct 15 12:57:20 PM UTC 24
Finished Oct 15 12:57:32 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991287617 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.3991287617
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.957018393
Short name T1065
Test name
Test status
Simulation time 64442744 ps
CPU time 0.59 seconds
Started Oct 15 12:57:19 PM UTC 24
Finished Oct 15 12:57:32 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957018393 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.957018393
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2968003154
Short name T1068
Test name
Test status
Simulation time 79519510 ps
CPU time 0.7 seconds
Started Oct 15 12:57:20 PM UTC 24
Finished Oct 15 12:57:33 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968003154 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_same_csr_outstanding.2968003154
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.820541746
Short name T1072
Test name
Test status
Simulation time 117619383 ps
CPU time 1.29 seconds
Started Oct 15 12:57:19 PM UTC 24
Finished Oct 15 12:57:33 PM UTC 24
Peak memory 210632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820541746 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.820541746
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.4072861656
Short name T1069
Test name
Test status
Simulation time 207422119 ps
CPU time 0.94 seconds
Started Oct 15 12:57:19 PM UTC 24
Finished Oct 15 12:57:33 PM UTC 24
Peak memory 210812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072861656 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err.4072861656
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3650997514
Short name T1064
Test name
Test status
Simulation time 56344490 ps
CPU time 0.98 seconds
Started Oct 15 12:57:24 PM UTC 24
Finished Oct 15 12:57:27 PM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3650997514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_
with_rand_reset.3650997514
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.2276559760
Short name T128
Test name
Test status
Simulation time 24969246 ps
CPU time 0.6 seconds
Started Oct 15 12:57:24 PM UTC 24
Finished Oct 15 12:57:27 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276559760 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.2276559760
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.4187807656
Short name T1060
Test name
Test status
Simulation time 17893392 ps
CPU time 0.63 seconds
Started Oct 15 12:57:24 PM UTC 24
Finished Oct 15 12:57:27 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187807656 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.4187807656
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3015202822
Short name T1062
Test name
Test status
Simulation time 53279143 ps
CPU time 0.76 seconds
Started Oct 15 12:57:24 PM UTC 24
Finished Oct 15 12:57:27 PM UTC 24
Peak memory 208380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015202822 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_same_csr_outstanding.3015202822
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.4165749057
Short name T1083
Test name
Test status
Simulation time 182418379 ps
CPU time 1.88 seconds
Started Oct 15 12:57:21 PM UTC 24
Finished Oct 15 12:57:34 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165749057 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.4165749057
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.4121206574
Short name T1073
Test name
Test status
Simulation time 220422635 ps
CPU time 0.93 seconds
Started Oct 15 12:57:21 PM UTC 24
Finished Oct 15 12:57:33 PM UTC 24
Peak memory 210812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121206574 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err.4121206574
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.1327967499
Short name T995
Test name
Test status
Simulation time 102667318 ps
CPU time 0.87 seconds
Started Oct 15 12:56:44 PM UTC 24
Finished Oct 15 12:56:46 PM UTC 24
Peak memory 208392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327967499 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.1327967499
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.1515432964
Short name T130
Test name
Test status
Simulation time 157098048 ps
CPU time 1.77 seconds
Started Oct 15 12:56:43 PM UTC 24
Finished Oct 15 12:56:46 PM UTC 24
Peak memory 208392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515432964 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.1515432964
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2795065393
Short name T993
Test name
Test status
Simulation time 88894218 ps
CPU time 0.72 seconds
Started Oct 15 12:56:43 PM UTC 24
Finished Oct 15 12:56:45 PM UTC 24
Peak memory 208392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795065393 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.2795065393
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.5143723
Short name T994
Test name
Test status
Simulation time 45588958 ps
CPU time 0.78 seconds
Started Oct 15 12:56:44 PM UTC 24
Finished Oct 15 12:56:46 PM UTC 24
Peak memory 210756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=5143723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with
_rand_reset.5143723
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.1480444226
Short name T168
Test name
Test status
Simulation time 28309469 ps
CPU time 0.7 seconds
Started Oct 15 12:56:43 PM UTC 24
Finished Oct 15 12:56:45 PM UTC 24
Peak memory 206348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480444226 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.1480444226
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.338076760
Short name T133
Test name
Test status
Simulation time 25490814 ps
CPU time 0.76 seconds
Started Oct 15 12:56:44 PM UTC 24
Finished Oct 15 12:56:46 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338076760 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_same_csr_outstanding.338076760
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.384359564
Short name T64
Test name
Test status
Simulation time 215722012 ps
CPU time 2.65 seconds
Started Oct 15 12:56:43 PM UTC 24
Finished Oct 15 12:56:46 PM UTC 24
Peak memory 211060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384359564 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.384359564
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.2080984123
Short name T58
Test name
Test status
Simulation time 157125670 ps
CPU time 1.17 seconds
Started Oct 15 12:56:43 PM UTC 24
Finished Oct 15 12:56:45 PM UTC 24
Peak memory 210748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080984123 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.2080984123
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.78101730
Short name T1063
Test name
Test status
Simulation time 54135309 ps
CPU time 0.64 seconds
Started Oct 15 12:57:24 PM UTC 24
Finished Oct 15 12:57:27 PM UTC 24
Peak memory 206344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78101730 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pw
rmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.78101730
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.54096212
Short name T1059
Test name
Test status
Simulation time 21828924 ps
CPU time 0.6 seconds
Started Oct 15 12:57:24 PM UTC 24
Finished Oct 15 12:57:27 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54096212 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pw
rmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.54096212
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.221200598
Short name T1088
Test name
Test status
Simulation time 83525481 ps
CPU time 0.67 seconds
Started Oct 15 12:57:24 PM UTC 24
Finished Oct 15 12:57:34 PM UTC 24
Peak memory 206584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221200598 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.221200598
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.4241633472
Short name T1061
Test name
Test status
Simulation time 53876680 ps
CPU time 0.55 seconds
Started Oct 15 12:57:24 PM UTC 24
Finished Oct 15 12:57:27 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241633472 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.4241633472
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.1898874668
Short name T1084
Test name
Test status
Simulation time 50318194 ps
CPU time 0.56 seconds
Started Oct 15 12:57:24 PM UTC 24
Finished Oct 15 12:57:34 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898874668 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.1898874668
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.426831728
Short name T1082
Test name
Test status
Simulation time 46956836 ps
CPU time 0.52 seconds
Started Oct 15 12:57:24 PM UTC 24
Finished Oct 15 12:57:34 PM UTC 24
Peak memory 206260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426831728 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.426831728
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.186667587
Short name T1085
Test name
Test status
Simulation time 71978966 ps
CPU time 0.58 seconds
Started Oct 15 12:57:24 PM UTC 24
Finished Oct 15 12:57:34 PM UTC 24
Peak memory 206836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186667587 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.186667587
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.3494888559
Short name T1086
Test name
Test status
Simulation time 17844856 ps
CPU time 0.62 seconds
Started Oct 15 12:57:24 PM UTC 24
Finished Oct 15 12:57:34 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494888559 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.3494888559
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.4068932574
Short name T1087
Test name
Test status
Simulation time 24050682 ps
CPU time 0.62 seconds
Started Oct 15 12:57:25 PM UTC 24
Finished Oct 15 12:57:34 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068932574 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.4068932574
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.3604685101
Short name T1078
Test name
Test status
Simulation time 23675416 ps
CPU time 0.61 seconds
Started Oct 15 12:57:28 PM UTC 24
Finished Oct 15 12:57:34 PM UTC 24
Peak memory 208104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604685101 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.3604685101
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.962735212
Short name T1013
Test name
Test status
Simulation time 83866009 ps
CPU time 1.07 seconds
Started Oct 15 12:56:44 PM UTC 24
Finished Oct 15 12:57:05 PM UTC 24
Peak memory 210812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962735212 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.962735212
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1019837417
Short name T1018
Test name
Test status
Simulation time 61662227 ps
CPU time 1.63 seconds
Started Oct 15 12:56:44 PM UTC 24
Finished Oct 15 12:57:05 PM UTC 24
Peak memory 210860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019837417 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.1019837417
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2855412657
Short name T1009
Test name
Test status
Simulation time 76383672 ps
CPU time 0.83 seconds
Started Oct 15 12:56:44 PM UTC 24
Finished Oct 15 12:57:04 PM UTC 24
Peak memory 208236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855412657 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.2855412657
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.422882979
Short name T1016
Test name
Test status
Simulation time 106346124 ps
CPU time 1.36 seconds
Started Oct 15 12:56:45 PM UTC 24
Finished Oct 15 12:57:05 PM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=422882979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_wi
th_rand_reset.422882979
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.975383146
Short name T1012
Test name
Test status
Simulation time 54374769 ps
CPU time 0.92 seconds
Started Oct 15 12:56:44 PM UTC 24
Finished Oct 15 12:57:05 PM UTC 24
Peak memory 208392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975383146 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.975383146
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.797773177
Short name T1011
Test name
Test status
Simulation time 49629327 ps
CPU time 0.75 seconds
Started Oct 15 12:56:44 PM UTC 24
Finished Oct 15 12:57:05 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797773177 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_same_csr_outstanding.797773177
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.3714818456
Short name T998
Test name
Test status
Simulation time 232853122 ps
CPU time 1.54 seconds
Started Oct 15 12:56:44 PM UTC 24
Finished Oct 15 12:56:58 PM UTC 24
Peak memory 210640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714818456 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.3714818456
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.4210960007
Short name T1017
Test name
Test status
Simulation time 196175609 ps
CPU time 1.7 seconds
Started Oct 15 12:56:44 PM UTC 24
Finished Oct 15 12:57:05 PM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210960007 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err.4210960007
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.517501288
Short name T1079
Test name
Test status
Simulation time 22634320 ps
CPU time 0.63 seconds
Started Oct 15 12:57:28 PM UTC 24
Finished Oct 15 12:57:34 PM UTC 24
Peak memory 208268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517501288 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.517501288
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.2477690394
Short name T1074
Test name
Test status
Simulation time 62357163 ps
CPU time 0.54 seconds
Started Oct 15 12:57:28 PM UTC 24
Finished Oct 15 12:57:33 PM UTC 24
Peak memory 206344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477690394 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.2477690394
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.3645714054
Short name T1080
Test name
Test status
Simulation time 20389606 ps
CPU time 0.58 seconds
Started Oct 15 12:57:28 PM UTC 24
Finished Oct 15 12:57:34 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645714054 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.3645714054
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.2303974640
Short name T1076
Test name
Test status
Simulation time 16740401 ps
CPU time 0.55 seconds
Started Oct 15 12:57:28 PM UTC 24
Finished Oct 15 12:57:34 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303974640 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.2303974640
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.1637486436
Short name T1077
Test name
Test status
Simulation time 18459197 ps
CPU time 0.59 seconds
Started Oct 15 12:57:29 PM UTC 24
Finished Oct 15 12:57:34 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637486436 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.1637486436
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.3251745026
Short name T1081
Test name
Test status
Simulation time 84766566 ps
CPU time 0.59 seconds
Started Oct 15 12:57:29 PM UTC 24
Finished Oct 15 12:57:34 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251745026 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.3251745026
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.2071635335
Short name T1099
Test name
Test status
Simulation time 17252970 ps
CPU time 0.57 seconds
Started Oct 15 12:57:33 PM UTC 24
Finished Oct 15 12:57:35 PM UTC 24
Peak memory 206292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071635335 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.2071635335
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.745395291
Short name T1097
Test name
Test status
Simulation time 37367945 ps
CPU time 0.55 seconds
Started Oct 15 12:57:33 PM UTC 24
Finished Oct 15 12:57:35 PM UTC 24
Peak memory 206344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745395291 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.745395291
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.239921045
Short name T1100
Test name
Test status
Simulation time 20293796 ps
CPU time 0.59 seconds
Started Oct 15 12:57:33 PM UTC 24
Finished Oct 15 12:57:35 PM UTC 24
Peak memory 206320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239921045 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.239921045
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.2551663625
Short name T1092
Test name
Test status
Simulation time 18963045 ps
CPU time 0.58 seconds
Started Oct 15 12:57:37 PM UTC 24
Finished Oct 15 12:57:39 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551663625 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.2551663625
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.4143208341
Short name T126
Test name
Test status
Simulation time 24478919 ps
CPU time 1.1 seconds
Started Oct 15 12:56:46 PM UTC 24
Finished Oct 15 12:57:06 PM UTC 24
Peak memory 210808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143208341 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.4143208341
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1820919975
Short name T1031
Test name
Test status
Simulation time 72717520 ps
CPU time 2.7 seconds
Started Oct 15 12:56:46 PM UTC 24
Finished Oct 15 12:57:07 PM UTC 24
Peak memory 210952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820919975 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.1820919975
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.4241299490
Short name T121
Test name
Test status
Simulation time 31599839 ps
CPU time 0.7 seconds
Started Oct 15 12:56:45 PM UTC 24
Finished Oct 15 12:56:46 PM UTC 24
Peak memory 208392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241299490 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.4241299490
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.2127870755
Short name T1022
Test name
Test status
Simulation time 122408555 ps
CPU time 1.09 seconds
Started Oct 15 12:56:46 PM UTC 24
Finished Oct 15 12:57:06 PM UTC 24
Peak memory 210756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2127870755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_w
ith_rand_reset.2127870755
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.4088446236
Short name T1015
Test name
Test status
Simulation time 60298299 ps
CPU time 0.65 seconds
Started Oct 15 12:56:46 PM UTC 24
Finished Oct 15 12:57:05 PM UTC 24
Peak memory 208396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088446236 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.4088446236
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.1283980162
Short name T169
Test name
Test status
Simulation time 23733863 ps
CPU time 0.66 seconds
Started Oct 15 12:56:45 PM UTC 24
Finished Oct 15 12:56:46 PM UTC 24
Peak memory 206348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283980162 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.1283980162
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.21656949
Short name T1019
Test name
Test status
Simulation time 24881989 ps
CPU time 0.91 seconds
Started Oct 15 12:56:46 PM UTC 24
Finished Oct 15 12:57:05 PM UTC 24
Peak memory 208396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21656949 -assert nopostproc +UV
M_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_same_csr_outstanding.21656949
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.258364653
Short name T1025
Test name
Test status
Simulation time 40292562 ps
CPU time 1.86 seconds
Started Oct 15 12:56:45 PM UTC 24
Finished Oct 15 12:57:06 PM UTC 24
Peak memory 210388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258364653 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.258364653
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2413097442
Short name T72
Test name
Test status
Simulation time 210395365 ps
CPU time 1.65 seconds
Started Oct 15 12:56:45 PM UTC 24
Finished Oct 15 12:57:05 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413097442 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.2413097442
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.982623633
Short name T1046
Test name
Test status
Simulation time 20973773 ps
CPU time 0.62 seconds
Started Oct 15 12:57:37 PM UTC 24
Finished Oct 15 12:57:39 PM UTC 24
Peak memory 206344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982623633 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.982623633
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.837698457
Short name T1075
Test name
Test status
Simulation time 26395562 ps
CPU time 0.64 seconds
Started Oct 15 12:57:38 PM UTC 24
Finished Oct 15 12:57:39 PM UTC 24
Peak memory 206344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837698457 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.837698457
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.498408311
Short name T1104
Test name
Test status
Simulation time 24081766 ps
CPU time 0.6 seconds
Started Oct 15 12:57:38 PM UTC 24
Finished Oct 15 12:57:40 PM UTC 24
Peak memory 208228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498408311 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.498408311
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.1566479059
Short name T1103
Test name
Test status
Simulation time 91738089 ps
CPU time 0.6 seconds
Started Oct 15 12:57:38 PM UTC 24
Finished Oct 15 12:57:39 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566479059 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.1566479059
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.3277815657
Short name T1106
Test name
Test status
Simulation time 48753637 ps
CPU time 0.65 seconds
Started Oct 15 12:57:38 PM UTC 24
Finished Oct 15 12:57:40 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277815657 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.3277815657
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.2163700801
Short name T1105
Test name
Test status
Simulation time 16630590 ps
CPU time 0.55 seconds
Started Oct 15 12:57:38 PM UTC 24
Finished Oct 15 12:57:40 PM UTC 24
Peak memory 207920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163700801 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.2163700801
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.905211027
Short name T1107
Test name
Test status
Simulation time 51286531 ps
CPU time 0.64 seconds
Started Oct 15 12:57:38 PM UTC 24
Finished Oct 15 12:57:40 PM UTC 24
Peak memory 206344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905211027 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.905211027
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.4179291405
Short name T1110
Test name
Test status
Simulation time 46478433 ps
CPU time 0.75 seconds
Started Oct 15 12:57:38 PM UTC 24
Finished Oct 15 12:57:40 PM UTC 24
Peak memory 206344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179291405 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.4179291405
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.2324786680
Short name T1108
Test name
Test status
Simulation time 43958133 ps
CPU time 0.61 seconds
Started Oct 15 12:57:38 PM UTC 24
Finished Oct 15 12:57:40 PM UTC 24
Peak memory 206340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324786680 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.2324786680
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.140138476
Short name T1109
Test name
Test status
Simulation time 32596472 ps
CPU time 0.73 seconds
Started Oct 15 12:57:38 PM UTC 24
Finished Oct 15 12:57:40 PM UTC 24
Peak memory 206344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140138476 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.140138476
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1731762621
Short name T1023
Test name
Test status
Simulation time 69121335 ps
CPU time 0.76 seconds
Started Oct 15 12:56:46 PM UTC 24
Finished Oct 15 12:57:06 PM UTC 24
Peak memory 209780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1731762621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_w
ith_rand_reset.1731762621
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.1121341324
Short name T122
Test name
Test status
Simulation time 36913939 ps
CPU time 0.76 seconds
Started Oct 15 12:56:46 PM UTC 24
Finished Oct 15 12:57:06 PM UTC 24
Peak memory 206304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121341324 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.1121341324
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.4034033914
Short name T1020
Test name
Test status
Simulation time 26047609 ps
CPU time 0.69 seconds
Started Oct 15 12:56:46 PM UTC 24
Finished Oct 15 12:57:05 PM UTC 24
Peak memory 206272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034033914 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.4034033914
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2469987249
Short name T1021
Test name
Test status
Simulation time 43934459 ps
CPU time 0.78 seconds
Started Oct 15 12:56:46 PM UTC 24
Finished Oct 15 12:57:06 PM UTC 24
Peak memory 208332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469987249 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_same_csr_outstanding.2469987249
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.1017808238
Short name T46
Test name
Test status
Simulation time 35148011 ps
CPU time 1.53 seconds
Started Oct 15 12:56:46 PM UTC 24
Finished Oct 15 12:57:06 PM UTC 24
Peak memory 210812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017808238 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.1017808238
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2517385532
Short name T73
Test name
Test status
Simulation time 189419158 ps
CPU time 1.61 seconds
Started Oct 15 12:56:46 PM UTC 24
Finished Oct 15 12:57:06 PM UTC 24
Peak memory 210748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517385532 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err.2517385532
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.415336058
Short name T996
Test name
Test status
Simulation time 66735076 ps
CPU time 0.84 seconds
Started Oct 15 12:56:48 PM UTC 24
Finished Oct 15 12:56:57 PM UTC 24
Peak memory 210816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=415336058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_wi
th_rand_reset.415336058
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.1727265933
Short name T134
Test name
Test status
Simulation time 54087618 ps
CPU time 0.56 seconds
Started Oct 15 12:56:48 PM UTC 24
Finished Oct 15 12:56:56 PM UTC 24
Peak memory 208132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727265933 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.1727265933
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.929181878
Short name T1003
Test name
Test status
Simulation time 44374335 ps
CPU time 0.58 seconds
Started Oct 15 12:56:48 PM UTC 24
Finished Oct 15 12:57:02 PM UTC 24
Peak memory 206064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929181878 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.929181878
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2414442796
Short name T1004
Test name
Test status
Simulation time 452053500 ps
CPU time 0.75 seconds
Started Oct 15 12:56:48 PM UTC 24
Finished Oct 15 12:57:03 PM UTC 24
Peak memory 210688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414442796 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_same_csr_outstanding.2414442796
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.3036078251
Short name T65
Test name
Test status
Simulation time 417613088 ps
CPU time 2.21 seconds
Started Oct 15 12:56:46 PM UTC 24
Finished Oct 15 12:57:07 PM UTC 24
Peak memory 211064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036078251 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.3036078251
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.3152402690
Short name T1001
Test name
Test status
Simulation time 60749644 ps
CPU time 0.73 seconds
Started Oct 15 12:56:58 PM UTC 24
Finished Oct 15 12:57:02 PM UTC 24
Peak memory 210756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3152402690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_w
ith_rand_reset.3152402690
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.578661537
Short name T123
Test name
Test status
Simulation time 33815841 ps
CPU time 0.59 seconds
Started Oct 15 12:56:52 PM UTC 24
Finished Oct 15 12:56:57 PM UTC 24
Peak memory 208392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578661537 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.578661537
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.1684090331
Short name T170
Test name
Test status
Simulation time 29724441 ps
CPU time 0.54 seconds
Started Oct 15 12:56:50 PM UTC 24
Finished Oct 15 12:56:52 PM UTC 24
Peak memory 206348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684090331 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.1684090331
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.190791079
Short name T1005
Test name
Test status
Simulation time 203274638 ps
CPU time 0.88 seconds
Started Oct 15 12:56:58 PM UTC 24
Finished Oct 15 12:57:03 PM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190791079 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_same_csr_outstanding.190791079
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.3909928460
Short name T997
Test name
Test status
Simulation time 45528609 ps
CPU time 1.68 seconds
Started Oct 15 12:56:48 PM UTC 24
Finished Oct 15 12:56:58 PM UTC 24
Peak memory 210744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909928460 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.3909928460
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.2604876752
Short name T66
Test name
Test status
Simulation time 203950066 ps
CPU time 1.45 seconds
Started Oct 15 12:56:48 PM UTC 24
Finished Oct 15 12:56:58 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604876752 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.2604876752
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.349159132
Short name T1000
Test name
Test status
Simulation time 85897770 ps
CPU time 0.84 seconds
Started Oct 15 12:56:59 PM UTC 24
Finished Oct 15 12:57:02 PM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=349159132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_wi
th_rand_reset.349159132
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.3855808789
Short name T999
Test name
Test status
Simulation time 18388933 ps
CPU time 0.54 seconds
Started Oct 15 12:56:59 PM UTC 24
Finished Oct 15 12:57:01 PM UTC 24
Peak memory 208396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855808789 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.3855808789
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.2676899044
Short name T1002
Test name
Test status
Simulation time 40229119 ps
CPU time 0.55 seconds
Started Oct 15 12:56:58 PM UTC 24
Finished Oct 15 12:57:02 PM UTC 24
Peak memory 206348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676899044 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.2676899044
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.233296665
Short name T135
Test name
Test status
Simulation time 30329984 ps
CPU time 0.68 seconds
Started Oct 15 12:56:59 PM UTC 24
Finished Oct 15 12:57:02 PM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233296665 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_same_csr_outstanding.233296665
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.1847341454
Short name T1006
Test name
Test status
Simulation time 318894465 ps
CPU time 1.66 seconds
Started Oct 15 12:56:58 PM UTC 24
Finished Oct 15 12:57:04 PM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847341454 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.1847341454
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.3461213136
Short name T67
Test name
Test status
Simulation time 117934502 ps
CPU time 1.04 seconds
Started Oct 15 12:56:58 PM UTC 24
Finished Oct 15 12:57:03 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461213136 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.3461213136
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3146143039
Short name T1028
Test name
Test status
Simulation time 61478808 ps
CPU time 1.21 seconds
Started Oct 15 12:57:04 PM UTC 24
Finished Oct 15 12:57:06 PM UTC 24
Peak memory 210556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3146143039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_w
ith_rand_reset.3146143039
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.3212316012
Short name T124
Test name
Test status
Simulation time 32667751 ps
CPU time 0.73 seconds
Started Oct 15 12:57:03 PM UTC 24
Finished Oct 15 12:57:05 PM UTC 24
Peak memory 208392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212316012 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.3212316012
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.1102544402
Short name T172
Test name
Test status
Simulation time 72790717 ps
CPU time 0.7 seconds
Started Oct 15 12:57:03 PM UTC 24
Finished Oct 15 12:57:05 PM UTC 24
Peak memory 206324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102544402 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.1102544402
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.859205001
Short name T1026
Test name
Test status
Simulation time 48621550 ps
CPU time 1.04 seconds
Started Oct 15 12:57:03 PM UTC 24
Finished Oct 15 12:57:06 PM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859205001 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_same_csr_outstanding.859205001
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.1733262000
Short name T1008
Test name
Test status
Simulation time 50977132 ps
CPU time 1.16 seconds
Started Oct 15 12:57:02 PM UTC 24
Finished Oct 15 12:57:04 PM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733262000 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.1733262000
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2391989230
Short name T1007
Test name
Test status
Simulation time 413226542 ps
CPU time 1.04 seconds
Started Oct 15 12:57:02 PM UTC 24
Finished Oct 15 12:57:04 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391989230 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.2391989230
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.363799446
Short name T6
Test name
Test status
Simulation time 35529995 ps
CPU time 1.21 seconds
Started Oct 15 12:52:38 PM UTC 24
Finished Oct 15 12:52:40 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363799446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.363799446
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.2260047469
Short name T14
Test name
Test status
Simulation time 61604811 ps
CPU time 1.32 seconds
Started Oct 15 12:52:44 PM UTC 24
Finished Oct 15 12:52:47 PM UTC 24
Peak memory 211252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260047469 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disable_rom_integrity_check.2260047469
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.239147371
Short name T11
Test name
Test status
Simulation time 107592515 ps
CPU time 1.54 seconds
Started Oct 15 12:52:43 PM UTC 24
Finished Oct 15 12:52:46 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239147371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.239147371
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.2008364306
Short name T13
Test name
Test status
Simulation time 70487520 ps
CPU time 0.93 seconds
Started Oct 15 12:52:43 PM UTC 24
Finished Oct 15 12:52:45 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008364306 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.2008364306
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.1062912026
Short name T4
Test name
Test status
Simulation time 273439425 ps
CPU time 2.11 seconds
Started Oct 15 12:52:35 PM UTC 24
Finished Oct 15 12:52:38 PM UTC 24
Peak memory 211184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062912026 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wakeup_race.1062912026
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.2411854773
Short name T2
Test name
Test status
Simulation time 138884449 ps
CPU time 1.3 seconds
Started Oct 15 12:52:34 PM UTC 24
Finished Oct 15 12:52:37 PM UTC 24
Peak memory 211140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411854773 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.2411854773
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.2972312602
Short name T20
Test name
Test status
Simulation time 469934549 ps
CPU time 1.82 seconds
Started Oct 15 12:52:46 PM UTC 24
Finished Oct 15 12:52:49 PM UTC 24
Peak memory 238044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972312602 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.2972312602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2801620720
Short name T37
Test name
Test status
Simulation time 842058528 ps
CPU time 5.9 seconds
Started Oct 15 12:52:40 PM UTC 24
Finished Oct 15 12:52:47 PM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801620720 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.2801620720
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1925562757
Short name T7
Test name
Test status
Simulation time 73790905 ps
CPU time 1.54 seconds
Started Oct 15 12:52:40 PM UTC 24
Finished Oct 15 12:52:43 PM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925562757 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1925562757
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.1442129561
Short name T1
Test name
Test status
Simulation time 86719032 ps
CPU time 1.04 seconds
Started Oct 15 12:52:32 PM UTC 24
Finished Oct 15 12:52:34 PM UTC 24
Peak memory 209496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442129561 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.1442129561
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.3307969487
Short name T16
Test name
Test status
Simulation time 2808012771 ps
CPU time 4.04 seconds
Started Oct 15 12:52:47 PM UTC 24
Finished Oct 15 12:52:52 PM UTC 24
Peak memory 212616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307969487 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.3307969487
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.4021307967
Short name T3
Test name
Test status
Simulation time 376457592 ps
CPU time 1.42 seconds
Started Oct 15 12:52:35 PM UTC 24
Finished Oct 15 12:52:38 PM UTC 24
Peak memory 210348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021307967 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.4021307967
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.3423081823
Short name T5
Test name
Test status
Simulation time 123588244 ps
CPU time 1.02 seconds
Started Oct 15 12:52:37 PM UTC 24
Finished Oct 15 12:52:39 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423081823 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.3423081823
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.2468235850
Short name T15
Test name
Test status
Simulation time 44788405 ps
CPU time 1.32 seconds
Started Oct 15 12:52:50 PM UTC 24
Finished Oct 15 12:52:52 PM UTC 24
Peak memory 211300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468235850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.2468235850
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.3489579049
Short name T12
Test name
Test status
Simulation time 38602770 ps
CPU time 0.91 seconds
Started Oct 15 12:52:51 PM UTC 24
Finished Oct 15 12:52:53 PM UTC 24
Peak memory 209124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489579049 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_malfunc.3489579049
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.3583768850
Short name T151
Test name
Test status
Simulation time 200858757 ps
CPU time 1.5 seconds
Started Oct 15 12:52:53 PM UTC 24
Finished Oct 15 12:52:56 PM UTC 24
Peak memory 209240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583768850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.3583768850
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.2242660540
Short name T18
Test name
Test status
Simulation time 53585702 ps
CPU time 1.11 seconds
Started Oct 15 12:52:53 PM UTC 24
Finished Oct 15 12:52:55 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242660540 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.2242660540
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.4237031235
Short name T39
Test name
Test status
Simulation time 45775235 ps
CPU time 1.03 seconds
Started Oct 15 12:52:52 PM UTC 24
Finished Oct 15 12:52:54 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237031235 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.4237031235
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.2732502407
Short name T42
Test name
Test status
Simulation time 56676664 ps
CPU time 0.95 seconds
Started Oct 15 12:52:54 PM UTC 24
Finished Oct 15 12:52:56 PM UTC 24
Peak memory 212908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732502407 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invalid.2732502407
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.1901579089
Short name T33
Test name
Test status
Simulation time 110447909 ps
CPU time 1.61 seconds
Started Oct 15 12:52:47 PM UTC 24
Finished Oct 15 12:52:50 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901579089 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wakeup_race.1901579089
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.1654872401
Short name T32
Test name
Test status
Simulation time 50342987 ps
CPU time 1.31 seconds
Started Oct 15 12:52:47 PM UTC 24
Finished Oct 15 12:52:49 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654872401 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.1654872401
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.3175212889
Short name T38
Test name
Test status
Simulation time 119251761 ps
CPU time 1.21 seconds
Started Oct 15 12:52:54 PM UTC 24
Finished Oct 15 12:52:56 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175212889 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.3175212889
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.1311122110
Short name T59
Test name
Test status
Simulation time 301860220 ps
CPU time 2.27 seconds
Started Oct 15 12:52:51 PM UTC 24
Finished Oct 15 12:52:54 PM UTC 24
Peak memory 211420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311122110 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_ctrl_config_regwen.1311122110
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3020852440
Short name T26
Test name
Test status
Simulation time 818175507 ps
CPU time 3.4 seconds
Started Oct 15 12:52:50 PM UTC 24
Finished Oct 15 12:52:54 PM UTC 24
Peak memory 212500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020852440 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.3020852440
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.193456762
Short name T145
Test name
Test status
Simulation time 899629882 ps
CPU time 4.12 seconds
Started Oct 15 12:52:50 PM UTC 24
Finished Oct 15 12:52:55 PM UTC 24
Peak memory 212432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193456762 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_inters
ig_mubi.193456762
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.1883908649
Short name T36
Test name
Test status
Simulation time 172601138 ps
CPU time 1.13 seconds
Started Oct 15 12:52:50 PM UTC 24
Finished Oct 15 12:52:52 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883908649 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_mubi.1883908649
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.2101311626
Short name T31
Test name
Test status
Simulation time 60257216 ps
CPU time 1 seconds
Started Oct 15 12:52:47 PM UTC 24
Finished Oct 15 12:52:49 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101311626 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.2101311626
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.3760521209
Short name T24
Test name
Test status
Simulation time 5140731667 ps
CPU time 14.02 seconds
Started Oct 15 12:52:55 PM UTC 24
Finished Oct 15 12:53:10 PM UTC 24
Peak memory 212940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3760521209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr
_stress_all_with_rand_reset.3760521209
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.839762135
Short name T34
Test name
Test status
Simulation time 67286048 ps
CPU time 1.24 seconds
Started Oct 15 12:52:48 PM UTC 24
Finished Oct 15 12:52:50 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839762135 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.839762135
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.3305621611
Short name T35
Test name
Test status
Simulation time 312279200 ps
CPU time 1.69 seconds
Started Oct 15 12:52:48 PM UTC 24
Finished Oct 15 12:52:51 PM UTC 24
Peak memory 211384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305621611 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.3305621611
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.816566532
Short name T277
Test name
Test status
Simulation time 38371148 ps
CPU time 1.16 seconds
Started Oct 15 12:53:42 PM UTC 24
Finished Oct 15 12:53:44 PM UTC 24
Peak memory 210356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816566532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.816566532
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.1958153229
Short name T287
Test name
Test status
Simulation time 82655105 ps
CPU time 1.07 seconds
Started Oct 15 12:53:44 PM UTC 24
Finished Oct 15 12:53:46 PM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958153229 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disable_rom_integrity_check.1958153229
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.2796303500
Short name T280
Test name
Test status
Simulation time 46415621 ps
CPU time 0.88 seconds
Started Oct 15 12:53:43 PM UTC 24
Finished Oct 15 12:53:45 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796303500 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_malfunc.2796303500
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.2287637881
Short name T284
Test name
Test status
Simulation time 112156534 ps
CPU time 1.39 seconds
Started Oct 15 12:53:43 PM UTC 24
Finished Oct 15 12:53:46 PM UTC 24
Peak memory 209060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287637881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.2287637881
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.3669228077
Short name T285
Test name
Test status
Simulation time 24527950 ps
CPU time 0.96 seconds
Started Oct 15 12:53:44 PM UTC 24
Finished Oct 15 12:53:46 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669228077 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.3669228077
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.1622508005
Short name T281
Test name
Test status
Simulation time 32757815 ps
CPU time 0.92 seconds
Started Oct 15 12:53:43 PM UTC 24
Finished Oct 15 12:53:45 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622508005 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.1622508005
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.3717334875
Short name T286
Test name
Test status
Simulation time 138024071 ps
CPU time 0.86 seconds
Started Oct 15 12:53:44 PM UTC 24
Finished Oct 15 12:53:46 PM UTC 24
Peak memory 212968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717334875 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_invalid.3717334875
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.3222966042
Short name T276
Test name
Test status
Simulation time 515662967 ps
CPU time 1.18 seconds
Started Oct 15 12:53:41 PM UTC 24
Finished Oct 15 12:53:44 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222966042 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wakeup_race.3222966042
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.3960776333
Short name T275
Test name
Test status
Simulation time 165035019 ps
CPU time 1.27 seconds
Started Oct 15 12:53:41 PM UTC 24
Finished Oct 15 12:53:44 PM UTC 24
Peak memory 211200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960776333 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.3960776333
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.142686293
Short name T289
Test name
Test status
Simulation time 112973074 ps
CPU time 1.54 seconds
Started Oct 15 12:53:44 PM UTC 24
Finished Oct 15 12:53:47 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142686293 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.142686293
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.4018725872
Short name T282
Test name
Test status
Simulation time 231519006 ps
CPU time 1.09 seconds
Started Oct 15 12:53:43 PM UTC 24
Finished Oct 15 12:53:45 PM UTC 24
Peak memory 210412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018725872 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_ctrl_config_regwen.4018725872
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2798093031
Short name T279
Test name
Test status
Simulation time 1000956914 ps
CPU time 2.11 seconds
Started Oct 15 12:53:42 PM UTC 24
Finished Oct 15 12:53:45 PM UTC 24
Peak memory 212536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798093031 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2798093031
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.928189845
Short name T290
Test name
Test status
Simulation time 1016083241 ps
CPU time 3.89 seconds
Started Oct 15 12:53:43 PM UTC 24
Finished Oct 15 12:53:48 PM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928189845 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.928189845
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1896988568
Short name T283
Test name
Test status
Simulation time 74139457 ps
CPU time 1.24 seconds
Started Oct 15 12:53:43 PM UTC 24
Finished Oct 15 12:53:45 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896988568 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1896988568
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.3014399307
Short name T271
Test name
Test status
Simulation time 53151276 ps
CPU time 0.94 seconds
Started Oct 15 12:53:41 PM UTC 24
Finished Oct 15 12:53:43 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014399307 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.3014399307
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.3438719560
Short name T295
Test name
Test status
Simulation time 8078268495 ps
CPU time 3.53 seconds
Started Oct 15 12:53:45 PM UTC 24
Finished Oct 15 12:53:49 PM UTC 24
Peak memory 212856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438719560 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.3438719560
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.3745870579
Short name T320
Test name
Test status
Simulation time 1959308771 ps
CPU time 8.57 seconds
Started Oct 15 12:53:45 PM UTC 24
Finished Oct 15 12:53:54 PM UTC 24
Peak memory 212668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3745870579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmg
r_stress_all_with_rand_reset.3745870579
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.4051224870
Short name T274
Test name
Test status
Simulation time 258726162 ps
CPU time 1.04 seconds
Started Oct 15 12:53:42 PM UTC 24
Finished Oct 15 12:53:44 PM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051224870 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.4051224870
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/10.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.206119777
Short name T293
Test name
Test status
Simulation time 70444250 ps
CPU time 1.06 seconds
Started Oct 15 12:53:46 PM UTC 24
Finished Oct 15 12:53:48 PM UTC 24
Peak memory 210620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206119777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.206119777
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.3720616764
Short name T304
Test name
Test status
Simulation time 79278645 ps
CPU time 0.8 seconds
Started Oct 15 12:53:49 PM UTC 24
Finished Oct 15 12:53:51 PM UTC 24
Peak memory 209384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720616764 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disable_rom_integrity_check.3720616764
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.1094767372
Short name T297
Test name
Test status
Simulation time 33117841 ps
CPU time 0.82 seconds
Started Oct 15 12:53:47 PM UTC 24
Finished Oct 15 12:53:49 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094767372 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_malfunc.1094767372
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.153921569
Short name T302
Test name
Test status
Simulation time 111175396 ps
CPU time 1.16 seconds
Started Oct 15 12:53:47 PM UTC 24
Finished Oct 15 12:53:50 PM UTC 24
Peak memory 209184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153921569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.153921569
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.4092635430
Short name T305
Test name
Test status
Simulation time 65239812 ps
CPU time 0.97 seconds
Started Oct 15 12:53:49 PM UTC 24
Finished Oct 15 12:53:51 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092635430 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.4092635430
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.1431533442
Short name T296
Test name
Test status
Simulation time 80029127 ps
CPU time 0.76 seconds
Started Oct 15 12:53:47 PM UTC 24
Finished Oct 15 12:53:49 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431533442 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.1431533442
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.4260735790
Short name T306
Test name
Test status
Simulation time 52897690 ps
CPU time 0.93 seconds
Started Oct 15 12:53:49 PM UTC 24
Finished Oct 15 12:53:51 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260735790 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invalid.4260735790
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.850700720
Short name T291
Test name
Test status
Simulation time 326877397 ps
CPU time 1.14 seconds
Started Oct 15 12:53:46 PM UTC 24
Finished Oct 15 12:53:48 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850700720 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_wakeup_race.850700720
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.3714278823
Short name T294
Test name
Test status
Simulation time 66776074 ps
CPU time 1.52 seconds
Started Oct 15 12:53:46 PM UTC 24
Finished Oct 15 12:53:49 PM UTC 24
Peak memory 211200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714278823 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.3714278823
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.3993250576
Short name T307
Test name
Test status
Simulation time 108944790 ps
CPU time 1.26 seconds
Started Oct 15 12:53:49 PM UTC 24
Finished Oct 15 12:53:51 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993250576 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.3993250576
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.3537373122
Short name T303
Test name
Test status
Simulation time 194023962 ps
CPU time 1.66 seconds
Started Oct 15 12:53:47 PM UTC 24
Finished Oct 15 12:53:50 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537373122 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_ctrl_config_regwen.3537373122
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4130243826
Short name T300
Test name
Test status
Simulation time 963914898 ps
CPU time 2.24 seconds
Started Oct 15 12:53:46 PM UTC 24
Finished Oct 15 12:53:50 PM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130243826 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4130243826
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1126235683
Short name T298
Test name
Test status
Simulation time 1242417033 ps
CPU time 2.28 seconds
Started Oct 15 12:53:46 PM UTC 24
Finished Oct 15 12:53:50 PM UTC 24
Peak memory 212572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126235683 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1126235683
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.1878682549
Short name T299
Test name
Test status
Simulation time 92383777 ps
CPU time 1.04 seconds
Started Oct 15 12:53:47 PM UTC 24
Finished Oct 15 12:53:50 PM UTC 24
Peak memory 210988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878682549 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_mubi.1878682549
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.694519750
Short name T288
Test name
Test status
Simulation time 29176607 ps
CPU time 1.05 seconds
Started Oct 15 12:53:45 PM UTC 24
Finished Oct 15 12:53:47 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694519750 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.694519750
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.2547896262
Short name T317
Test name
Test status
Simulation time 1403115541 ps
CPU time 2.61 seconds
Started Oct 15 12:53:50 PM UTC 24
Finished Oct 15 12:53:54 PM UTC 24
Peak memory 212364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547896262 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.2547896262
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.3379063265
Short name T77
Test name
Test status
Simulation time 3545686824 ps
CPU time 15.72 seconds
Started Oct 15 12:53:49 PM UTC 24
Finished Oct 15 12:54:06 PM UTC 24
Peak memory 212668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3379063265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmg
r_stress_all_with_rand_reset.3379063265
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.338786840
Short name T292
Test name
Test status
Simulation time 120774771 ps
CPU time 0.95 seconds
Started Oct 15 12:53:46 PM UTC 24
Finished Oct 15 12:53:48 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338786840 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.338786840
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.1401153820
Short name T301
Test name
Test status
Simulation time 320556991 ps
CPU time 2.53 seconds
Started Oct 15 12:53:46 PM UTC 24
Finished Oct 15 12:53:50 PM UTC 24
Peak memory 212408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401153820 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.1401153820
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/11.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.3167110956
Short name T315
Test name
Test status
Simulation time 35622460 ps
CPU time 1.14 seconds
Started Oct 15 12:53:51 PM UTC 24
Finished Oct 15 12:53:54 PM UTC 24
Peak memory 209924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167110956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.3167110956
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.850411018
Short name T314
Test name
Test status
Simulation time 30382803 ps
CPU time 1 seconds
Started Oct 15 12:53:52 PM UTC 24
Finished Oct 15 12:53:54 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850411018 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst_malfunc.850411018
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.4278086335
Short name T321
Test name
Test status
Simulation time 112125853 ps
CPU time 1.4 seconds
Started Oct 15 12:53:52 PM UTC 24
Finished Oct 15 12:53:54 PM UTC 24
Peak memory 209060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278086335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.4278086335
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.2981530852
Short name T316
Test name
Test status
Simulation time 57694271 ps
CPU time 0.69 seconds
Started Oct 15 12:53:52 PM UTC 24
Finished Oct 15 12:53:54 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981530852 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.2981530852
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.1342352185
Short name T319
Test name
Test status
Simulation time 45623551 ps
CPU time 1.02 seconds
Started Oct 15 12:53:52 PM UTC 24
Finished Oct 15 12:53:54 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342352185 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.1342352185
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.2368034848
Short name T323
Test name
Test status
Simulation time 307544172 ps
CPU time 1.04 seconds
Started Oct 15 12:53:53 PM UTC 24
Finished Oct 15 12:53:55 PM UTC 24
Peak memory 212968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368034848 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invalid.2368034848
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.4115762238
Short name T312
Test name
Test status
Simulation time 193044311 ps
CPU time 1.85 seconds
Started Oct 15 12:53:50 PM UTC 24
Finished Oct 15 12:53:53 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115762238 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_wakeup_race.4115762238
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.17116232
Short name T308
Test name
Test status
Simulation time 47913736 ps
CPU time 1.28 seconds
Started Oct 15 12:53:50 PM UTC 24
Finished Oct 15 12:53:52 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17116232 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.17116232
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.4194417483
Short name T324
Test name
Test status
Simulation time 93951494 ps
CPU time 1.43 seconds
Started Oct 15 12:53:53 PM UTC 24
Finished Oct 15 12:53:56 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194417483 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.4194417483
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.425478593
Short name T313
Test name
Test status
Simulation time 35783778 ps
CPU time 0.85 seconds
Started Oct 15 12:53:52 PM UTC 24
Finished Oct 15 12:53:54 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425478593 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_ctrl_config_regwen.425478593
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.379354342
Short name T326
Test name
Test status
Simulation time 794939186 ps
CPU time 3.57 seconds
Started Oct 15 12:53:51 PM UTC 24
Finished Oct 15 12:53:56 PM UTC 24
Peak memory 212488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379354342 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.379354342
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.707158469
Short name T325
Test name
Test status
Simulation time 896705748 ps
CPU time 3.09 seconds
Started Oct 15 12:53:51 PM UTC 24
Finished Oct 15 12:53:56 PM UTC 24
Peak memory 212624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707158469 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.707158469
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3147147108
Short name T318
Test name
Test status
Simulation time 93567293 ps
CPU time 1.19 seconds
Started Oct 15 12:53:52 PM UTC 24
Finished Oct 15 12:53:54 PM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147147108 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3147147108
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.2866928399
Short name T278
Test name
Test status
Simulation time 30019805 ps
CPU time 1.04 seconds
Started Oct 15 12:53:50 PM UTC 24
Finished Oct 15 12:53:52 PM UTC 24
Peak memory 209020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866928399 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.2866928399
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all.3442779883
Short name T331
Test name
Test status
Simulation time 353137038 ps
CPU time 1.46 seconds
Started Oct 15 12:53:54 PM UTC 24
Finished Oct 15 12:53:57 PM UTC 24
Peak memory 211324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442779883 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.3442779883
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all_with_rand_reset.1638013223
Short name T368
Test name
Test status
Simulation time 3374171971 ps
CPU time 12.25 seconds
Started Oct 15 12:53:53 PM UTC 24
Finished Oct 15 12:54:07 PM UTC 24
Peak memory 212656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1638013223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmg
r_stress_all_with_rand_reset.1638013223
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.1296788975
Short name T310
Test name
Test status
Simulation time 325358705 ps
CPU time 1.82 seconds
Started Oct 15 12:53:50 PM UTC 24
Finished Oct 15 12:53:53 PM UTC 24
Peak memory 210080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296788975 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.1296788975
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.2089102551
Short name T309
Test name
Test status
Simulation time 233786976 ps
CPU time 1.36 seconds
Started Oct 15 12:53:50 PM UTC 24
Finished Oct 15 12:53:53 PM UTC 24
Peak memory 211000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089102551 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.2089102551
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/12.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.2950186900
Short name T329
Test name
Test status
Simulation time 25996781 ps
CPU time 1 seconds
Started Oct 15 12:53:55 PM UTC 24
Finished Oct 15 12:53:57 PM UTC 24
Peak memory 211420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950186900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.2950186900
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.2489304996
Short name T336
Test name
Test status
Simulation time 29364154 ps
CPU time 0.98 seconds
Started Oct 15 12:53:56 PM UTC 24
Finished Oct 15 12:53:58 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489304996 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_malfunc.2489304996
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.2290565872
Short name T341
Test name
Test status
Simulation time 383256980 ps
CPU time 1.27 seconds
Started Oct 15 12:53:56 PM UTC 24
Finished Oct 15 12:53:59 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290565872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.2290565872
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.3063159503
Short name T338
Test name
Test status
Simulation time 50987634 ps
CPU time 0.9 seconds
Started Oct 15 12:53:56 PM UTC 24
Finished Oct 15 12:53:58 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063159503 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.3063159503
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_global_esc.4049638220
Short name T335
Test name
Test status
Simulation time 68097923 ps
CPU time 0.92 seconds
Started Oct 15 12:53:56 PM UTC 24
Finished Oct 15 12:53:58 PM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049638220 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.4049638220
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_invalid.293200853
Short name T344
Test name
Test status
Simulation time 94599588 ps
CPU time 1.06 seconds
Started Oct 15 12:53:58 PM UTC 24
Finished Oct 15 12:54:01 PM UTC 24
Peak memory 212960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293200853 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_invalid.293200853
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.1921197810
Short name T332
Test name
Test status
Simulation time 136297428 ps
CPU time 1.59 seconds
Started Oct 15 12:53:55 PM UTC 24
Finished Oct 15 12:53:57 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921197810 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_wakeup_race.1921197810
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.3292923837
Short name T327
Test name
Test status
Simulation time 23112741 ps
CPU time 0.81 seconds
Started Oct 15 12:53:55 PM UTC 24
Finished Oct 15 12:53:56 PM UTC 24
Peak memory 208988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292923837 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.3292923837
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset_invalid.3213101133
Short name T345
Test name
Test status
Simulation time 109492436 ps
CPU time 1.26 seconds
Started Oct 15 12:53:58 PM UTC 24
Finished Oct 15 12:54:01 PM UTC 24
Peak memory 221196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213101133 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.3213101133
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.762953659
Short name T339
Test name
Test status
Simulation time 174881512 ps
CPU time 1.18 seconds
Started Oct 15 12:53:56 PM UTC 24
Finished Oct 15 12:53:58 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762953659 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_ctrl_config_regwen.762953659
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3554070759
Short name T337
Test name
Test status
Simulation time 795295788 ps
CPU time 2.37 seconds
Started Oct 15 12:53:55 PM UTC 24
Finished Oct 15 12:53:58 PM UTC 24
Peak memory 212356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554070759 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3554070759
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2744282631
Short name T340
Test name
Test status
Simulation time 1215316087 ps
CPU time 2.63 seconds
Started Oct 15 12:53:55 PM UTC 24
Finished Oct 15 12:53:58 PM UTC 24
Peak memory 212308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744282631 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2744282631
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.4003985700
Short name T333
Test name
Test status
Simulation time 55130320 ps
CPU time 1.4 seconds
Started Oct 15 12:53:55 PM UTC 24
Finished Oct 15 12:53:57 PM UTC 24
Peak memory 211252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003985700 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_mubi.4003985700
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.849568916
Short name T328
Test name
Test status
Simulation time 30573162 ps
CPU time 1.08 seconds
Started Oct 15 12:53:54 PM UTC 24
Finished Oct 15 12:53:57 PM UTC 24
Peak memory 208728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849568916 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.849568916
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all.1905813242
Short name T361
Test name
Test status
Simulation time 1503224646 ps
CPU time 5.18 seconds
Started Oct 15 12:53:58 PM UTC 24
Finished Oct 15 12:54:05 PM UTC 24
Peak memory 212680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905813242 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.1905813242
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.1298636720
Short name T146
Test name
Test status
Simulation time 4067118571 ps
CPU time 8.69 seconds
Started Oct 15 12:53:58 PM UTC 24
Finished Oct 15 12:54:08 PM UTC 24
Peak memory 212748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1298636720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmg
r_stress_all_with_rand_reset.1298636720
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.1667896232
Short name T330
Test name
Test status
Simulation time 368073780 ps
CPU time 1.22 seconds
Started Oct 15 12:53:55 PM UTC 24
Finished Oct 15 12:53:57 PM UTC 24
Peak memory 210464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667896232 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.1667896232
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.1716508999
Short name T334
Test name
Test status
Simulation time 251836832 ps
CPU time 1.92 seconds
Started Oct 15 12:53:55 PM UTC 24
Finished Oct 15 12:53:58 PM UTC 24
Peak memory 211276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716508999 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.1716508999
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/13.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.3319429725
Short name T349
Test name
Test status
Simulation time 36211915 ps
CPU time 1.04 seconds
Started Oct 15 12:54:00 PM UTC 24
Finished Oct 15 12:54:02 PM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319429725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.3319429725
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.2568933701
Short name T356
Test name
Test status
Simulation time 94721684 ps
CPU time 1.1 seconds
Started Oct 15 12:54:01 PM UTC 24
Finished Oct 15 12:54:04 PM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568933701 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_disable_rom_integrity_check.2568933701
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.2392723321
Short name T350
Test name
Test status
Simulation time 37616987 ps
CPU time 0.91 seconds
Started Oct 15 12:54:00 PM UTC 24
Finished Oct 15 12:54:02 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392723321 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_malfunc.2392723321
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_escalation_timeout.1943876469
Short name T353
Test name
Test status
Simulation time 110094350 ps
CPU time 1.27 seconds
Started Oct 15 12:54:00 PM UTC 24
Finished Oct 15 12:54:02 PM UTC 24
Peak memory 209060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943876469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.1943876469
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.3669640733
Short name T355
Test name
Test status
Simulation time 38688113 ps
CPU time 0.92 seconds
Started Oct 15 12:54:01 PM UTC 24
Finished Oct 15 12:54:03 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669640733 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.3669640733
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_global_esc.2990009756
Short name T351
Test name
Test status
Simulation time 29453503 ps
CPU time 0.87 seconds
Started Oct 15 12:54:00 PM UTC 24
Finished Oct 15 12:54:02 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990009756 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.2990009756
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_invalid.2667353643
Short name T357
Test name
Test status
Simulation time 75225860 ps
CPU time 1.03 seconds
Started Oct 15 12:54:01 PM UTC 24
Finished Oct 15 12:54:04 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667353643 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invalid.2667353643
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_wakeup_race.2181758115
Short name T347
Test name
Test status
Simulation time 340390909 ps
CPU time 2.01 seconds
Started Oct 15 12:53:58 PM UTC 24
Finished Oct 15 12:54:02 PM UTC 24
Peak memory 210392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181758115 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_wakeup_race.2181758115
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset.4278986668
Short name T343
Test name
Test status
Simulation time 62693034 ps
CPU time 0.88 seconds
Started Oct 15 12:53:58 PM UTC 24
Finished Oct 15 12:54:00 PM UTC 24
Peak memory 209556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278986668 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.4278986668
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.1914590814
Short name T358
Test name
Test status
Simulation time 103235665 ps
CPU time 1.46 seconds
Started Oct 15 12:54:01 PM UTC 24
Finished Oct 15 12:54:04 PM UTC 24
Peak memory 211016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914590814 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.1914590814
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.983569347
Short name T354
Test name
Test status
Simulation time 353486203 ps
CPU time 1.54 seconds
Started Oct 15 12:54:00 PM UTC 24
Finished Oct 15 12:54:03 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983569347 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_ctrl_config_regwen.983569347
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.57481330
Short name T360
Test name
Test status
Simulation time 1211907975 ps
CPU time 3.45 seconds
Started Oct 15 12:54:00 PM UTC 24
Finished Oct 15 12:54:04 PM UTC 24
Peak memory 212800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57481330 -ass
ert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_intersig
_mubi.57481330
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3698096446
Short name T359
Test name
Test status
Simulation time 947439396 ps
CPU time 3.4 seconds
Started Oct 15 12:54:00 PM UTC 24
Finished Oct 15 12:54:04 PM UTC 24
Peak memory 212688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698096446 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3698096446
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3216733255
Short name T352
Test name
Test status
Simulation time 145817429 ps
CPU time 1.31 seconds
Started Oct 15 12:54:00 PM UTC 24
Finished Oct 15 12:54:02 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216733255 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_mubi.3216733255
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_smoke.2479367704
Short name T342
Test name
Test status
Simulation time 33735539 ps
CPU time 0.94 seconds
Started Oct 15 12:53:58 PM UTC 24
Finished Oct 15 12:54:00 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479367704 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.2479367704
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all.1748480229
Short name T367
Test name
Test status
Simulation time 935220596 ps
CPU time 2.05 seconds
Started Oct 15 12:54:03 PM UTC 24
Finished Oct 15 12:54:06 PM UTC 24
Peak memory 212536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748480229 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.1748480229
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all_with_rand_reset.3701114563
Short name T78
Test name
Test status
Simulation time 4091637627 ps
CPU time 14.74 seconds
Started Oct 15 12:54:01 PM UTC 24
Finished Oct 15 12:54:18 PM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3701114563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmg
r_stress_all_with_rand_reset.3701114563
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup.2338452349
Short name T348
Test name
Test status
Simulation time 277643404 ps
CPU time 2.17 seconds
Started Oct 15 12:53:58 PM UTC 24
Finished Oct 15 12:54:02 PM UTC 24
Peak memory 211136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338452349 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.2338452349
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.2423858494
Short name T346
Test name
Test status
Simulation time 311829101 ps
CPU time 1.8 seconds
Started Oct 15 12:53:59 PM UTC 24
Finished Oct 15 12:54:02 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423858494 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.2423858494
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/14.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_aborted_low_power.999056961
Short name T369
Test name
Test status
Simulation time 29784130 ps
CPU time 1.41 seconds
Started Oct 15 12:54:04 PM UTC 24
Finished Oct 15 12:54:07 PM UTC 24
Peak memory 210848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999056961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.999056961
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.12745516
Short name T180
Test name
Test status
Simulation time 93940256 ps
CPU time 0.95 seconds
Started Oct 15 12:54:06 PM UTC 24
Finished Oct 15 12:54:08 PM UTC 24
Peak memory 209060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12745516 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disable_rom_integrity_check.12745516
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.1351760537
Short name T371
Test name
Test status
Simulation time 29413086 ps
CPU time 1.08 seconds
Started Oct 15 12:54:04 PM UTC 24
Finished Oct 15 12:54:07 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351760537 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_malfunc.1351760537
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.519610573
Short name T377
Test name
Test status
Simulation time 407622227 ps
CPU time 1.19 seconds
Started Oct 15 12:54:06 PM UTC 24
Finished Oct 15 12:54:08 PM UTC 24
Peak memory 209184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519610573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.519610573
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.2751848185
Short name T376
Test name
Test status
Simulation time 58094368 ps
CPU time 1.09 seconds
Started Oct 15 12:54:06 PM UTC 24
Finished Oct 15 12:54:08 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751848185 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.2751848185
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_global_esc.1563252614
Short name T372
Test name
Test status
Simulation time 57670010 ps
CPU time 0.92 seconds
Started Oct 15 12:54:06 PM UTC 24
Finished Oct 15 12:54:08 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563252614 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.1563252614
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_invalid.2355402316
Short name T311
Test name
Test status
Simulation time 50417427 ps
CPU time 1.1 seconds
Started Oct 15 12:54:06 PM UTC 24
Finished Oct 15 12:54:08 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355402316 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_invalid.2355402316
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_wakeup_race.2876132303
Short name T365
Test name
Test status
Simulation time 131703770 ps
CPU time 1.53 seconds
Started Oct 15 12:54:03 PM UTC 24
Finished Oct 15 12:54:06 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876132303 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_wakeup_race.2876132303
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset.2287903553
Short name T366
Test name
Test status
Simulation time 88213962 ps
CPU time 1.63 seconds
Started Oct 15 12:54:03 PM UTC 24
Finished Oct 15 12:54:06 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287903553 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.2287903553
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset_invalid.4084952761
Short name T322
Test name
Test status
Simulation time 171352909 ps
CPU time 1.27 seconds
Started Oct 15 12:54:06 PM UTC 24
Finished Oct 15 12:54:09 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084952761 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.4084952761
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.2881177549
Short name T374
Test name
Test status
Simulation time 297436118 ps
CPU time 1.3 seconds
Started Oct 15 12:54:06 PM UTC 24
Finished Oct 15 12:54:08 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881177549 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_ctrl_config_regwen.2881177549
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1764327189
Short name T375
Test name
Test status
Simulation time 1069742871 ps
CPU time 2.79 seconds
Started Oct 15 12:54:04 PM UTC 24
Finished Oct 15 12:54:08 PM UTC 24
Peak memory 212432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764327189 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1764327189
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2556547863
Short name T373
Test name
Test status
Simulation time 1050747782 ps
CPU time 2.57 seconds
Started Oct 15 12:54:04 PM UTC 24
Finished Oct 15 12:54:08 PM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556547863 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2556547863
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2787810891
Short name T370
Test name
Test status
Simulation time 52508990 ps
CPU time 1.38 seconds
Started Oct 15 12:54:04 PM UTC 24
Finished Oct 15 12:54:07 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787810891 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2787810891
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.4186716545
Short name T362
Test name
Test status
Simulation time 39550494 ps
CPU time 0.98 seconds
Started Oct 15 12:54:03 PM UTC 24
Finished Oct 15 12:54:05 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186716545 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.4186716545
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.1313476005
Short name T48
Test name
Test status
Simulation time 1697341451 ps
CPU time 8.39 seconds
Started Oct 15 12:54:07 PM UTC 24
Finished Oct 15 12:54:17 PM UTC 24
Peak memory 212620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1313476005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmg
r_stress_all_with_rand_reset.1313476005
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup.790424015
Short name T363
Test name
Test status
Simulation time 71646423 ps
CPU time 0.94 seconds
Started Oct 15 12:54:03 PM UTC 24
Finished Oct 15 12:54:05 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790424015 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.790424015
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup_reset.2620277740
Short name T364
Test name
Test status
Simulation time 119767436 ps
CPU time 1.26 seconds
Started Oct 15 12:54:03 PM UTC 24
Finished Oct 15 12:54:06 PM UTC 24
Peak memory 211276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620277740 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.2620277740
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/15.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_aborted_low_power.87686260
Short name T116
Test name
Test status
Simulation time 30606420 ps
CPU time 1.17 seconds
Started Oct 15 12:54:08 PM UTC 24
Finished Oct 15 12:54:10 PM UTC 24
Peak memory 210384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87686260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=
pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.87686260
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.4133362808
Short name T388
Test name
Test status
Simulation time 75573782 ps
CPU time 1.04 seconds
Started Oct 15 12:54:09 PM UTC 24
Finished Oct 15 12:54:11 PM UTC 24
Peak memory 209384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133362808 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disable_rom_integrity_check.4133362808
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.208340126
Short name T383
Test name
Test status
Simulation time 32441359 ps
CPU time 0.79 seconds
Started Oct 15 12:54:09 PM UTC 24
Finished Oct 15 12:54:11 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208340126 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_malfunc.208340126
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_escalation_timeout.222549645
Short name T392
Test name
Test status
Simulation time 199958353 ps
CPU time 1.5 seconds
Started Oct 15 12:54:09 PM UTC 24
Finished Oct 15 12:54:12 PM UTC 24
Peak memory 209184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222549645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.222549645
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_glitch.2663044869
Short name T384
Test name
Test status
Simulation time 70718938 ps
CPU time 0.89 seconds
Started Oct 15 12:54:09 PM UTC 24
Finished Oct 15 12:54:11 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663044869 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.2663044869
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_global_esc.2071471626
Short name T386
Test name
Test status
Simulation time 101436473 ps
CPU time 0.97 seconds
Started Oct 15 12:54:09 PM UTC 24
Finished Oct 15 12:54:11 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071471626 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.2071471626
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_invalid.1680132971
Short name T389
Test name
Test status
Simulation time 75011799 ps
CPU time 1.02 seconds
Started Oct 15 12:54:09 PM UTC 24
Finished Oct 15 12:54:12 PM UTC 24
Peak memory 212968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680132971 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_invalid.1680132971
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_wakeup_race.1044877853
Short name T381
Test name
Test status
Simulation time 201551844 ps
CPU time 1.71 seconds
Started Oct 15 12:54:07 PM UTC 24
Finished Oct 15 12:54:10 PM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044877853 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_wakeup_race.1044877853
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.373819558
Short name T378
Test name
Test status
Simulation time 89835501 ps
CPU time 0.92 seconds
Started Oct 15 12:54:07 PM UTC 24
Finished Oct 15 12:54:10 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373819558 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.373819558
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset_invalid.4022250868
Short name T391
Test name
Test status
Simulation time 107466984 ps
CPU time 1.27 seconds
Started Oct 15 12:54:09 PM UTC 24
Finished Oct 15 12:54:12 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022250868 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.4022250868
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.3132189019
Short name T390
Test name
Test status
Simulation time 321301631 ps
CPU time 1.52 seconds
Started Oct 15 12:54:09 PM UTC 24
Finished Oct 15 12:54:12 PM UTC 24
Peak memory 211456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132189019 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_ctrl_config_regwen.3132189019
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3260928822
Short name T393
Test name
Test status
Simulation time 809039597 ps
CPU time 2.94 seconds
Started Oct 15 12:54:08 PM UTC 24
Finished Oct 15 12:54:12 PM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260928822 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3260928822
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3707117726
Short name T394
Test name
Test status
Simulation time 876747056 ps
CPU time 2.39 seconds
Started Oct 15 12:54:09 PM UTC 24
Finished Oct 15 12:54:13 PM UTC 24
Peak memory 212480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707117726 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3707117726
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2261022252
Short name T385
Test name
Test status
Simulation time 54375259 ps
CPU time 1.08 seconds
Started Oct 15 12:54:09 PM UTC 24
Finished Oct 15 12:54:11 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261022252 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2261022252
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.2808087168
Short name T379
Test name
Test status
Simulation time 40444960 ps
CPU time 0.99 seconds
Started Oct 15 12:54:07 PM UTC 24
Finished Oct 15 12:54:10 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808087168 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.2808087168
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all.1249438496
Short name T401
Test name
Test status
Simulation time 529975014 ps
CPU time 3.3 seconds
Started Oct 15 12:54:10 PM UTC 24
Finished Oct 15 12:54:15 PM UTC 24
Peak memory 212276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249438496 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.1249438496
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all_with_rand_reset.1153469854
Short name T90
Test name
Test status
Simulation time 10180361979 ps
CPU time 10.12 seconds
Started Oct 15 12:54:10 PM UTC 24
Finished Oct 15 12:54:22 PM UTC 24
Peak memory 212620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1153469854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmg
r_stress_all_with_rand_reset.1153469854
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.1996886494
Short name T380
Test name
Test status
Simulation time 278760794 ps
CPU time 1.37 seconds
Started Oct 15 12:54:07 PM UTC 24
Finished Oct 15 12:54:10 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996886494 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.1996886494
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup_reset.1832705602
Short name T387
Test name
Test status
Simulation time 299294162 ps
CPU time 2.4 seconds
Started Oct 15 12:54:08 PM UTC 24
Finished Oct 15 12:54:11 PM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832705602 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.1832705602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/16.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_aborted_low_power.389050773
Short name T117
Test name
Test status
Simulation time 160181719 ps
CPU time 1.25 seconds
Started Oct 15 12:54:12 PM UTC 24
Finished Oct 15 12:54:14 PM UTC 24
Peak memory 211100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389050773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.389050773
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.315382050
Short name T402
Test name
Test status
Simulation time 31969649 ps
CPU time 0.88 seconds
Started Oct 15 12:54:14 PM UTC 24
Finished Oct 15 12:54:15 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315382050 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_malfunc.315382050
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_escalation_timeout.2532501044
Short name T409
Test name
Test status
Simulation time 408088400 ps
CPU time 1.31 seconds
Started Oct 15 12:54:14 PM UTC 24
Finished Oct 15 12:54:16 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532501044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.2532501044
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_glitch.57828701
Short name T404
Test name
Test status
Simulation time 78243041 ps
CPU time 0.87 seconds
Started Oct 15 12:54:14 PM UTC 24
Finished Oct 15 12:54:16 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57828701 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.57828701
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_global_esc.2388221424
Short name T405
Test name
Test status
Simulation time 33143440 ps
CPU time 1 seconds
Started Oct 15 12:54:14 PM UTC 24
Finished Oct 15 12:54:16 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388221424 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.2388221424
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_invalid.2277731976
Short name T406
Test name
Test status
Simulation time 80189872 ps
CPU time 1.03 seconds
Started Oct 15 12:54:14 PM UTC 24
Finished Oct 15 12:54:16 PM UTC 24
Peak memory 212968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277731976 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_invalid.2277731976
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_wakeup_race.1266563742
Short name T400
Test name
Test status
Simulation time 206653828 ps
CPU time 1.45 seconds
Started Oct 15 12:54:12 PM UTC 24
Finished Oct 15 12:54:14 PM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266563742 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_wakeup_race.1266563742
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset.4036561799
Short name T397
Test name
Test status
Simulation time 84647285 ps
CPU time 1.1 seconds
Started Oct 15 12:54:12 PM UTC 24
Finished Oct 15 12:54:14 PM UTC 24
Peak memory 211140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036561799 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.4036561799
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset_invalid.425477639
Short name T407
Test name
Test status
Simulation time 106258991 ps
CPU time 1.14 seconds
Started Oct 15 12:54:14 PM UTC 24
Finished Oct 15 12:54:16 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425477639 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.425477639
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.2037441287
Short name T408
Test name
Test status
Simulation time 135297373 ps
CPU time 1.32 seconds
Started Oct 15 12:54:14 PM UTC 24
Finished Oct 15 12:54:16 PM UTC 24
Peak memory 209860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037441287 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_ctrl_config_regwen.2037441287
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1443629941
Short name T403
Test name
Test status
Simulation time 1019535523 ps
CPU time 2.5 seconds
Started Oct 15 12:54:12 PM UTC 24
Finished Oct 15 12:54:16 PM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443629941 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1443629941
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4192092283
Short name T410
Test name
Test status
Simulation time 938962668 ps
CPU time 3.92 seconds
Started Oct 15 12:54:12 PM UTC 24
Finished Oct 15 12:54:17 PM UTC 24
Peak memory 212688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192092283 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.4192092283
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.456246737
Short name T398
Test name
Test status
Simulation time 102464389 ps
CPU time 1.01 seconds
Started Oct 15 12:54:12 PM UTC 24
Finished Oct 15 12:54:14 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456246737 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_mubi.456246737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.4222815700
Short name T395
Test name
Test status
Simulation time 43345845 ps
CPU time 1.02 seconds
Started Oct 15 12:54:11 PM UTC 24
Finished Oct 15 12:54:13 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222815700 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.4222815700
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all.617892834
Short name T412
Test name
Test status
Simulation time 226267508 ps
CPU time 1.11 seconds
Started Oct 15 12:54:15 PM UTC 24
Finished Oct 15 12:54:17 PM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617892834 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.617892834
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all_with_rand_reset.990114214
Short name T462
Test name
Test status
Simulation time 7881456454 ps
CPU time 11.34 seconds
Started Oct 15 12:54:15 PM UTC 24
Finished Oct 15 12:54:28 PM UTC 24
Peak memory 212620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=990114214 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr
_stress_all_with_rand_reset.990114214
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup.2269476834
Short name T396
Test name
Test status
Simulation time 139854863 ps
CPU time 0.99 seconds
Started Oct 15 12:54:12 PM UTC 24
Finished Oct 15 12:54:14 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269476834 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.2269476834
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup_reset.954512769
Short name T399
Test name
Test status
Simulation time 89271305 ps
CPU time 1.29 seconds
Started Oct 15 12:54:12 PM UTC 24
Finished Oct 15 12:54:14 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954512769 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.954512769
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/17.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_aborted_low_power.4054306316
Short name T419
Test name
Test status
Simulation time 42222219 ps
CPU time 1.09 seconds
Started Oct 15 12:54:17 PM UTC 24
Finished Oct 15 12:54:19 PM UTC 24
Peak memory 211420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054306316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.4054306316
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_disable_rom_integrity_check.1163478814
Short name T424
Test name
Test status
Simulation time 67681751 ps
CPU time 1.14 seconds
Started Oct 15 12:54:18 PM UTC 24
Finished Oct 15 12:54:20 PM UTC 24
Peak memory 209060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163478814 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disable_rom_integrity_check.1163478814
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.3912811627
Short name T417
Test name
Test status
Simulation time 45950124 ps
CPU time 0.85 seconds
Started Oct 15 12:54:17 PM UTC 24
Finished Oct 15 12:54:19 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912811627 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_malfunc.3912811627
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_escalation_timeout.2822220358
Short name T422
Test name
Test status
Simulation time 401475630 ps
CPU time 1.09 seconds
Started Oct 15 12:54:17 PM UTC 24
Finished Oct 15 12:54:20 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822220358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.2822220358
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_glitch.2162061815
Short name T420
Test name
Test status
Simulation time 49874453 ps
CPU time 0.89 seconds
Started Oct 15 12:54:17 PM UTC 24
Finished Oct 15 12:54:19 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162061815 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.2162061815
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_global_esc.1630701816
Short name T418
Test name
Test status
Simulation time 31413226 ps
CPU time 0.74 seconds
Started Oct 15 12:54:17 PM UTC 24
Finished Oct 15 12:54:19 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630701816 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.1630701816
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_invalid.2724570212
Short name T426
Test name
Test status
Simulation time 85085282 ps
CPU time 1.08 seconds
Started Oct 15 12:54:19 PM UTC 24
Finished Oct 15 12:54:21 PM UTC 24
Peak memory 212968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724570212 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invalid.2724570212
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_wakeup_race.1980759698
Short name T415
Test name
Test status
Simulation time 184834558 ps
CPU time 1.69 seconds
Started Oct 15 12:54:15 PM UTC 24
Finished Oct 15 12:54:18 PM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980759698 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_wakeup_race.1980759698
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset.3136576381
Short name T413
Test name
Test status
Simulation time 189036416 ps
CPU time 1.14 seconds
Started Oct 15 12:54:15 PM UTC 24
Finished Oct 15 12:54:18 PM UTC 24
Peak memory 210648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136576381 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.3136576381
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset_invalid.737704503
Short name T425
Test name
Test status
Simulation time 169022033 ps
CPU time 1.12 seconds
Started Oct 15 12:54:18 PM UTC 24
Finished Oct 15 12:54:20 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737704503 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.737704503
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.1169639806
Short name T423
Test name
Test status
Simulation time 138440838 ps
CPU time 1.27 seconds
Started Oct 15 12:54:17 PM UTC 24
Finished Oct 15 12:54:20 PM UTC 24
Peak memory 210224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169639806 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_ctrl_config_regwen.1169639806
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1883688382
Short name T431
Test name
Test status
Simulation time 859004223 ps
CPU time 3.3 seconds
Started Oct 15 12:54:17 PM UTC 24
Finished Oct 15 12:54:22 PM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883688382 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1883688382
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4108924832
Short name T432
Test name
Test status
Simulation time 888651295 ps
CPU time 3.32 seconds
Started Oct 15 12:54:17 PM UTC 24
Finished Oct 15 12:54:22 PM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108924832 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.4108924832
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1244112138
Short name T421
Test name
Test status
Simulation time 167696241 ps
CPU time 1.34 seconds
Started Oct 15 12:54:17 PM UTC 24
Finished Oct 15 12:54:20 PM UTC 24
Peak memory 210628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244112138 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1244112138
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_smoke.1572383921
Short name T411
Test name
Test status
Simulation time 62361902 ps
CPU time 0.88 seconds
Started Oct 15 12:54:15 PM UTC 24
Finished Oct 15 12:54:17 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572383921 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.1572383921
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all.2748572009
Short name T119
Test name
Test status
Simulation time 1184982073 ps
CPU time 4.14 seconds
Started Oct 15 12:54:19 PM UTC 24
Finished Oct 15 12:54:24 PM UTC 24
Peak memory 212536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748572009 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.2748572009
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all_with_rand_reset.2058771533
Short name T50
Test name
Test status
Simulation time 5183134786 ps
CPU time 20.6 seconds
Started Oct 15 12:54:19 PM UTC 24
Finished Oct 15 12:54:41 PM UTC 24
Peak memory 212748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2058771533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmg
r_stress_all_with_rand_reset.2058771533
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup.1514049934
Short name T414
Test name
Test status
Simulation time 509897276 ps
CPU time 1.14 seconds
Started Oct 15 12:54:15 PM UTC 24
Finished Oct 15 12:54:18 PM UTC 24
Peak memory 210080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514049934 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.1514049934
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup_reset.1780744842
Short name T416
Test name
Test status
Simulation time 220989346 ps
CPU time 1.61 seconds
Started Oct 15 12:54:15 PM UTC 24
Finished Oct 15 12:54:18 PM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780744842 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.1780744842
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/18.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_aborted_low_power.1462493849
Short name T429
Test name
Test status
Simulation time 50128614 ps
CPU time 1.08 seconds
Started Oct 15 12:54:19 PM UTC 24
Finished Oct 15 12:54:21 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462493849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.1462493849
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_disable_rom_integrity_check.84979334
Short name T440
Test name
Test status
Simulation time 55295461 ps
CPU time 0.93 seconds
Started Oct 15 12:54:21 PM UTC 24
Finished Oct 15 12:54:23 PM UTC 24
Peak memory 209180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84979334 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disable_rom_integrity_check.84979334
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.1700360866
Short name T436
Test name
Test status
Simulation time 55809072 ps
CPU time 0.87 seconds
Started Oct 15 12:54:21 PM UTC 24
Finished Oct 15 12:54:22 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700360866 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_malfunc.1700360866
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_escalation_timeout.646020496
Short name T439
Test name
Test status
Simulation time 420469995 ps
CPU time 0.94 seconds
Started Oct 15 12:54:21 PM UTC 24
Finished Oct 15 12:54:23 PM UTC 24
Peak memory 209184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646020496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.646020496
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_glitch.1533663847
Short name T438
Test name
Test status
Simulation time 60802110 ps
CPU time 0.98 seconds
Started Oct 15 12:54:21 PM UTC 24
Finished Oct 15 12:54:23 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533663847 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.1533663847
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_global_esc.975085615
Short name T437
Test name
Test status
Simulation time 87101329 ps
CPU time 0.96 seconds
Started Oct 15 12:54:21 PM UTC 24
Finished Oct 15 12:54:23 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975085615 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.975085615
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_invalid.3855997253
Short name T443
Test name
Test status
Simulation time 66107157 ps
CPU time 1.02 seconds
Started Oct 15 12:54:22 PM UTC 24
Finished Oct 15 12:54:24 PM UTC 24
Peak memory 212968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855997253 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_invalid.3855997253
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_wakeup_race.769050007
Short name T430
Test name
Test status
Simulation time 235226918 ps
CPU time 1.35 seconds
Started Oct 15 12:54:19 PM UTC 24
Finished Oct 15 12:54:21 PM UTC 24
Peak memory 210084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769050007 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_wakeup_race.769050007
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset.2969461181
Short name T428
Test name
Test status
Simulation time 35569267 ps
CPU time 1.12 seconds
Started Oct 15 12:54:19 PM UTC 24
Finished Oct 15 12:54:21 PM UTC 24
Peak memory 210244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969461181 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.2969461181
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset_invalid.2834008272
Short name T444
Test name
Test status
Simulation time 123214299 ps
CPU time 1.22 seconds
Started Oct 15 12:54:22 PM UTC 24
Finished Oct 15 12:54:24 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834008272 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.2834008272
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.3293729692
Short name T441
Test name
Test status
Simulation time 212592976 ps
CPU time 1.16 seconds
Started Oct 15 12:54:21 PM UTC 24
Finished Oct 15 12:54:23 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293729692 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_ctrl_config_regwen.3293729692
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3148425655
Short name T447
Test name
Test status
Simulation time 782127912 ps
CPU time 3.76 seconds
Started Oct 15 12:54:20 PM UTC 24
Finished Oct 15 12:54:25 PM UTC 24
Peak memory 212664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148425655 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3148425655
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1510240871
Short name T445
Test name
Test status
Simulation time 826837003 ps
CPU time 3.4 seconds
Started Oct 15 12:54:20 PM UTC 24
Finished Oct 15 12:54:25 PM UTC 24
Peak memory 212688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510240871 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1510240871
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.1004727460
Short name T435
Test name
Test status
Simulation time 64287222 ps
CPU time 0.95 seconds
Started Oct 15 12:54:20 PM UTC 24
Finished Oct 15 12:54:22 PM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004727460 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_mubi.1004727460
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_smoke.4127375165
Short name T427
Test name
Test status
Simulation time 38454316 ps
CPU time 0.95 seconds
Started Oct 15 12:54:19 PM UTC 24
Finished Oct 15 12:54:21 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127375165 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.4127375165
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all.3780559887
Short name T446
Test name
Test status
Simulation time 546298144 ps
CPU time 2.15 seconds
Started Oct 15 12:54:22 PM UTC 24
Finished Oct 15 12:54:25 PM UTC 24
Peak memory 211928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780559887 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.3780559887
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup.196210577
Short name T434
Test name
Test status
Simulation time 156506259 ps
CPU time 1.59 seconds
Started Oct 15 12:54:19 PM UTC 24
Finished Oct 15 12:54:22 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196210577 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.196210577
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup_reset.2674854136
Short name T433
Test name
Test status
Simulation time 352597504 ps
CPU time 1.54 seconds
Started Oct 15 12:54:19 PM UTC 24
Finished Oct 15 12:54:22 PM UTC 24
Peak memory 211144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674854136 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.2674854136
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/19.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.393590903
Short name T105
Test name
Test status
Simulation time 23293017 ps
CPU time 1.13 seconds
Started Oct 15 12:52:57 PM UTC 24
Finished Oct 15 12:53:00 PM UTC 24
Peak memory 210916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393590903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.393590903
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.538998641
Short name T157
Test name
Test status
Simulation time 75631927 ps
CPU time 1.05 seconds
Started Oct 15 12:53:02 PM UTC 24
Finished Oct 15 12:53:04 PM UTC 24
Peak memory 209060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538998641 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disable_rom_integrity_check.538998641
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.706192205
Short name T109
Test name
Test status
Simulation time 31329818 ps
CPU time 0.97 seconds
Started Oct 15 12:53:00 PM UTC 24
Finished Oct 15 12:53:02 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706192205 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_malfunc.706192205
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.2616863360
Short name T111
Test name
Test status
Simulation time 203323695 ps
CPU time 1.49 seconds
Started Oct 15 12:53:01 PM UTC 24
Finished Oct 15 12:53:04 PM UTC 24
Peak memory 209240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616863360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.2616863360
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.1574105765
Short name T19
Test name
Test status
Simulation time 31314412 ps
CPU time 0.88 seconds
Started Oct 15 12:53:01 PM UTC 24
Finished Oct 15 12:53:03 PM UTC 24
Peak memory 208932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574105765 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.1574105765
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.757071598
Short name T108
Test name
Test status
Simulation time 23069540 ps
CPU time 0.85 seconds
Started Oct 15 12:53:00 PM UTC 24
Finished Oct 15 12:53:02 PM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757071598 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.757071598
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.117966656
Short name T43
Test name
Test status
Simulation time 50888880 ps
CPU time 1.08 seconds
Started Oct 15 12:53:02 PM UTC 24
Finished Oct 15 12:53:05 PM UTC 24
Peak memory 210836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117966656 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invalid.117966656
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.697932733
Short name T75
Test name
Test status
Simulation time 195679220 ps
CPU time 1.24 seconds
Started Oct 15 12:52:56 PM UTC 24
Finished Oct 15 12:52:58 PM UTC 24
Peak memory 209180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697932733 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wakeup_race.697932733
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.2775783423
Short name T184
Test name
Test status
Simulation time 138930482 ps
CPU time 1.1 seconds
Started Oct 15 12:52:56 PM UTC 24
Finished Oct 15 12:52:58 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775783423 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.2775783423
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.2118500754
Short name T41
Test name
Test status
Simulation time 159023020 ps
CPU time 1.19 seconds
Started Oct 15 12:53:02 PM UTC 24
Finished Oct 15 12:53:05 PM UTC 24
Peak memory 211020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118500754 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.2118500754
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.19748559
Short name T22
Test name
Test status
Simulation time 389443741 ps
CPU time 2.13 seconds
Started Oct 15 12:53:05 PM UTC 24
Finished Oct 15 12:53:08 PM UTC 24
Peak memory 240096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19748559 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.19748559
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.1087561377
Short name T60
Test name
Test status
Simulation time 486208794 ps
CPU time 1.31 seconds
Started Oct 15 12:53:00 PM UTC 24
Finished Oct 15 12:53:02 PM UTC 24
Peak memory 210416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087561377 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_ctrl_config_regwen.1087561377
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1487001104
Short name T110
Test name
Test status
Simulation time 832401221 ps
CPU time 3 seconds
Started Oct 15 12:52:59 PM UTC 24
Finished Oct 15 12:53:03 PM UTC 24
Peak memory 212432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487001104 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.1487001104
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3933184275
Short name T44
Test name
Test status
Simulation time 1389466515 ps
CPU time 2.88 seconds
Started Oct 15 12:52:59 PM UTC 24
Finished Oct 15 12:53:02 PM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933184275 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.3933184275
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.3196040657
Short name T107
Test name
Test status
Simulation time 382751494 ps
CPU time 1.26 seconds
Started Oct 15 12:52:59 PM UTC 24
Finished Oct 15 12:53:01 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196040657 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_mubi.3196040657
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.3681577097
Short name T183
Test name
Test status
Simulation time 34396382 ps
CPU time 1 seconds
Started Oct 15 12:52:56 PM UTC 24
Finished Oct 15 12:52:58 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681577097 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.3681577097
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.2689909079
Short name T113
Test name
Test status
Simulation time 854604916 ps
CPU time 3.97 seconds
Started Oct 15 12:53:05 PM UTC 24
Finished Oct 15 12:53:10 PM UTC 24
Peak memory 212728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689909079 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.2689909079
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.3706990628
Short name T25
Test name
Test status
Simulation time 919964773 ps
CPU time 6.49 seconds
Started Oct 15 12:53:05 PM UTC 24
Finished Oct 15 12:53:12 PM UTC 24
Peak memory 212668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3706990628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr
_stress_all_with_rand_reset.3706990628
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.496286093
Short name T185
Test name
Test status
Simulation time 261524498 ps
CPU time 2.01 seconds
Started Oct 15 12:52:56 PM UTC 24
Finished Oct 15 12:52:59 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496286093 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.496286093
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.1618582034
Short name T106
Test name
Test status
Simulation time 199833422 ps
CPU time 1.38 seconds
Started Oct 15 12:52:57 PM UTC 24
Finished Oct 15 12:53:00 PM UTC 24
Peak memory 211324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618582034 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.1618582034
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/2.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_aborted_low_power.596351208
Short name T448
Test name
Test status
Simulation time 32448715 ps
CPU time 1.09 seconds
Started Oct 15 12:54:24 PM UTC 24
Finished Oct 15 12:54:26 PM UTC 24
Peak memory 209624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596351208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.596351208
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.2188239163
Short name T457
Test name
Test status
Simulation time 74168944 ps
CPU time 0.96 seconds
Started Oct 15 12:54:24 PM UTC 24
Finished Oct 15 12:54:26 PM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188239163 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disable_rom_integrity_check.2188239163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.3153148910
Short name T449
Test name
Test status
Simulation time 44687342 ps
CPU time 0.85 seconds
Started Oct 15 12:54:24 PM UTC 24
Finished Oct 15 12:54:26 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153148910 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst_malfunc.3153148910
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_escalation_timeout.1932611965
Short name T456
Test name
Test status
Simulation time 204836262 ps
CPU time 0.98 seconds
Started Oct 15 12:54:24 PM UTC 24
Finished Oct 15 12:54:26 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932611965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.1932611965
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_glitch.1902132723
Short name T452
Test name
Test status
Simulation time 29260080 ps
CPU time 0.83 seconds
Started Oct 15 12:54:24 PM UTC 24
Finished Oct 15 12:54:26 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902132723 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.1902132723
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_global_esc.3422433217
Short name T455
Test name
Test status
Simulation time 50054381 ps
CPU time 0.99 seconds
Started Oct 15 12:54:24 PM UTC 24
Finished Oct 15 12:54:26 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422433217 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.3422433217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_invalid.220730189
Short name T461
Test name
Test status
Simulation time 45670681 ps
CPU time 0.72 seconds
Started Oct 15 12:54:26 PM UTC 24
Finished Oct 15 12:54:28 PM UTC 24
Peak memory 210836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220730189 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_invalid.220730189
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_wakeup_race.1010149518
Short name T450
Test name
Test status
Simulation time 136049831 ps
CPU time 1.39 seconds
Started Oct 15 12:54:24 PM UTC 24
Finished Oct 15 12:54:26 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010149518 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_wakeup_race.1010149518
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset.3903173878
Short name T382
Test name
Test status
Simulation time 137776766 ps
CPU time 1.01 seconds
Started Oct 15 12:54:24 PM UTC 24
Finished Oct 15 12:54:26 PM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903173878 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.3903173878
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset_invalid.3810117410
Short name T466
Test name
Test status
Simulation time 103665615 ps
CPU time 1.32 seconds
Started Oct 15 12:54:26 PM UTC 24
Finished Oct 15 12:54:28 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810117410 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3810117410
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.1202014563
Short name T454
Test name
Test status
Simulation time 104910861 ps
CPU time 1.05 seconds
Started Oct 15 12:54:24 PM UTC 24
Finished Oct 15 12:54:26 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202014563 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_ctrl_config_regwen.1202014563
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1003997513
Short name T460
Test name
Test status
Simulation time 872263116 ps
CPU time 2.4 seconds
Started Oct 15 12:54:24 PM UTC 24
Finished Oct 15 12:54:27 PM UTC 24
Peak memory 212736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003997513 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1003997513
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.471243436
Short name T464
Test name
Test status
Simulation time 789794951 ps
CPU time 2.86 seconds
Started Oct 15 12:54:24 PM UTC 24
Finished Oct 15 12:54:28 PM UTC 24
Peak memory 212688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471243436 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.471243436
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.934972662
Short name T453
Test name
Test status
Simulation time 54794483 ps
CPU time 1.19 seconds
Started Oct 15 12:54:24 PM UTC 24
Finished Oct 15 12:54:26 PM UTC 24
Peak memory 210628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934972662 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig_mubi.934972662
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_smoke.1655898555
Short name T442
Test name
Test status
Simulation time 37909460 ps
CPU time 0.88 seconds
Started Oct 15 12:54:22 PM UTC 24
Finished Oct 15 12:54:24 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655898555 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.1655898555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all.3497022087
Short name T481
Test name
Test status
Simulation time 4692717899 ps
CPU time 3.89 seconds
Started Oct 15 12:54:26 PM UTC 24
Finished Oct 15 12:54:31 PM UTC 24
Peak memory 212664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497022087 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.3497022087
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all_with_rand_reset.2783968686
Short name T147
Test name
Test status
Simulation time 5164195799 ps
CPU time 7.44 seconds
Started Oct 15 12:54:26 PM UTC 24
Finished Oct 15 12:54:34 PM UTC 24
Peak memory 212728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2783968686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmg
r_stress_all_with_rand_reset.2783968686
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup.2923776905
Short name T451
Test name
Test status
Simulation time 170469713 ps
CPU time 1.29 seconds
Started Oct 15 12:54:24 PM UTC 24
Finished Oct 15 12:54:26 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923776905 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.2923776905
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup_reset.2189563850
Short name T458
Test name
Test status
Simulation time 401103879 ps
CPU time 1.48 seconds
Started Oct 15 12:54:24 PM UTC 24
Finished Oct 15 12:54:26 PM UTC 24
Peak memory 211324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189563850 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.2189563850
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/20.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_aborted_low_power.997288577
Short name T468
Test name
Test status
Simulation time 19494240 ps
CPU time 0.75 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:30 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997288577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.997288577
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.2170172217
Short name T475
Test name
Test status
Simulation time 63392950 ps
CPU time 0.81 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:30 PM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170172217 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disable_rom_integrity_check.2170172217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.798668255
Short name T471
Test name
Test status
Simulation time 40166187 ps
CPU time 0.85 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:30 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798668255 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_malfunc.798668255
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_escalation_timeout.126585325
Short name T477
Test name
Test status
Simulation time 199454649 ps
CPU time 1.06 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:30 PM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126585325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.126585325
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_glitch.1818917213
Short name T473
Test name
Test status
Simulation time 50607471 ps
CPU time 0.69 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:30 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818917213 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.1818917213
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_global_esc.266851673
Short name T470
Test name
Test status
Simulation time 53068801 ps
CPU time 0.81 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:30 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266851673 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.266851673
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_invalid.1500344833
Short name T478
Test name
Test status
Simulation time 70040903 ps
CPU time 0.82 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:30 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500344833 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invalid.1500344833
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_wakeup_race.721920047
Short name T469
Test name
Test status
Simulation time 310223462 ps
CPU time 0.94 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:30 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721920047 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_wakeup_race.721920047
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset.3788315832
Short name T465
Test name
Test status
Simulation time 26523660 ps
CPU time 0.92 seconds
Started Oct 15 12:54:26 PM UTC 24
Finished Oct 15 12:54:28 PM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788315832 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.3788315832
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset_invalid.412591185
Short name T480
Test name
Test status
Simulation time 110918950 ps
CPU time 1.21 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:31 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412591185 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.412591185
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.1118930489
Short name T479
Test name
Test status
Simulation time 90720641 ps
CPU time 1.16 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:30 PM UTC 24
Peak memory 210204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118930489 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_ctrl_config_regwen.1118930489
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3423282908
Short name T484
Test name
Test status
Simulation time 820454533 ps
CPU time 2.98 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:32 PM UTC 24
Peak memory 212496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423282908 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3423282908
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3668053593
Short name T483
Test name
Test status
Simulation time 1202729103 ps
CPU time 2.56 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:31 PM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668053593 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3668053593
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.2776869634
Short name T476
Test name
Test status
Simulation time 92075796 ps
CPU time 1.22 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:30 PM UTC 24
Peak memory 210424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776869634 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig_mubi.2776869634
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_smoke.3471392984
Short name T463
Test name
Test status
Simulation time 30708736 ps
CPU time 0.81 seconds
Started Oct 15 12:54:26 PM UTC 24
Finished Oct 15 12:54:28 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471392984 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.3471392984
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all.1405120814
Short name T505
Test name
Test status
Simulation time 1012660602 ps
CPU time 4.54 seconds
Started Oct 15 12:54:29 PM UTC 24
Finished Oct 15 12:54:35 PM UTC 24
Peak memory 212404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405120814 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.1405120814
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all_with_rand_reset.2114734239
Short name T520
Test name
Test status
Simulation time 10565583284 ps
CPU time 6.48 seconds
Started Oct 15 12:54:29 PM UTC 24
Finished Oct 15 12:54:37 PM UTC 24
Peak memory 213004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2114734239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmg
r_stress_all_with_rand_reset.2114734239
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup.1221888471
Short name T472
Test name
Test status
Simulation time 131233058 ps
CPU time 1.22 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:30 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221888471 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.1221888471
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup_reset.817887513
Short name T474
Test name
Test status
Simulation time 290243328 ps
CPU time 1.28 seconds
Started Oct 15 12:54:28 PM UTC 24
Finished Oct 15 12:54:30 PM UTC 24
Peak memory 211384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817887513 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.817887513
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/21.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_aborted_low_power.4256708472
Short name T491
Test name
Test status
Simulation time 21362132 ps
CPU time 0.92 seconds
Started Oct 15 12:54:31 PM UTC 24
Finished Oct 15 12:54:33 PM UTC 24
Peak memory 211192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256708472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.4256708472
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_disable_rom_integrity_check.3962600784
Short name T499
Test name
Test status
Simulation time 67011857 ps
CPU time 1.12 seconds
Started Oct 15 12:54:31 PM UTC 24
Finished Oct 15 12:54:33 PM UTC 24
Peak memory 209384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962600784 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_disable_rom_integrity_check.3962600784
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.1953345740
Short name T490
Test name
Test status
Simulation time 39644836 ps
CPU time 0.86 seconds
Started Oct 15 12:54:31 PM UTC 24
Finished Oct 15 12:54:33 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953345740 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst_malfunc.1953345740
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_escalation_timeout.178689290
Short name T495
Test name
Test status
Simulation time 404049374 ps
CPU time 1.08 seconds
Started Oct 15 12:54:31 PM UTC 24
Finished Oct 15 12:54:33 PM UTC 24
Peak memory 209184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178689290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.178689290
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_glitch.2653172493
Short name T494
Test name
Test status
Simulation time 121116626 ps
CPU time 0.86 seconds
Started Oct 15 12:54:31 PM UTC 24
Finished Oct 15 12:54:33 PM UTC 24
Peak memory 208860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653172493 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2653172493
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_global_esc.3055648822
Short name T493
Test name
Test status
Simulation time 22339907 ps
CPU time 0.84 seconds
Started Oct 15 12:54:31 PM UTC 24
Finished Oct 15 12:54:33 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055648822 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.3055648822
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_invalid.707127855
Short name T497
Test name
Test status
Simulation time 40710563 ps
CPU time 0.96 seconds
Started Oct 15 12:54:31 PM UTC 24
Finished Oct 15 12:54:33 PM UTC 24
Peak memory 210836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707127855 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invalid.707127855
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_wakeup_race.86789088
Short name T487
Test name
Test status
Simulation time 193299832 ps
CPU time 1.35 seconds
Started Oct 15 12:54:30 PM UTC 24
Finished Oct 15 12:54:32 PM UTC 24
Peak memory 210204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86789088 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_wakeup_race.86789088
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset.1219729141
Short name T486
Test name
Test status
Simulation time 97410071 ps
CPU time 1.26 seconds
Started Oct 15 12:54:30 PM UTC 24
Finished Oct 15 12:54:32 PM UTC 24
Peak memory 211140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219729141 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.1219729141
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset_invalid.1786485831
Short name T496
Test name
Test status
Simulation time 171232926 ps
CPU time 0.92 seconds
Started Oct 15 12:54:31 PM UTC 24
Finished Oct 15 12:54:33 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786485831 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.1786485831
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.3008754935
Short name T498
Test name
Test status
Simulation time 166647373 ps
CPU time 1.21 seconds
Started Oct 15 12:54:31 PM UTC 24
Finished Oct 15 12:54:33 PM UTC 24
Peak memory 210412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008754935 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_ctrl_config_regwen.3008754935
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2849298122
Short name T502
Test name
Test status
Simulation time 1126138015 ps
CPU time 2.86 seconds
Started Oct 15 12:54:31 PM UTC 24
Finished Oct 15 12:54:35 PM UTC 24
Peak memory 212416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849298122 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2849298122
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3988474914
Short name T508
Test name
Test status
Simulation time 802458387 ps
CPU time 3.51 seconds
Started Oct 15 12:54:31 PM UTC 24
Finished Oct 15 12:54:36 PM UTC 24
Peak memory 212672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988474914 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3988474914
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3779105918
Short name T492
Test name
Test status
Simulation time 107351406 ps
CPU time 1.02 seconds
Started Oct 15 12:54:31 PM UTC 24
Finished Oct 15 12:54:33 PM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779105918 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3779105918
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_smoke.1226115485
Short name T482
Test name
Test status
Simulation time 33105026 ps
CPU time 0.81 seconds
Started Oct 15 12:54:30 PM UTC 24
Finished Oct 15 12:54:31 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226115485 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.1226115485
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all.922467526
Short name T511
Test name
Test status
Simulation time 548797693 ps
CPU time 2.47 seconds
Started Oct 15 12:54:33 PM UTC 24
Finished Oct 15 12:54:36 PM UTC 24
Peak memory 212408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922467526 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.922467526
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all_with_rand_reset.3949989710
Short name T79
Test name
Test status
Simulation time 10525663823 ps
CPU time 13.89 seconds
Started Oct 15 12:54:31 PM UTC 24
Finished Oct 15 12:54:47 PM UTC 24
Peak memory 212612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3949989710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmg
r_stress_all_with_rand_reset.3949989710
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup.45598133
Short name T485
Test name
Test status
Simulation time 179349271 ps
CPU time 1.1 seconds
Started Oct 15 12:54:30 PM UTC 24
Finished Oct 15 12:54:32 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45598133 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.45598133
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup_reset.3633028756
Short name T488
Test name
Test status
Simulation time 275369694 ps
CPU time 1.39 seconds
Started Oct 15 12:54:30 PM UTC 24
Finished Oct 15 12:54:32 PM UTC 24
Peak memory 211384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633028756 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.3633028756
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/22.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_aborted_low_power.1255779226
Short name T506
Test name
Test status
Simulation time 69031432 ps
CPU time 1.06 seconds
Started Oct 15 12:54:33 PM UTC 24
Finished Oct 15 12:54:35 PM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255779226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.1255779226
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_disable_rom_integrity_check.3390771388
Short name T179
Test name
Test status
Simulation time 64734342 ps
CPU time 0.86 seconds
Started Oct 15 12:54:34 PM UTC 24
Finished Oct 15 12:54:37 PM UTC 24
Peak memory 209060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390771388 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_disable_rom_integrity_check.3390771388
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.1951150525
Short name T513
Test name
Test status
Simulation time 31316679 ps
CPU time 0.89 seconds
Started Oct 15 12:54:34 PM UTC 24
Finished Oct 15 12:54:36 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951150525 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_malfunc.1951150525
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_escalation_timeout.3130643277
Short name T489
Test name
Test status
Simulation time 202563521 ps
CPU time 1.25 seconds
Started Oct 15 12:54:34 PM UTC 24
Finished Oct 15 12:54:37 PM UTC 24
Peak memory 209096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130643277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.3130643277
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_glitch.964582210
Short name T514
Test name
Test status
Simulation time 50326022 ps
CPU time 0.85 seconds
Started Oct 15 12:54:34 PM UTC 24
Finished Oct 15 12:54:36 PM UTC 24
Peak memory 208856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964582210 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.964582210
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_global_esc.2164951605
Short name T512
Test name
Test status
Simulation time 49220225 ps
CPU time 0.82 seconds
Started Oct 15 12:54:34 PM UTC 24
Finished Oct 15 12:54:36 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164951605 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.2164951605
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_invalid.3907515770
Short name T516
Test name
Test status
Simulation time 57229627 ps
CPU time 0.94 seconds
Started Oct 15 12:54:34 PM UTC 24
Finished Oct 15 12:54:37 PM UTC 24
Peak memory 212968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907515770 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_invalid.3907515770
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_wakeup_race.2048273624
Short name T504
Test name
Test status
Simulation time 138332183 ps
CPU time 1.13 seconds
Started Oct 15 12:54:33 PM UTC 24
Finished Oct 15 12:54:35 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048273624 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_wakeup_race.2048273624
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset.1592420688
Short name T503
Test name
Test status
Simulation time 27610470 ps
CPU time 1.06 seconds
Started Oct 15 12:54:33 PM UTC 24
Finished Oct 15 12:54:35 PM UTC 24
Peak memory 209796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592420688 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.1592420688
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset_invalid.1486461314
Short name T515
Test name
Test status
Simulation time 175861715 ps
CPU time 0.97 seconds
Started Oct 15 12:54:34 PM UTC 24
Finished Oct 15 12:54:37 PM UTC 24
Peak memory 221208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486461314 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.1486461314
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.1011487909
Short name T517
Test name
Test status
Simulation time 289421917 ps
CPU time 1.15 seconds
Started Oct 15 12:54:34 PM UTC 24
Finished Oct 15 12:54:37 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011487909 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_ctrl_config_regwen.1011487909
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4010973308
Short name T522
Test name
Test status
Simulation time 860769093 ps
CPU time 3.39 seconds
Started Oct 15 12:54:33 PM UTC 24
Finished Oct 15 12:54:38 PM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010973308 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4010973308
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3108860502
Short name T521
Test name
Test status
Simulation time 1064271451 ps
CPU time 2.06 seconds
Started Oct 15 12:54:34 PM UTC 24
Finished Oct 15 12:54:37 PM UTC 24
Peak memory 212688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108860502 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3108860502
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.4216853236
Short name T518
Test name
Test status
Simulation time 96986994 ps
CPU time 1.24 seconds
Started Oct 15 12:54:34 PM UTC 24
Finished Oct 15 12:54:37 PM UTC 24
Peak memory 210628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216853236 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_mubi.4216853236
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_smoke.739219405
Short name T500
Test name
Test status
Simulation time 49825260 ps
CPU time 0.92 seconds
Started Oct 15 12:54:33 PM UTC 24
Finished Oct 15 12:54:35 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739219405 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.739219405
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all.2980647439
Short name T534
Test name
Test status
Simulation time 3100165653 ps
CPU time 3.87 seconds
Started Oct 15 12:54:36 PM UTC 24
Finished Oct 15 12:54:41 PM UTC 24
Peak memory 212532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980647439 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.2980647439
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all_with_rand_reset.4167430014
Short name T546
Test name
Test status
Simulation time 6948934578 ps
CPU time 8.03 seconds
Started Oct 15 12:54:36 PM UTC 24
Finished Oct 15 12:54:45 PM UTC 24
Peak memory 212620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4167430014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmg
r_stress_all_with_rand_reset.4167430014
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup.947624609
Short name T507
Test name
Test status
Simulation time 181362889 ps
CPU time 1.19 seconds
Started Oct 15 12:54:33 PM UTC 24
Finished Oct 15 12:54:35 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947624609 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.947624609
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup_reset.1683505717
Short name T509
Test name
Test status
Simulation time 268863713 ps
CPU time 1.47 seconds
Started Oct 15 12:54:33 PM UTC 24
Finished Oct 15 12:54:36 PM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683505717 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.1683505717
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/23.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_aborted_low_power.723550503
Short name T523
Test name
Test status
Simulation time 38552071 ps
CPU time 0.9 seconds
Started Oct 15 12:54:36 PM UTC 24
Finished Oct 15 12:54:38 PM UTC 24
Peak memory 211424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723550503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.723550503
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_disable_rom_integrity_check.1340204156
Short name T527
Test name
Test status
Simulation time 60378586 ps
CPU time 0.96 seconds
Started Oct 15 12:54:38 PM UTC 24
Finished Oct 15 12:54:40 PM UTC 24
Peak memory 209384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340204156 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_disable_rom_integrity_check.1340204156
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.2938041580
Short name T525
Test name
Test status
Simulation time 28752897 ps
CPU time 0.97 seconds
Started Oct 15 12:54:37 PM UTC 24
Finished Oct 15 12:54:40 PM UTC 24
Peak memory 209048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938041580 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_malfunc.2938041580
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_escalation_timeout.1939601829
Short name T531
Test name
Test status
Simulation time 198472523 ps
CPU time 1.17 seconds
Started Oct 15 12:54:38 PM UTC 24
Finished Oct 15 12:54:40 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939601829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.1939601829
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_glitch.404739792
Short name T519
Test name
Test status
Simulation time 48412923 ps
CPU time 0.95 seconds
Started Oct 15 12:54:38 PM UTC 24
Finished Oct 15 12:54:40 PM UTC 24
Peak memory 208936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404739792 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.404739792
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_global_esc.2116024607
Short name T526
Test name
Test status
Simulation time 58514698 ps
CPU time 0.88 seconds
Started Oct 15 12:54:37 PM UTC 24
Finished Oct 15 12:54:40 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116024607 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.2116024607
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_invalid.1768833343
Short name T528
Test name
Test status
Simulation time 78461280 ps
CPU time 0.88 seconds
Started Oct 15 12:54:38 PM UTC 24
Finished Oct 15 12:54:40 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768833343 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_invalid.1768833343
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_wakeup_race.1556443335
Short name T524
Test name
Test status
Simulation time 286821957 ps
CPU time 1.37 seconds
Started Oct 15 12:54:36 PM UTC 24
Finished Oct 15 12:54:39 PM UTC 24
Peak memory 210412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556443335 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_wakeup_race.1556443335
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset.1659315780
Short name T459
Test name
Test status
Simulation time 270983232 ps
CPU time 1.15 seconds
Started Oct 15 12:54:36 PM UTC 24
Finished Oct 15 12:54:38 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659315780 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.1659315780
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset_invalid.3585220415
Short name T530
Test name
Test status
Simulation time 101063500 ps
CPU time 1.02 seconds
Started Oct 15 12:54:38 PM UTC 24
Finished Oct 15 12:54:40 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585220415 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.3585220415
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.372757488
Short name T532
Test name
Test status
Simulation time 110044037 ps
CPU time 1.27 seconds
Started Oct 15 12:54:37 PM UTC 24
Finished Oct 15 12:54:40 PM UTC 24
Peak memory 210412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372757488 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_ctrl_config_regwen.372757488
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4063439534
Short name T541
Test name
Test status
Simulation time 831644074 ps
CPU time 2.91 seconds
Started Oct 15 12:54:37 PM UTC 24
Finished Oct 15 12:54:41 PM UTC 24
Peak memory 212704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063439534 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4063439534
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2970011219
Short name T533
Test name
Test status
Simulation time 1505439357 ps
CPU time 2.21 seconds
Started Oct 15 12:54:37 PM UTC 24
Finished Oct 15 12:54:41 PM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970011219 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2970011219
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.3903072139
Short name T529
Test name
Test status
Simulation time 164101450 ps
CPU time 1.06 seconds
Started Oct 15 12:54:37 PM UTC 24
Finished Oct 15 12:54:40 PM UTC 24
Peak memory 210628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903072139 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_mubi.3903072139
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_smoke.2372790055
Short name T510
Test name
Test status
Simulation time 40158424 ps
CPU time 0.9 seconds
Started Oct 15 12:54:36 PM UTC 24
Finished Oct 15 12:54:38 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372790055 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.2372790055
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all.2322902948
Short name T536
Test name
Test status
Simulation time 717862550 ps
CPU time 2.15 seconds
Started Oct 15 12:54:38 PM UTC 24
Finished Oct 15 12:54:41 PM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322902948 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.2322902948
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all_with_rand_reset.1959304809
Short name T92
Test name
Test status
Simulation time 5045626293 ps
CPU time 6.42 seconds
Started Oct 15 12:54:38 PM UTC 24
Finished Oct 15 12:54:45 PM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1959304809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmg
r_stress_all_with_rand_reset.1959304809
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup.3463757223
Short name T501
Test name
Test status
Simulation time 144044347 ps
CPU time 1.1 seconds
Started Oct 15 12:54:36 PM UTC 24
Finished Oct 15 12:54:38 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463757223 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.3463757223
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup_reset.3360307506
Short name T467
Test name
Test status
Simulation time 99295960 ps
CPU time 0.87 seconds
Started Oct 15 12:54:36 PM UTC 24
Finished Oct 15 12:54:38 PM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360307506 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.3360307506
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/24.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_aborted_low_power.2929041434
Short name T540
Test name
Test status
Simulation time 68340271 ps
CPU time 1.05 seconds
Started Oct 15 12:54:39 PM UTC 24
Finished Oct 15 12:54:41 PM UTC 24
Peak memory 209980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929041434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.2929041434
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_disable_rom_integrity_check.475124210
Short name T550
Test name
Test status
Simulation time 66208004 ps
CPU time 0.99 seconds
Started Oct 15 12:54:41 PM UTC 24
Finished Oct 15 12:54:46 PM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475124210 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_disable_rom_integrity_check.475124210
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_escalation_timeout.4268704993
Short name T549
Test name
Test status
Simulation time 402917264 ps
CPU time 0.95 seconds
Started Oct 15 12:54:41 PM UTC 24
Finished Oct 15 12:54:46 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268704993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.4268704993
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_glitch.3910257786
Short name T547
Test name
Test status
Simulation time 59467386 ps
CPU time 0.73 seconds
Started Oct 15 12:54:41 PM UTC 24
Finished Oct 15 12:54:46 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910257786 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.3910257786
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_global_esc.551032527
Short name T548
Test name
Test status
Simulation time 113573467 ps
CPU time 0.8 seconds
Started Oct 15 12:54:41 PM UTC 24
Finished Oct 15 12:54:46 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551032527 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.551032527
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_invalid.3633378362
Short name T586
Test name
Test status
Simulation time 43075917 ps
CPU time 0.92 seconds
Started Oct 15 12:54:41 PM UTC 24
Finished Oct 15 12:55:03 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633378362 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invalid.3633378362
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_wakeup_race.3913784989
Short name T543
Test name
Test status
Simulation time 305325531 ps
CPU time 1.54 seconds
Started Oct 15 12:54:39 PM UTC 24
Finished Oct 15 12:54:42 PM UTC 24
Peak memory 210412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913784989 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wakeup_race.3913784989
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset.3683082119
Short name T537
Test name
Test status
Simulation time 135476834 ps
CPU time 1.08 seconds
Started Oct 15 12:54:39 PM UTC 24
Finished Oct 15 12:54:41 PM UTC 24
Peak memory 209436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683082119 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.3683082119
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset_invalid.222986022
Short name T585
Test name
Test status
Simulation time 101955817 ps
CPU time 1.03 seconds
Started Oct 15 12:54:41 PM UTC 24
Finished Oct 15 12:55:03 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222986022 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.222986022
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2054708101
Short name T544
Test name
Test status
Simulation time 839560423 ps
CPU time 2.97 seconds
Started Oct 15 12:54:39 PM UTC 24
Finished Oct 15 12:54:43 PM UTC 24
Peak memory 212436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054708101 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2054708101
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2989847964
Short name T545
Test name
Test status
Simulation time 925888688 ps
CPU time 3.4 seconds
Started Oct 15 12:54:39 PM UTC 24
Finished Oct 15 12:54:44 PM UTC 24
Peak memory 212364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989847964 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2989847964
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.99805224
Short name T542
Test name
Test status
Simulation time 66176699 ps
CPU time 1.18 seconds
Started Oct 15 12:54:39 PM UTC 24
Finished Oct 15 12:54:42 PM UTC 24
Peak memory 210984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99805224 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_mubi.99805224
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_smoke.2988800022
Short name T535
Test name
Test status
Simulation time 29552416 ps
CPU time 0.96 seconds
Started Oct 15 12:54:39 PM UTC 24
Finished Oct 15 12:54:41 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988800022 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.2988800022
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.1343736871
Short name T594
Test name
Test status
Simulation time 1570703179 ps
CPU time 2.4 seconds
Started Oct 15 12:54:41 PM UTC 24
Finished Oct 15 12:55:08 PM UTC 24
Peak memory 212748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343736871 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.1343736871
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all_with_rand_reset.3476499542
Short name T609
Test name
Test status
Simulation time 3505914088 ps
CPU time 13.08 seconds
Started Oct 15 12:54:41 PM UTC 24
Finished Oct 15 12:55:16 PM UTC 24
Peak memory 213004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3476499542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmg
r_stress_all_with_rand_reset.3476499542
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup.2104014936
Short name T539
Test name
Test status
Simulation time 287247232 ps
CPU time 1.06 seconds
Started Oct 15 12:54:39 PM UTC 24
Finished Oct 15 12:54:41 PM UTC 24
Peak memory 210080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104014936 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.2104014936
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup_reset.1023133188
Short name T538
Test name
Test status
Simulation time 252767783 ps
CPU time 1.06 seconds
Started Oct 15 12:54:39 PM UTC 24
Finished Oct 15 12:54:41 PM UTC 24
Peak memory 210916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023133188 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.1023133188
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/25.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_aborted_low_power.1779720649
Short name T556
Test name
Test status
Simulation time 45409376 ps
CPU time 0.86 seconds
Started Oct 15 12:54:43 PM UTC 24
Finished Oct 15 12:54:52 PM UTC 24
Peak memory 209620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779720649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.1779720649
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.4207977076
Short name T659
Test name
Test status
Simulation time 58589922 ps
CPU time 0.75 seconds
Started Oct 15 12:54:46 PM UTC 24
Finished Oct 15 12:55:32 PM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207977076 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disable_rom_integrity_check.4207977076
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.987932648
Short name T554
Test name
Test status
Simulation time 28912039 ps
CPU time 0.55 seconds
Started Oct 15 12:54:43 PM UTC 24
Finished Oct 15 12:54:52 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987932648 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst_malfunc.987932648
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.2690827675
Short name T552
Test name
Test status
Simulation time 112404606 ps
CPU time 0.87 seconds
Started Oct 15 12:54:44 PM UTC 24
Finished Oct 15 12:54:47 PM UTC 24
Peak memory 209852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690827675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.2690827675
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.1341988593
Short name T551
Test name
Test status
Simulation time 34939836 ps
CPU time 0.63 seconds
Started Oct 15 12:54:44 PM UTC 24
Finished Oct 15 12:54:47 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341988593 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.1341988593
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.330687340
Short name T555
Test name
Test status
Simulation time 30175290 ps
CPU time 0.57 seconds
Started Oct 15 12:54:43 PM UTC 24
Finished Oct 15 12:54:52 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330687340 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.330687340
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_invalid.1624338460
Short name T656
Test name
Test status
Simulation time 56802931 ps
CPU time 0.61 seconds
Started Oct 15 12:54:46 PM UTC 24
Finished Oct 15 12:55:31 PM UTC 24
Peak memory 212972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624338460 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invalid.1624338460
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.2097988610
Short name T658
Test name
Test status
Simulation time 114633989 ps
CPU time 0.87 seconds
Started Oct 15 12:54:46 PM UTC 24
Finished Oct 15 12:55:32 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097988610 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.2097988610
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.2746545907
Short name T558
Test name
Test status
Simulation time 296297970 ps
CPU time 0.84 seconds
Started Oct 15 12:54:43 PM UTC 24
Finished Oct 15 12:54:52 PM UTC 24
Peak memory 211420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746545907 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_ctrl_config_regwen.2746545907
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1641397911
Short name T560
Test name
Test status
Simulation time 937381471 ps
CPU time 1.92 seconds
Started Oct 15 12:54:43 PM UTC 24
Finished Oct 15 12:54:53 PM UTC 24
Peak memory 212688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641397911 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1641397911
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2902963614
Short name T561
Test name
Test status
Simulation time 884537207 ps
CPU time 2.98 seconds
Started Oct 15 12:54:43 PM UTC 24
Finished Oct 15 12:54:54 PM UTC 24
Peak memory 212688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902963614 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2902963614
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2367411372
Short name T559
Test name
Test status
Simulation time 84986482 ps
CPU time 0.85 seconds
Started Oct 15 12:54:43 PM UTC 24
Finished Oct 15 12:54:52 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367411372 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2367411372
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_smoke.1129443179
Short name T570
Test name
Test status
Simulation time 139512639 ps
CPU time 0.7 seconds
Started Oct 15 12:54:43 PM UTC 24
Finished Oct 15 12:54:57 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129443179 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1129443179
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.4084412111
Short name T589
Test name
Test status
Simulation time 525791755 ps
CPU time 1.77 seconds
Started Oct 15 12:54:48 PM UTC 24
Finished Oct 15 12:55:04 PM UTC 24
Peak memory 211464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084412111 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.4084412111
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.1066448466
Short name T94
Test name
Test status
Simulation time 5186512140 ps
CPU time 5.51 seconds
Started Oct 15 12:54:46 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 212800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1066448466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmg
r_stress_all_with_rand_reset.1066448466
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.3865940883
Short name T557
Test name
Test status
Simulation time 430055088 ps
CPU time 1.12 seconds
Started Oct 15 12:54:43 PM UTC 24
Finished Oct 15 12:54:52 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865940883 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.3865940883
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/26.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.526089247
Short name T562
Test name
Test status
Simulation time 28535361 ps
CPU time 0.8 seconds
Started Oct 15 12:54:48 PM UTC 24
Finished Oct 15 12:54:56 PM UTC 24
Peak memory 211148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526089247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.526089247
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.1229273695
Short name T573
Test name
Test status
Simulation time 66283458 ps
CPU time 0.66 seconds
Started Oct 15 12:54:57 PM UTC 24
Finished Oct 15 12:55:01 PM UTC 24
Peak memory 209060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229273695 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disable_rom_integrity_check.1229273695
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1617302583
Short name T566
Test name
Test status
Simulation time 30399351 ps
CPU time 0.6 seconds
Started Oct 15 12:54:52 PM UTC 24
Finished Oct 15 12:54:57 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617302583 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_malfunc.1617302583
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_escalation_timeout.1718368847
Short name T576
Test name
Test status
Simulation time 1840498662 ps
CPU time 0.79 seconds
Started Oct 15 12:54:53 PM UTC 24
Finished Oct 15 12:55:02 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718368847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.1718368847
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_glitch.3093912203
Short name T568
Test name
Test status
Simulation time 76938639 ps
CPU time 0.54 seconds
Started Oct 15 12:54:55 PM UTC 24
Finished Oct 15 12:54:57 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093912203 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.3093912203
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_global_esc.588811560
Short name T575
Test name
Test status
Simulation time 51883379 ps
CPU time 0.58 seconds
Started Oct 15 12:54:53 PM UTC 24
Finished Oct 15 12:55:02 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588811560 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.588811560
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_invalid.2403385803
Short name T579
Test name
Test status
Simulation time 44597541 ps
CPU time 0.77 seconds
Started Oct 15 12:54:58 PM UTC 24
Finished Oct 15 12:55:03 PM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403385803 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invalid.2403385803
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.3876780783
Short name T564
Test name
Test status
Simulation time 125931837 ps
CPU time 0.77 seconds
Started Oct 15 12:54:48 PM UTC 24
Finished Oct 15 12:54:57 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876780783 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_wakeup_race.3876780783
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.3515767542
Short name T563
Test name
Test status
Simulation time 33349604 ps
CPU time 0.76 seconds
Started Oct 15 12:54:48 PM UTC 24
Finished Oct 15 12:54:57 PM UTC 24
Peak memory 209736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515767542 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.3515767542
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset_invalid.1671649875
Short name T584
Test name
Test status
Simulation time 104957256 ps
CPU time 0.98 seconds
Started Oct 15 12:54:58 PM UTC 24
Finished Oct 15 12:55:03 PM UTC 24
Peak memory 221268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671649875 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.1671649875
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.3436798091
Short name T565
Test name
Test status
Simulation time 52040775 ps
CPU time 0.65 seconds
Started Oct 15 12:54:52 PM UTC 24
Finished Oct 15 12:54:57 PM UTC 24
Peak memory 210340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436798091 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_ctrl_config_regwen.3436798091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3296787852
Short name T572
Test name
Test status
Simulation time 919466489 ps
CPU time 2.79 seconds
Started Oct 15 12:54:52 PM UTC 24
Finished Oct 15 12:54:59 PM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296787852 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3296787852
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2906865947
Short name T571
Test name
Test status
Simulation time 1270248631 ps
CPU time 2.19 seconds
Started Oct 15 12:54:52 PM UTC 24
Finished Oct 15 12:54:59 PM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906865947 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2906865947
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.2635386969
Short name T569
Test name
Test status
Simulation time 244567888 ps
CPU time 0.76 seconds
Started Oct 15 12:54:52 PM UTC 24
Finished Oct 15 12:54:57 PM UTC 24
Peak memory 210892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635386969 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_mubi.2635386969
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.1817296209
Short name T577
Test name
Test status
Simulation time 31294677 ps
CPU time 0.59 seconds
Started Oct 15 12:54:48 PM UTC 24
Finished Oct 15 12:55:03 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817296209 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.1817296209
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all.3196420228
Short name T595
Test name
Test status
Simulation time 1552017330 ps
CPU time 5.79 seconds
Started Oct 15 12:54:58 PM UTC 24
Finished Oct 15 12:55:08 PM UTC 24
Peak memory 212388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196420228 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.3196420228
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all_with_rand_reset.1511884908
Short name T80
Test name
Test status
Simulation time 8897650945 ps
CPU time 13.82 seconds
Started Oct 15 12:54:58 PM UTC 24
Finished Oct 15 12:55:16 PM UTC 24
Peak memory 212620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1511884908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmg
r_stress_all_with_rand_reset.1511884908
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.4206168649
Short name T588
Test name
Test status
Simulation time 274293432 ps
CPU time 1.16 seconds
Started Oct 15 12:54:48 PM UTC 24
Finished Oct 15 12:55:03 PM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206168649 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.4206168649
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.29080829
Short name T567
Test name
Test status
Simulation time 290332242 ps
CPU time 0.9 seconds
Started Oct 15 12:54:48 PM UTC 24
Finished Oct 15 12:54:57 PM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29080829 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.29080829
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/27.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.2181281905
Short name T574
Test name
Test status
Simulation time 34842071 ps
CPU time 0.88 seconds
Started Oct 15 12:54:59 PM UTC 24
Finished Oct 15 12:55:02 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181281905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.2181281905
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.3115994437
Short name T605
Test name
Test status
Simulation time 89386042 ps
CPU time 0.7 seconds
Started Oct 15 12:55:04 PM UTC 24
Finished Oct 15 12:55:14 PM UTC 24
Peak memory 211196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115994437 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_disable_rom_integrity_check.3115994437
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.3978982382
Short name T553
Test name
Test status
Simulation time 31709056 ps
CPU time 0.63 seconds
Started Oct 15 12:55:04 PM UTC 24
Finished Oct 15 12:55:06 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978982382 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst_malfunc.3978982382
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_escalation_timeout.1650201347
Short name T607
Test name
Test status
Simulation time 483704645 ps
CPU time 0.85 seconds
Started Oct 15 12:55:04 PM UTC 24
Finished Oct 15 12:55:14 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650201347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.1650201347
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_glitch.2261478490
Short name T603
Test name
Test status
Simulation time 108108036 ps
CPU time 0.62 seconds
Started Oct 15 12:55:04 PM UTC 24
Finished Oct 15 12:55:14 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261478490 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.2261478490
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_global_esc.3047004745
Short name T590
Test name
Test status
Simulation time 23792575 ps
CPU time 0.6 seconds
Started Oct 15 12:55:04 PM UTC 24
Finished Oct 15 12:55:06 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047004745 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.3047004745
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_invalid.2460832648
Short name T606
Test name
Test status
Simulation time 145580617 ps
CPU time 0.73 seconds
Started Oct 15 12:55:04 PM UTC 24
Finished Oct 15 12:55:14 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460832648 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_invalid.2460832648
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_wakeup_race.426634729
Short name T587
Test name
Test status
Simulation time 334946815 ps
CPU time 1.08 seconds
Started Oct 15 12:54:58 PM UTC 24
Finished Oct 15 12:55:03 PM UTC 24
Peak memory 211188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426634729 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_wakeup_race.426634729
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset.4083589990
Short name T583
Test name
Test status
Simulation time 292679455 ps
CPU time 0.88 seconds
Started Oct 15 12:54:58 PM UTC 24
Finished Oct 15 12:55:03 PM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083589990 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.4083589990
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset_invalid.3634818709
Short name T592
Test name
Test status
Simulation time 269245136 ps
CPU time 0.74 seconds
Started Oct 15 12:55:04 PM UTC 24
Finished Oct 15 12:55:07 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634818709 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.3634818709
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.4239991725
Short name T591
Test name
Test status
Simulation time 194039571 ps
CPU time 0.91 seconds
Started Oct 15 12:55:04 PM UTC 24
Finished Oct 15 12:55:07 PM UTC 24
Peak memory 209036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239991725 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_ctrl_config_regwen.4239991725
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2407543989
Short name T578
Test name
Test status
Simulation time 1732116533 ps
CPU time 1.6 seconds
Started Oct 15 12:55:00 PM UTC 24
Finished Oct 15 12:55:03 PM UTC 24
Peak memory 212688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407543989 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2407543989
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.252752080
Short name T624
Test name
Test status
Simulation time 846976494 ps
CPU time 2.24 seconds
Started Oct 15 12:55:02 PM UTC 24
Finished Oct 15 12:55:19 PM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252752080 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.252752080
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2008969668
Short name T593
Test name
Test status
Simulation time 297023420 ps
CPU time 0.95 seconds
Started Oct 15 12:55:04 PM UTC 24
Finished Oct 15 12:55:07 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008969668 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2008969668
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_smoke.717413761
Short name T582
Test name
Test status
Simulation time 30243067 ps
CPU time 0.84 seconds
Started Oct 15 12:54:58 PM UTC 24
Finished Oct 15 12:55:03 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717413761 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.717413761
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all.2279795759
Short name T613
Test name
Test status
Simulation time 490657291 ps
CPU time 1.07 seconds
Started Oct 15 12:55:04 PM UTC 24
Finished Oct 15 12:55:17 PM UTC 24
Peak memory 211120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279795759 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.2279795759
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all_with_rand_reset.68997661
Short name T81
Test name
Test status
Simulation time 6830358569 ps
CPU time 12.97 seconds
Started Oct 15 12:55:04 PM UTC 24
Finished Oct 15 12:55:26 PM UTC 24
Peak memory 212940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=68997661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_
stress_all_with_rand_reset.68997661
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup.858525312
Short name T580
Test name
Test status
Simulation time 106788975 ps
CPU time 0.61 seconds
Started Oct 15 12:54:58 PM UTC 24
Finished Oct 15 12:55:03 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858525312 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.858525312
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup_reset.980206848
Short name T581
Test name
Test status
Simulation time 50066620 ps
CPU time 0.7 seconds
Started Oct 15 12:54:58 PM UTC 24
Finished Oct 15 12:55:03 PM UTC 24
Peak memory 209860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980206848 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.980206848
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/28.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_aborted_low_power.4060955421
Short name T618
Test name
Test status
Simulation time 38905331 ps
CPU time 0.82 seconds
Started Oct 15 12:55:05 PM UTC 24
Finished Oct 15 12:55:17 PM UTC 24
Peak memory 210680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060955421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.4060955421
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_disable_rom_integrity_check.1133671361
Short name T652
Test name
Test status
Simulation time 76192052 ps
CPU time 0.64 seconds
Started Oct 15 12:55:13 PM UTC 24
Finished Oct 15 12:55:28 PM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133671361 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_disable_rom_integrity_check.1133671361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2543558705
Short name T596
Test name
Test status
Simulation time 47980777 ps
CPU time 0.53 seconds
Started Oct 15 12:55:07 PM UTC 24
Finished Oct 15 12:55:12 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543558705 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_malfunc.2543558705
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_escalation_timeout.1062776783
Short name T601
Test name
Test status
Simulation time 110117280 ps
CPU time 0.8 seconds
Started Oct 15 12:55:09 PM UTC 24
Finished Oct 15 12:55:14 PM UTC 24
Peak memory 209060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062776783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.1062776783
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_glitch.2274124653
Short name T600
Test name
Test status
Simulation time 55139671 ps
CPU time 0.55 seconds
Started Oct 15 12:55:09 PM UTC 24
Finished Oct 15 12:55:13 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274124653 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.2274124653
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_global_esc.2806560106
Short name T597
Test name
Test status
Simulation time 44214688 ps
CPU time 0.57 seconds
Started Oct 15 12:55:07 PM UTC 24
Finished Oct 15 12:55:12 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806560106 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.2806560106
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_invalid.4107408515
Short name T653
Test name
Test status
Simulation time 73505141 ps
CPU time 0.74 seconds
Started Oct 15 12:55:13 PM UTC 24
Finished Oct 15 12:55:28 PM UTC 24
Peak memory 212968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107408515 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invalid.4107408515
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_wakeup_race.1744879154
Short name T621
Test name
Test status
Simulation time 272738388 ps
CPU time 1.45 seconds
Started Oct 15 12:55:05 PM UTC 24
Finished Oct 15 12:55:18 PM UTC 24
Peak memory 210340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744879154 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_wakeup_race.1744879154
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset.2014254759
Short name T604
Test name
Test status
Simulation time 34775556 ps
CPU time 0.64 seconds
Started Oct 15 12:55:04 PM UTC 24
Finished Oct 15 12:55:14 PM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014254759 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.2014254759
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset_invalid.508934962
Short name T651
Test name
Test status
Simulation time 157242433 ps
CPU time 0.81 seconds
Started Oct 15 12:55:13 PM UTC 24
Finished Oct 15 12:55:28 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508934962 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.508934962
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.2789304569
Short name T599
Test name
Test status
Simulation time 229277646 ps
CPU time 1.02 seconds
Started Oct 15 12:55:07 PM UTC 24
Finished Oct 15 12:55:13 PM UTC 24
Peak memory 210412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789304569 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_ctrl_config_regwen.2789304569
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2697818844
Short name T623
Test name
Test status
Simulation time 1092322398 ps
CPU time 2.16 seconds
Started Oct 15 12:55:05 PM UTC 24
Finished Oct 15 12:55:19 PM UTC 24
Peak memory 212444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697818844 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2697818844
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2952166615
Short name T602
Test name
Test status
Simulation time 1352498223 ps
CPU time 2.2 seconds
Started Oct 15 12:55:07 PM UTC 24
Finished Oct 15 12:55:14 PM UTC 24
Peak memory 212608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952166615 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2952166615
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.80675072
Short name T598
Test name
Test status
Simulation time 87668542 ps
CPU time 0.84 seconds
Started Oct 15 12:55:07 PM UTC 24
Finished Oct 15 12:55:12 PM UTC 24
Peak memory 209808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80675072 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_mubi.80675072
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_smoke.4206991532
Short name T608
Test name
Test status
Simulation time 61394428 ps
CPU time 0.65 seconds
Started Oct 15 12:55:04 PM UTC 24
Finished Oct 15 12:55:14 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206991532 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.4206991532
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all.960944866
Short name T633
Test name
Test status
Simulation time 657210273 ps
CPU time 1.43 seconds
Started Oct 15 12:55:13 PM UTC 24
Finished Oct 15 12:55:23 PM UTC 24
Peak memory 211024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960944866 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.960944866
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all_with_rand_reset.4178772155
Short name T93
Test name
Test status
Simulation time 5293348124 ps
CPU time 6.9 seconds
Started Oct 15 12:55:13 PM UTC 24
Finished Oct 15 12:55:27 PM UTC 24
Peak memory 212668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4178772155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmg
r_stress_all_with_rand_reset.4178772155
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup.2605647721
Short name T620
Test name
Test status
Simulation time 128963698 ps
CPU time 1.15 seconds
Started Oct 15 12:55:05 PM UTC 24
Finished Oct 15 12:55:18 PM UTC 24
Peak memory 209104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605647721 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.2605647721
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup_reset.2874911780
Short name T615
Test name
Test status
Simulation time 225540445 ps
CPU time 0.78 seconds
Started Oct 15 12:55:05 PM UTC 24
Finished Oct 15 12:55:17 PM UTC 24
Peak memory 211324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874911780 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.2874911780
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/29.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.672872063
Short name T112
Test name
Test status
Simulation time 33636641 ps
CPU time 1 seconds
Started Oct 15 12:53:05 PM UTC 24
Finished Oct 15 12:53:07 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672872063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.672872063
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.2347310271
Short name T158
Test name
Test status
Simulation time 66882281 ps
CPU time 1.12 seconds
Started Oct 15 12:53:10 PM UTC 24
Finished Oct 15 12:53:12 PM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347310271 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disable_rom_integrity_check.2347310271
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.1235577647
Short name T156
Test name
Test status
Simulation time 29654444 ps
CPU time 1 seconds
Started Oct 15 12:53:07 PM UTC 24
Finished Oct 15 12:53:09 PM UTC 24
Peak memory 208408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235577647 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_malfunc.1235577647
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.2286828063
Short name T152
Test name
Test status
Simulation time 144733445 ps
CPU time 1.49 seconds
Started Oct 15 12:53:10 PM UTC 24
Finished Oct 15 12:53:12 PM UTC 24
Peak memory 209240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286828063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.2286828063
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.1871268685
Short name T194
Test name
Test status
Simulation time 33253220 ps
CPU time 1.01 seconds
Started Oct 15 12:53:10 PM UTC 24
Finished Oct 15 12:53:12 PM UTC 24
Peak memory 208816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871268685 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.1871268685
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.307145420
Short name T193
Test name
Test status
Simulation time 91850535 ps
CPU time 0.95 seconds
Started Oct 15 12:53:10 PM UTC 24
Finished Oct 15 12:53:11 PM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307145420 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.307145420
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.609838316
Short name T195
Test name
Test status
Simulation time 79925323 ps
CPU time 1.02 seconds
Started Oct 15 12:53:10 PM UTC 24
Finished Oct 15 12:53:12 PM UTC 24
Peak memory 212960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609838316 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invalid.609838316
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.3257195730
Short name T189
Test name
Test status
Simulation time 183387071 ps
CPU time 1.37 seconds
Started Oct 15 12:53:05 PM UTC 24
Finished Oct 15 12:53:07 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257195730 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wakeup_race.3257195730
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.3501590869
Short name T187
Test name
Test status
Simulation time 66263811 ps
CPU time 1.19 seconds
Started Oct 15 12:53:05 PM UTC 24
Finished Oct 15 12:53:07 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501590869 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.3501590869
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.1133158373
Short name T196
Test name
Test status
Simulation time 113978444 ps
CPU time 1.66 seconds
Started Oct 15 12:53:10 PM UTC 24
Finished Oct 15 12:53:12 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133158373 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.1133158373
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.1366576900
Short name T29
Test name
Test status
Simulation time 473146210 ps
CPU time 1.78 seconds
Started Oct 15 12:53:11 PM UTC 24
Finished Oct 15 12:53:14 PM UTC 24
Peak memory 238524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366576900 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.1366576900
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.1816206045
Short name T83
Test name
Test status
Simulation time 333534595 ps
CPU time 1.97 seconds
Started Oct 15 12:53:09 PM UTC 24
Finished Oct 15 12:53:12 PM UTC 24
Peak memory 210600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816206045 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_ctrl_config_regwen.1816206045
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2323860606
Short name T164
Test name
Test status
Simulation time 761345414 ps
CPU time 3.71 seconds
Started Oct 15 12:53:06 PM UTC 24
Finished Oct 15 12:53:11 PM UTC 24
Peak memory 212544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323860606 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.2323860606
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.592052076
Short name T192
Test name
Test status
Simulation time 1197027087 ps
CPU time 3.55 seconds
Started Oct 15 12:53:06 PM UTC 24
Finished Oct 15 12:53:11 PM UTC 24
Peak memory 212364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592052076 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_inters
ig_mubi.592052076
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2727872387
Short name T191
Test name
Test status
Simulation time 285005731 ps
CPU time 1.33 seconds
Started Oct 15 12:53:07 PM UTC 24
Finished Oct 15 12:53:10 PM UTC 24
Peak memory 210520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727872387 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2727872387
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.926374030
Short name T186
Test name
Test status
Simulation time 28045247 ps
CPU time 1.09 seconds
Started Oct 15 12:53:05 PM UTC 24
Finished Oct 15 12:53:07 PM UTC 24
Peak memory 208992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926374030 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.926374030
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.2181748425
Short name T137
Test name
Test status
Simulation time 1680717654 ps
CPU time 6.08 seconds
Started Oct 15 12:53:11 PM UTC 24
Finished Oct 15 12:53:18 PM UTC 24
Peak memory 212404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181748425 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.2181748425
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.3304395539
Short name T140
Test name
Test status
Simulation time 3848950357 ps
CPU time 14.66 seconds
Started Oct 15 12:53:11 PM UTC 24
Finished Oct 15 12:53:27 PM UTC 24
Peak memory 212668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3304395539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr
_stress_all_with_rand_reset.3304395539
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.2844505057
Short name T190
Test name
Test status
Simulation time 390866987 ps
CPU time 1.63 seconds
Started Oct 15 12:53:05 PM UTC 24
Finished Oct 15 12:53:08 PM UTC 24
Peak memory 210084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844505057 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.2844505057
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.507777942
Short name T188
Test name
Test status
Simulation time 53992435 ps
CPU time 1.08 seconds
Started Oct 15 12:53:05 PM UTC 24
Finished Oct 15 12:53:07 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507777942 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.507777942
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/3.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_aborted_low_power.2315272720
Short name T617
Test name
Test status
Simulation time 100834346 ps
CPU time 0.77 seconds
Started Oct 15 12:55:15 PM UTC 24
Finished Oct 15 12:55:17 PM UTC 24
Peak memory 210616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315272720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.2315272720
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.4102292149
Short name T634
Test name
Test status
Simulation time 73189766 ps
CPU time 0.65 seconds
Started Oct 15 12:55:18 PM UTC 24
Finished Oct 15 12:55:23 PM UTC 24
Peak memory 209068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102292149 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disable_rom_integrity_check.4102292149
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3145259637
Short name T626
Test name
Test status
Simulation time 31927219 ps
CPU time 0.56 seconds
Started Oct 15 12:55:17 PM UTC 24
Finished Oct 15 12:55:21 PM UTC 24
Peak memory 209040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145259637 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_malfunc.3145259637
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_escalation_timeout.11780371
Short name T641
Test name
Test status
Simulation time 132696281 ps
CPU time 0.93 seconds
Started Oct 15 12:55:18 PM UTC 24
Finished Oct 15 12:55:26 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11780371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=
pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.11780371
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_glitch.1015029768
Short name T678
Test name
Test status
Simulation time 62671906 ps
CPU time 0.64 seconds
Started Oct 15 12:55:18 PM UTC 24
Finished Oct 15 12:55:33 PM UTC 24
Peak memory 208932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015029768 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.1015029768
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_global_esc.2292486561
Short name T632
Test name
Test status
Simulation time 54606317 ps
CPU time 0.62 seconds
Started Oct 15 12:55:18 PM UTC 24
Finished Oct 15 12:55:23 PM UTC 24
Peak memory 209136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292486561 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.2292486561
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_invalid.2600738400
Short name T637
Test name
Test status
Simulation time 77603849 ps
CPU time 0.65 seconds
Started Oct 15 12:55:18 PM UTC 24
Finished Oct 15 12:55:26 PM UTC 24
Peak memory 212872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600738400 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_invalid.2600738400
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_wakeup_race.1074576471
Short name T611
Test name
Test status
Simulation time 123973726 ps
CPU time 0.89 seconds
Started Oct 15 12:55:14 PM UTC 24
Finished Oct 15 12:55:17 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074576471 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_wakeup_race.1074576471
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset.3245121174
Short name T614
Test name
Test status
Simulation time 90422414 ps
CPU time 0.82 seconds
Started Oct 15 12:55:14 PM UTC 24
Finished Oct 15 12:55:17 PM UTC 24
Peak memory 209616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245121174 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.3245121174
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset_invalid.3982651232
Short name T640
Test name
Test status
Simulation time 133468856 ps
CPU time 0.85 seconds
Started Oct 15 12:55:18 PM UTC 24
Finished Oct 15 12:55:26 PM UTC 24
Peak memory 221268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982651232 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.3982651232
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.4246251590
Short name T627
Test name
Test status
Simulation time 223939727 ps
CPU time 1.18 seconds
Started Oct 15 12:55:17 PM UTC 24
Finished Oct 15 12:55:22 PM UTC 24
Peak memory 210596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246251590 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_ctrl_config_regwen.4246251590
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1394640145
Short name T625
Test name
Test status
Simulation time 851869194 ps
CPU time 2.92 seconds
Started Oct 15 12:55:15 PM UTC 24
Finished Oct 15 12:55:19 PM UTC 24
Peak memory 212256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394640145 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1394640145
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2389355382
Short name T622
Test name
Test status
Simulation time 964734218 ps
CPU time 2.04 seconds
Started Oct 15 12:55:15 PM UTC 24
Finished Oct 15 12:55:18 PM UTC 24
Peak memory 212304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389355382 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2389355382
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.4199544001
Short name T619
Test name
Test status
Simulation time 140202152 ps
CPU time 0.95 seconds
Started Oct 15 12:55:15 PM UTC 24
Finished Oct 15 12:55:17 PM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199544001 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_mubi.4199544001
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_smoke.1773404460
Short name T610
Test name
Test status
Simulation time 52908699 ps
CPU time 0.6 seconds
Started Oct 15 12:55:14 PM UTC 24
Finished Oct 15 12:55:17 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773404460 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.1773404460
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all.3760675978
Short name T642
Test name
Test status
Simulation time 229774293 ps
CPU time 0.87 seconds
Started Oct 15 12:55:18 PM UTC 24
Finished Oct 15 12:55:26 PM UTC 24
Peak memory 211120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760675978 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.3760675978
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all_with_rand_reset.4099822225
Short name T679
Test name
Test status
Simulation time 3178768144 ps
CPU time 7.92 seconds
Started Oct 15 12:55:18 PM UTC 24
Finished Oct 15 12:55:34 PM UTC 24
Peak memory 212732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4099822225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmg
r_stress_all_with_rand_reset.4099822225
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup.234404018
Short name T616
Test name
Test status
Simulation time 236449709 ps
CPU time 0.8 seconds
Started Oct 15 12:55:14 PM UTC 24
Finished Oct 15 12:55:17 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234404018 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.234404018
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup_reset.2720435470
Short name T612
Test name
Test status
Simulation time 203858672 ps
CPU time 0.76 seconds
Started Oct 15 12:55:14 PM UTC 24
Finished Oct 15 12:55:17 PM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720435470 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.2720435470
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/30.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_aborted_low_power.3875322004
Short name T629
Test name
Test status
Simulation time 117073182 ps
CPU time 0.79 seconds
Started Oct 15 12:55:19 PM UTC 24
Finished Oct 15 12:55:22 PM UTC 24
Peak memory 210276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875322004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.3875322004
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_disable_rom_integrity_check.446620318
Short name T648
Test name
Test status
Simulation time 57958012 ps
CPU time 0.78 seconds
Started Oct 15 12:55:24 PM UTC 24
Finished Oct 15 12:55:27 PM UTC 24
Peak memory 211316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446620318 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disable_rom_integrity_check.446620318
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.3445438697
Short name T649
Test name
Test status
Simulation time 39865911 ps
CPU time 0.72 seconds
Started Oct 15 12:55:22 PM UTC 24
Finished Oct 15 12:55:28 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445438697 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_malfunc.3445438697
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_escalation_timeout.664564793
Short name T643
Test name
Test status
Simulation time 382601604 ps
CPU time 0.84 seconds
Started Oct 15 12:55:24 PM UTC 24
Finished Oct 15 12:55:27 PM UTC 24
Peak memory 209184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664564793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.664564793
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_glitch.64861285
Short name T645
Test name
Test status
Simulation time 40130670 ps
CPU time 0.75 seconds
Started Oct 15 12:55:24 PM UTC 24
Finished Oct 15 12:55:27 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64861285 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.64861285
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_global_esc.3726196605
Short name T646
Test name
Test status
Simulation time 35924194 ps
CPU time 0.79 seconds
Started Oct 15 12:55:24 PM UTC 24
Finished Oct 15 12:55:27 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726196605 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.3726196605
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_invalid.3339850698
Short name T647
Test name
Test status
Simulation time 41413931 ps
CPU time 0.68 seconds
Started Oct 15 12:55:24 PM UTC 24
Finished Oct 15 12:55:27 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339850698 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invalid.3339850698
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_wakeup_race.1708069644
Short name T628
Test name
Test status
Simulation time 347545988 ps
CPU time 0.86 seconds
Started Oct 15 12:55:19 PM UTC 24
Finished Oct 15 12:55:22 PM UTC 24
Peak memory 210892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708069644 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_wakeup_race.1708069644
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset.456069554
Short name T638
Test name
Test status
Simulation time 53195301 ps
CPU time 0.6 seconds
Started Oct 15 12:55:18 PM UTC 24
Finished Oct 15 12:55:26 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456069554 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.456069554
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset_invalid.3145459360
Short name T644
Test name
Test status
Simulation time 458716921 ps
CPU time 0.75 seconds
Started Oct 15 12:55:24 PM UTC 24
Finished Oct 15 12:55:27 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145459360 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.3145459360
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.2086249532
Short name T650
Test name
Test status
Simulation time 149851076 ps
CPU time 0.8 seconds
Started Oct 15 12:55:22 PM UTC 24
Finished Oct 15 12:55:28 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086249532 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_ctrl_config_regwen.2086249532
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.482919499
Short name T635
Test name
Test status
Simulation time 1332962068 ps
CPU time 1.82 seconds
Started Oct 15 12:55:20 PM UTC 24
Finished Oct 15 12:55:23 PM UTC 24
Peak memory 212616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482919499 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.482919499
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.327939464
Short name T636
Test name
Test status
Simulation time 1152426404 ps
CPU time 2.01 seconds
Started Oct 15 12:55:20 PM UTC 24
Finished Oct 15 12:55:24 PM UTC 24
Peak memory 212476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327939464 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.327939464
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3894624833
Short name T654
Test name
Test status
Simulation time 142746377 ps
CPU time 0.97 seconds
Started Oct 15 12:55:22 PM UTC 24
Finished Oct 15 12:55:28 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894624833 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3894624833
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_smoke.1450095267
Short name T639
Test name
Test status
Simulation time 31921520 ps
CPU time 0.66 seconds
Started Oct 15 12:55:18 PM UTC 24
Finished Oct 15 12:55:26 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450095267 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.1450095267
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all.3128262337
Short name T655
Test name
Test status
Simulation time 710834694 ps
CPU time 2.13 seconds
Started Oct 15 12:55:25 PM UTC 24
Finished Oct 15 12:55:29 PM UTC 24
Peak memory 212396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128262337 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.3128262337
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all_with_rand_reset.3097176504
Short name T148
Test name
Test status
Simulation time 2579357989 ps
CPU time 7.83 seconds
Started Oct 15 12:55:24 PM UTC 24
Finished Oct 15 12:55:34 PM UTC 24
Peak memory 212620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3097176504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmg
r_stress_all_with_rand_reset.3097176504
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup.2442042473
Short name T630
Test name
Test status
Simulation time 222521211 ps
CPU time 1.05 seconds
Started Oct 15 12:55:19 PM UTC 24
Finished Oct 15 12:55:22 PM UTC 24
Peak memory 210200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442042473 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.2442042473
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup_reset.3750870837
Short name T631
Test name
Test status
Simulation time 222421298 ps
CPU time 1.15 seconds
Started Oct 15 12:55:19 PM UTC 24
Finished Oct 15 12:55:22 PM UTC 24
Peak memory 211384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750870837 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.3750870837
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/31.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.874584851
Short name T677
Test name
Test status
Simulation time 69879316 ps
CPU time 0.99 seconds
Started Oct 15 12:55:27 PM UTC 24
Finished Oct 15 12:55:33 PM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874584851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.874584851
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.2401117949
Short name T661
Test name
Test status
Simulation time 82131142 ps
CPU time 0.65 seconds
Started Oct 15 12:55:29 PM UTC 24
Finished Oct 15 12:55:32 PM UTC 24
Peak memory 211264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401117949 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disable_rom_integrity_check.2401117949
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.990508401
Short name T671
Test name
Test status
Simulation time 31889298 ps
CPU time 0.59 seconds
Started Oct 15 12:55:27 PM UTC 24
Finished Oct 15 12:55:32 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990508401 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_malfunc.990508401
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_escalation_timeout.1135950767
Short name T684
Test name
Test status
Simulation time 113636032 ps
CPU time 0.88 seconds
Started Oct 15 12:55:29 PM UTC 24
Finished Oct 15 12:55:34 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135950767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.1135950767
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_glitch.2430269120
Short name T657
Test name
Test status
Simulation time 29295619 ps
CPU time 0.57 seconds
Started Oct 15 12:55:29 PM UTC 24
Finished Oct 15 12:55:32 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430269120 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.2430269120
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_global_esc.1720626141
Short name T680
Test name
Test status
Simulation time 85038661 ps
CPU time 0.64 seconds
Started Oct 15 12:55:29 PM UTC 24
Finished Oct 15 12:55:34 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720626141 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.1720626141
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_invalid.107986986
Short name T662
Test name
Test status
Simulation time 79803798 ps
CPU time 0.65 seconds
Started Oct 15 12:55:29 PM UTC 24
Finished Oct 15 12:55:32 PM UTC 24
Peak memory 212960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107986986 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invalid.107986986
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_wakeup_race.1558010295
Short name T675
Test name
Test status
Simulation time 212652420 ps
CPU time 0.99 seconds
Started Oct 15 12:55:27 PM UTC 24
Finished Oct 15 12:55:33 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558010295 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_wakeup_race.1558010295
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset.3984077239
Short name T672
Test name
Test status
Simulation time 366157349 ps
CPU time 0.83 seconds
Started Oct 15 12:55:27 PM UTC 24
Finished Oct 15 12:55:32 PM UTC 24
Peak memory 208956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984077239 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.3984077239
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset_invalid.293269619
Short name T660
Test name
Test status
Simulation time 171588256 ps
CPU time 0.9 seconds
Started Oct 15 12:55:29 PM UTC 24
Finished Oct 15 12:55:32 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293269619 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.293269619
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.1420257208
Short name T683
Test name
Test status
Simulation time 200990431 ps
CPU time 0.93 seconds
Started Oct 15 12:55:29 PM UTC 24
Finished Oct 15 12:55:34 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420257208 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_ctrl_config_regwen.1420257208
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1590167342
Short name T688
Test name
Test status
Simulation time 731274923 ps
CPU time 2.98 seconds
Started Oct 15 12:55:27 PM UTC 24
Finished Oct 15 12:55:35 PM UTC 24
Peak memory 212432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590167342 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1590167342
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.948168621
Short name T681
Test name
Test status
Simulation time 1067338636 ps
CPU time 1.99 seconds
Started Oct 15 12:55:27 PM UTC 24
Finished Oct 15 12:55:34 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948168621 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.948168621
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2327046626
Short name T673
Test name
Test status
Simulation time 181792422 ps
CPU time 0.8 seconds
Started Oct 15 12:55:27 PM UTC 24
Finished Oct 15 12:55:33 PM UTC 24
Peak memory 210628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327046626 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2327046626
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_smoke.4276689422
Short name T669
Test name
Test status
Simulation time 163592243 ps
CPU time 0.72 seconds
Started Oct 15 12:55:27 PM UTC 24
Finished Oct 15 12:55:32 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276689422 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.4276689422
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all.2665837923
Short name T691
Test name
Test status
Simulation time 2147132743 ps
CPU time 4.3 seconds
Started Oct 15 12:55:29 PM UTC 24
Finished Oct 15 12:55:36 PM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665837923 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.2665837923
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.3190965767
Short name T717
Test name
Test status
Simulation time 21646172092 ps
CPU time 12.79 seconds
Started Oct 15 12:55:29 PM UTC 24
Finished Oct 15 12:55:44 PM UTC 24
Peak memory 212852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3190965767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmg
r_stress_all_with_rand_reset.3190965767
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup.901804241
Short name T676
Test name
Test status
Simulation time 226385818 ps
CPU time 1.02 seconds
Started Oct 15 12:55:27 PM UTC 24
Finished Oct 15 12:55:33 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901804241 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.901804241
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup_reset.2123536140
Short name T674
Test name
Test status
Simulation time 81188196 ps
CPU time 0.79 seconds
Started Oct 15 12:55:27 PM UTC 24
Finished Oct 15 12:55:33 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123536140 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.2123536140
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/32.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_aborted_low_power.3849929649
Short name T685
Test name
Test status
Simulation time 27501561 ps
CPU time 0.93 seconds
Started Oct 15 12:55:32 PM UTC 24
Finished Oct 15 12:55:34 PM UTC 24
Peak memory 210220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849929649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.3849929649
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.2668482799
Short name T697
Test name
Test status
Simulation time 72584803 ps
CPU time 0.98 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 210388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668482799 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_disable_rom_integrity_check.2668482799
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2806791872
Short name T686
Test name
Test status
Simulation time 66460033 ps
CPU time 0.85 seconds
Started Oct 15 12:55:32 PM UTC 24
Finished Oct 15 12:55:34 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806791872 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst_malfunc.2806791872
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_escalation_timeout.3383793578
Short name T694
Test name
Test status
Simulation time 422657039 ps
CPU time 0.94 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383793578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.3383793578
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_glitch.910882296
Short name T695
Test name
Test status
Simulation time 40899445 ps
CPU time 0.82 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 208892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910882296 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.910882296
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_global_esc.1980821942
Short name T692
Test name
Test status
Simulation time 37263203 ps
CPU time 0.77 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980821942 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.1980821942
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_invalid.2757536201
Short name T693
Test name
Test status
Simulation time 42701581 ps
CPU time 0.72 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757536201 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_invalid.2757536201
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_wakeup_race.2934789798
Short name T670
Test name
Test status
Simulation time 304840438 ps
CPU time 1.03 seconds
Started Oct 15 12:55:29 PM UTC 24
Finished Oct 15 12:55:32 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934789798 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wakeup_race.2934789798
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset.237205449
Short name T665
Test name
Test status
Simulation time 54552912 ps
CPU time 0.7 seconds
Started Oct 15 12:55:29 PM UTC 24
Finished Oct 15 12:55:32 PM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237205449 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.237205449
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.1550884762
Short name T696
Test name
Test status
Simulation time 154790991 ps
CPU time 0.86 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550884762 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.1550884762
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.1341073137
Short name T699
Test name
Test status
Simulation time 333422268 ps
CPU time 1.28 seconds
Started Oct 15 12:55:33 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 211276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341073137 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_ctrl_config_regwen.1341073137
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2292416658
Short name T689
Test name
Test status
Simulation time 1165033497 ps
CPU time 2.11 seconds
Started Oct 15 12:55:32 PM UTC 24
Finished Oct 15 12:55:35 PM UTC 24
Peak memory 212264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292416658 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2292416658
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2053396505
Short name T690
Test name
Test status
Simulation time 2230159834 ps
CPU time 2.1 seconds
Started Oct 15 12:55:32 PM UTC 24
Finished Oct 15 12:55:35 PM UTC 24
Peak memory 212704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053396505 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2053396505
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.2426086976
Short name T687
Test name
Test status
Simulation time 74567406 ps
CPU time 1.02 seconds
Started Oct 15 12:55:32 PM UTC 24
Finished Oct 15 12:55:34 PM UTC 24
Peak memory 209676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426086976 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_mubi.2426086976
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_smoke.1184838118
Short name T663
Test name
Test status
Simulation time 128210016 ps
CPU time 0.64 seconds
Started Oct 15 12:55:29 PM UTC 24
Finished Oct 15 12:55:32 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184838118 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.1184838118
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all.148018554
Short name T709
Test name
Test status
Simulation time 1708236177 ps
CPU time 3.84 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:55:40 PM UTC 24
Peak memory 212488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148018554 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.148018554
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all_with_rand_reset.3690437631
Short name T69
Test name
Test status
Simulation time 7877359780 ps
CPU time 25.54 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:56:02 PM UTC 24
Peak memory 212988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3690437631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmg
r_stress_all_with_rand_reset.3690437631
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup.692288930
Short name T666
Test name
Test status
Simulation time 39221462 ps
CPU time 0.59 seconds
Started Oct 15 12:55:30 PM UTC 24
Finished Oct 15 12:55:32 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692288930 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.692288930
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup_reset.3376194873
Short name T668
Test name
Test status
Simulation time 63758098 ps
CPU time 0.68 seconds
Started Oct 15 12:55:30 PM UTC 24
Finished Oct 15 12:55:32 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376194873 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.3376194873
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/33.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_aborted_low_power.2053217828
Short name T701
Test name
Test status
Simulation time 33882704 ps
CPU time 0.83 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 210100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053217828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.2053217828
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_disable_rom_integrity_check.4212168706
Short name T682
Test name
Test status
Simulation time 55618996 ps
CPU time 0.86 seconds
Started Oct 15 12:55:36 PM UTC 24
Finished Oct 15 12:55:48 PM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212168706 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disable_rom_integrity_check.4212168706
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.330938585
Short name T703
Test name
Test status
Simulation time 38345739 ps
CPU time 0.62 seconds
Started Oct 15 12:55:35 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330938585 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_malfunc.330938585
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_escalation_timeout.3070395037
Short name T735
Test name
Test status
Simulation time 210702816 ps
CPU time 0.91 seconds
Started Oct 15 12:55:35 PM UTC 24
Finished Oct 15 12:55:48 PM UTC 24
Peak memory 209240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070395037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.3070395037
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_glitch.3747278235
Short name T734
Test name
Test status
Simulation time 51109768 ps
CPU time 0.76 seconds
Started Oct 15 12:55:36 PM UTC 24
Finished Oct 15 12:55:48 PM UTC 24
Peak memory 208932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747278235 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.3747278235
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_global_esc.3115922873
Short name T702
Test name
Test status
Simulation time 44683227 ps
CPU time 0.55 seconds
Started Oct 15 12:55:35 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115922873 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.3115922873
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_invalid.2524625962
Short name T737
Test name
Test status
Simulation time 131866276 ps
CPU time 0.89 seconds
Started Oct 15 12:55:36 PM UTC 24
Finished Oct 15 12:55:48 PM UTC 24
Peak memory 212968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524625962 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_invalid.2524625962
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_wakeup_race.3592581906
Short name T704
Test name
Test status
Simulation time 249293254 ps
CPU time 1 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592581906 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_wakeup_race.3592581906
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset.3364829839
Short name T698
Test name
Test status
Simulation time 59131367 ps
CPU time 0.75 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364829839 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.3364829839
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset_invalid.1833497133
Short name T664
Test name
Test status
Simulation time 122933732 ps
CPU time 0.87 seconds
Started Oct 15 12:55:36 PM UTC 24
Finished Oct 15 12:55:48 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833497133 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.1833497133
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.4035681558
Short name T736
Test name
Test status
Simulation time 102468369 ps
CPU time 1.07 seconds
Started Oct 15 12:55:35 PM UTC 24
Finished Oct 15 12:55:48 PM UTC 24
Peak memory 209860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035681558 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_ctrl_config_regwen.4035681558
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1532345340
Short name T708
Test name
Test status
Simulation time 839157363 ps
CPU time 3.21 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:55:40 PM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532345340 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1532345340
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1694587903
Short name T707
Test name
Test status
Simulation time 1248458841 ps
CPU time 2.11 seconds
Started Oct 15 12:55:35 PM UTC 24
Finished Oct 15 12:55:39 PM UTC 24
Peak memory 212752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694587903 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1694587903
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.4255409624
Short name T733
Test name
Test status
Simulation time 87546524 ps
CPU time 0.88 seconds
Started Oct 15 12:55:35 PM UTC 24
Finished Oct 15 12:55:48 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255409624 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_mubi.4255409624
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_smoke.3873864876
Short name T700
Test name
Test status
Simulation time 157256135 ps
CPU time 0.75 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873864876 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.3873864876
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all.1080089882
Short name T718
Test name
Test status
Simulation time 1701932620 ps
CPU time 3.68 seconds
Started Oct 15 12:55:37 PM UTC 24
Finished Oct 15 12:55:45 PM UTC 24
Peak memory 212680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080089882 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.1080089882
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all_with_rand_reset.86251997
Short name T70
Test name
Test status
Simulation time 1756027578 ps
CPU time 7.28 seconds
Started Oct 15 12:55:37 PM UTC 24
Finished Oct 15 12:55:49 PM UTC 24
Peak memory 212860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=86251997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_
stress_all_with_rand_reset.86251997
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup.997079438
Short name T706
Test name
Test status
Simulation time 184839982 ps
CPU time 1.08 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:55:38 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997079438 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.997079438
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup_reset.1901302401
Short name T705
Test name
Test status
Simulation time 503417873 ps
CPU time 1.13 seconds
Started Oct 15 12:55:34 PM UTC 24
Finished Oct 15 12:55:37 PM UTC 24
Peak memory 211204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901302401 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.1901302401
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/34.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_aborted_low_power.4109795342
Short name T722
Test name
Test status
Simulation time 40117849 ps
CPU time 0.92 seconds
Started Oct 15 12:55:38 PM UTC 24
Finished Oct 15 12:55:46 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109795342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.4109795342
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_disable_rom_integrity_check.2936657076
Short name T725
Test name
Test status
Simulation time 99788259 ps
CPU time 0.69 seconds
Started Oct 15 12:55:39 PM UTC 24
Finished Oct 15 12:55:47 PM UTC 24
Peak memory 208712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936657076 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disable_rom_integrity_check.2936657076
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.1095927675
Short name T723
Test name
Test status
Simulation time 28799737 ps
CPU time 0.69 seconds
Started Oct 15 12:55:38 PM UTC 24
Finished Oct 15 12:55:47 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095927675 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_malfunc.1095927675
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_escalation_timeout.1293414665
Short name T727
Test name
Test status
Simulation time 398904819 ps
CPU time 0.93 seconds
Started Oct 15 12:55:38 PM UTC 24
Finished Oct 15 12:55:47 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293414665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.1293414665
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_glitch.4020881412
Short name T724
Test name
Test status
Simulation time 35382383 ps
CPU time 0.64 seconds
Started Oct 15 12:55:39 PM UTC 24
Finished Oct 15 12:55:47 PM UTC 24
Peak memory 208672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020881412 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.4020881412
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_global_esc.4207625307
Short name T726
Test name
Test status
Simulation time 50762659 ps
CPU time 0.78 seconds
Started Oct 15 12:55:38 PM UTC 24
Finished Oct 15 12:55:47 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207625307 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.4207625307
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_invalid.4198106891
Short name T710
Test name
Test status
Simulation time 42849412 ps
CPU time 0.67 seconds
Started Oct 15 12:55:39 PM UTC 24
Finished Oct 15 12:55:42 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198106891 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invalid.4198106891
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_wakeup_race.211970738
Short name T716
Test name
Test status
Simulation time 201940754 ps
CPU time 1.17 seconds
Started Oct 15 12:55:38 PM UTC 24
Finished Oct 15 12:55:44 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211970738 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_wakeup_race.211970738
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset.3250861428
Short name T713
Test name
Test status
Simulation time 76768608 ps
CPU time 0.66 seconds
Started Oct 15 12:55:38 PM UTC 24
Finished Oct 15 12:55:43 PM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250861428 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.3250861428
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset_invalid.75269054
Short name T730
Test name
Test status
Simulation time 92432786 ps
CPU time 0.97 seconds
Started Oct 15 12:55:39 PM UTC 24
Finished Oct 15 12:55:47 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75269054 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.75269054
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.3270023827
Short name T719
Test name
Test status
Simulation time 237033775 ps
CPU time 0.85 seconds
Started Oct 15 12:55:38 PM UTC 24
Finished Oct 15 12:55:46 PM UTC 24
Peak memory 210340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270023827 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_ctrl_config_regwen.3270023827
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1441967152
Short name T743
Test name
Test status
Simulation time 848953450 ps
CPU time 3.09 seconds
Started Oct 15 12:55:38 PM UTC 24
Finished Oct 15 12:55:49 PM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441967152 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1441967152
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1262554493
Short name T738
Test name
Test status
Simulation time 1289048798 ps
CPU time 2.12 seconds
Started Oct 15 12:55:38 PM UTC 24
Finished Oct 15 12:55:48 PM UTC 24
Peak memory 212496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262554493 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1262554493
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.2187028045
Short name T721
Test name
Test status
Simulation time 439633772 ps
CPU time 0.79 seconds
Started Oct 15 12:55:38 PM UTC 24
Finished Oct 15 12:55:46 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187028045 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_mubi.2187028045
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_smoke.2613886960
Short name T711
Test name
Test status
Simulation time 32611642 ps
CPU time 0.79 seconds
Started Oct 15 12:55:37 PM UTC 24
Finished Oct 15 12:55:42 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613886960 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.2613886960
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all.2581965913
Short name T715
Test name
Test status
Simulation time 903498534 ps
CPU time 1.67 seconds
Started Oct 15 12:55:41 PM UTC 24
Finished Oct 15 12:55:44 PM UTC 24
Peak memory 210964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581965913 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.2581965913
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all_with_rand_reset.3060675884
Short name T95
Test name
Test status
Simulation time 12701822970 ps
CPU time 18.8 seconds
Started Oct 15 12:55:40 PM UTC 24
Finished Oct 15 12:56:00 PM UTC 24
Peak memory 212732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3060675884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmg
r_stress_all_with_rand_reset.3060675884
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup.2290509784
Short name T714
Test name
Test status
Simulation time 794530539 ps
CPU time 0.75 seconds
Started Oct 15 12:55:38 PM UTC 24
Finished Oct 15 12:55:43 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290509784 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.2290509784
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup_reset.2996947903
Short name T720
Test name
Test status
Simulation time 92677231 ps
CPU time 0.76 seconds
Started Oct 15 12:55:38 PM UTC 24
Finished Oct 15 12:55:46 PM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996947903 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.2996947903
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/35.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_aborted_low_power.2580211463
Short name T729
Test name
Test status
Simulation time 99601810 ps
CPU time 0.81 seconds
Started Oct 15 12:55:44 PM UTC 24
Finished Oct 15 12:55:47 PM UTC 24
Peak memory 210616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580211463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.2580211463
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.647558614
Short name T731
Test name
Test status
Simulation time 40024559 ps
CPU time 0.52 seconds
Started Oct 15 12:55:45 PM UTC 24
Finished Oct 15 12:55:47 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647558614 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_malfunc.647558614
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_glitch.3988454948
Short name T782
Test name
Test status
Simulation time 61897203 ps
CPU time 0.56 seconds
Started Oct 15 12:55:48 PM UTC 24
Finished Oct 15 12:56:02 PM UTC 24
Peak memory 208932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988454948 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.3988454948
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_global_esc.3610284356
Short name T789
Test name
Test status
Simulation time 77403559 ps
CPU time 0.78 seconds
Started Oct 15 12:55:48 PM UTC 24
Finished Oct 15 12:56:03 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610284356 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.3610284356
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_invalid.1420603306
Short name T792
Test name
Test status
Simulation time 66830907 ps
CPU time 0.74 seconds
Started Oct 15 12:55:48 PM UTC 24
Finished Oct 15 12:56:03 PM UTC 24
Peak memory 212968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420603306 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_invalid.1420603306
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_wakeup_race.2629258326
Short name T740
Test name
Test status
Simulation time 104672677 ps
CPU time 0.97 seconds
Started Oct 15 12:55:43 PM UTC 24
Finished Oct 15 12:55:48 PM UTC 24
Peak memory 208988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629258326 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_wakeup_race.2629258326
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset.2731959132
Short name T739
Test name
Test status
Simulation time 53985873 ps
CPU time 0.85 seconds
Started Oct 15 12:55:43 PM UTC 24
Finished Oct 15 12:55:48 PM UTC 24
Peak memory 209012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731959132 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.2731959132
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset_invalid.3089280198
Short name T796
Test name
Test status
Simulation time 118571135 ps
CPU time 1.19 seconds
Started Oct 15 12:55:48 PM UTC 24
Finished Oct 15 12:56:03 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089280198 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.3089280198
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.703866227
Short name T755
Test name
Test status
Simulation time 94055059 ps
CPU time 0.62 seconds
Started Oct 15 12:55:48 PM UTC 24
Finished Oct 15 12:55:56 PM UTC 24
Peak memory 209788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703866227 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_ctrl_config_regwen.703866227
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3614542722
Short name T741
Test name
Test status
Simulation time 1455838396 ps
CPU time 2 seconds
Started Oct 15 12:55:45 PM UTC 24
Finished Oct 15 12:55:49 PM UTC 24
Peak memory 212672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614542722 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3614542722
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3266288076
Short name T742
Test name
Test status
Simulation time 1133865370 ps
CPU time 2.19 seconds
Started Oct 15 12:55:45 PM UTC 24
Finished Oct 15 12:55:49 PM UTC 24
Peak memory 212496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266288076 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3266288076
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.3043039944
Short name T732
Test name
Test status
Simulation time 647194040 ps
CPU time 0.92 seconds
Started Oct 15 12:55:45 PM UTC 24
Finished Oct 15 12:55:48 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043039944 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig_mubi.3043039944
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_smoke.975186750
Short name T712
Test name
Test status
Simulation time 45800123 ps
CPU time 0.57 seconds
Started Oct 15 12:55:41 PM UTC 24
Finished Oct 15 12:55:43 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975186750 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.975186750
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all.1683989634
Short name T817
Test name
Test status
Simulation time 2001107236 ps
CPU time 5.16 seconds
Started Oct 15 12:55:48 PM UTC 24
Finished Oct 15 12:56:07 PM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683989634 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.1683989634
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.1203405647
Short name T150
Test name
Test status
Simulation time 11356127293 ps
CPU time 7.3 seconds
Started Oct 15 12:55:48 PM UTC 24
Finished Oct 15 12:56:09 PM UTC 24
Peak memory 212940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1203405647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmg
r_stress_all_with_rand_reset.1203405647
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup.1869436664
Short name T728
Test name
Test status
Simulation time 46609976 ps
CPU time 0.64 seconds
Started Oct 15 12:55:44 PM UTC 24
Finished Oct 15 12:55:47 PM UTC 24
Peak memory 208828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869436664 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.1869436664
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup_reset.339457279
Short name T667
Test name
Test status
Simulation time 323659895 ps
CPU time 1.16 seconds
Started Oct 15 12:55:44 PM UTC 24
Finished Oct 15 12:55:48 PM UTC 24
Peak memory 211116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339457279 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.339457279
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/36.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_aborted_low_power.2972996876
Short name T749
Test name
Test status
Simulation time 54820491 ps
CPU time 0.72 seconds
Started Oct 15 12:55:49 PM UTC 24
Finished Oct 15 12:55:52 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972996876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.2972996876
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_disable_rom_integrity_check.1767544693
Short name T784
Test name
Test status
Simulation time 58136076 ps
CPU time 0.87 seconds
Started Oct 15 12:55:50 PM UTC 24
Finished Oct 15 12:56:03 PM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767544693 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disable_rom_integrity_check.1767544693
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.839540313
Short name T780
Test name
Test status
Simulation time 30746915 ps
CPU time 0.59 seconds
Started Oct 15 12:55:49 PM UTC 24
Finished Oct 15 12:56:02 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839540313 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_malfunc.839540313
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_escalation_timeout.1367693941
Short name T790
Test name
Test status
Simulation time 200018348 ps
CPU time 1.14 seconds
Started Oct 15 12:55:50 PM UTC 24
Finished Oct 15 12:56:03 PM UTC 24
Peak memory 209240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367693941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.1367693941
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_glitch.3087211850
Short name T744
Test name
Test status
Simulation time 35263588 ps
CPU time 0.61 seconds
Started Oct 15 12:55:50 PM UTC 24
Finished Oct 15 12:55:51 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087211850 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.3087211850
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_global_esc.3200404937
Short name T779
Test name
Test status
Simulation time 27600803 ps
CPU time 0.58 seconds
Started Oct 15 12:55:50 PM UTC 24
Finished Oct 15 12:56:02 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200404937 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.3200404937
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_invalid.4205475650
Short name T745
Test name
Test status
Simulation time 137951359 ps
CPU time 0.61 seconds
Started Oct 15 12:55:50 PM UTC 24
Finished Oct 15 12:55:51 PM UTC 24
Peak memory 212968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205475650 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invalid.4205475650
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_wakeup_race.3771826052
Short name T748
Test name
Test status
Simulation time 228023166 ps
CPU time 0.83 seconds
Started Oct 15 12:55:49 PM UTC 24
Finished Oct 15 12:55:52 PM UTC 24
Peak memory 208840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771826052 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_wakeup_race.3771826052
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset.210105866
Short name T759
Test name
Test status
Simulation time 64128907 ps
CPU time 0.87 seconds
Started Oct 15 12:55:48 PM UTC 24
Finished Oct 15 12:55:57 PM UTC 24
Peak memory 211200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210105866 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.210105866
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset_invalid.2735115639
Short name T746
Test name
Test status
Simulation time 203921117 ps
CPU time 0.8 seconds
Started Oct 15 12:55:50 PM UTC 24
Finished Oct 15 12:55:51 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735115639 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.2735115639
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.3556844111
Short name T791
Test name
Test status
Simulation time 260609396 ps
CPU time 1.22 seconds
Started Oct 15 12:55:49 PM UTC 24
Finished Oct 15 12:56:03 PM UTC 24
Peak memory 210352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556844111 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_ctrl_config_regwen.3556844111
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2716415942
Short name T753
Test name
Test status
Simulation time 811179807 ps
CPU time 2.63 seconds
Started Oct 15 12:55:49 PM UTC 24
Finished Oct 15 12:55:54 PM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716415942 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2716415942
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2509151659
Short name T752
Test name
Test status
Simulation time 991711299 ps
CPU time 2.28 seconds
Started Oct 15 12:55:49 PM UTC 24
Finished Oct 15 12:55:54 PM UTC 24
Peak memory 212304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509151659 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2509151659
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.3536030453
Short name T751
Test name
Test status
Simulation time 76345021 ps
CPU time 0.95 seconds
Started Oct 15 12:55:49 PM UTC 24
Finished Oct 15 12:55:52 PM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536030453 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_mubi.3536030453
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_smoke.431515376
Short name T794
Test name
Test status
Simulation time 29383181 ps
CPU time 0.88 seconds
Started Oct 15 12:55:48 PM UTC 24
Finished Oct 15 12:56:03 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431515376 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.431515376
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all.2579202707
Short name T754
Test name
Test status
Simulation time 2270168040 ps
CPU time 5.03 seconds
Started Oct 15 12:55:50 PM UTC 24
Finished Oct 15 12:55:56 PM UTC 24
Peak memory 212744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579202707 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.2579202707
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.1835985984
Short name T149
Test name
Test status
Simulation time 26825825040 ps
CPU time 13 seconds
Started Oct 15 12:55:50 PM UTC 24
Finished Oct 15 12:56:04 PM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1835985984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmg
r_stress_all_with_rand_reset.1835985984
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup.14271735
Short name T747
Test name
Test status
Simulation time 85737814 ps
CPU time 0.71 seconds
Started Oct 15 12:55:49 PM UTC 24
Finished Oct 15 12:55:52 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14271735 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.14271735
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup_reset.279681902
Short name T750
Test name
Test status
Simulation time 222538123 ps
CPU time 1.1 seconds
Started Oct 15 12:55:49 PM UTC 24
Finished Oct 15 12:55:52 PM UTC 24
Peak memory 210416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279681902 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.279681902
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/37.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_aborted_low_power.952505137
Short name T763
Test name
Test status
Simulation time 55386332 ps
CPU time 0.72 seconds
Started Oct 15 12:55:53 PM UTC 24
Finished Oct 15 12:55:58 PM UTC 24
Peak memory 208984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952505137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.952505137
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_disable_rom_integrity_check.1421543028
Short name T769
Test name
Test status
Simulation time 51254473 ps
CPU time 0.78 seconds
Started Oct 15 12:55:58 PM UTC 24
Finished Oct 15 12:56:00 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421543028 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disable_rom_integrity_check.1421543028
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.2287064551
Short name T761
Test name
Test status
Simulation time 40651238 ps
CPU time 0.67 seconds
Started Oct 15 12:55:54 PM UTC 24
Finished Oct 15 12:55:57 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287064551 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst_malfunc.2287064551
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_escalation_timeout.3599165529
Short name T771
Test name
Test status
Simulation time 212117813 ps
CPU time 0.87 seconds
Started Oct 15 12:55:58 PM UTC 24
Finished Oct 15 12:56:00 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599165529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.3599165529
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_glitch.3102395736
Short name T767
Test name
Test status
Simulation time 135051183 ps
CPU time 0.63 seconds
Started Oct 15 12:55:58 PM UTC 24
Finished Oct 15 12:55:59 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102395736 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.3102395736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_global_esc.381892704
Short name T764
Test name
Test status
Simulation time 114043104 ps
CPU time 0.62 seconds
Started Oct 15 12:55:56 PM UTC 24
Finished Oct 15 12:55:58 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381892704 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.381892704
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_invalid.647456626
Short name T783
Test name
Test status
Simulation time 38708702 ps
CPU time 0.73 seconds
Started Oct 15 12:55:58 PM UTC 24
Finished Oct 15 12:56:03 PM UTC 24
Peak memory 210836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647456626 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invalid.647456626
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_wakeup_race.273886412
Short name T760
Test name
Test status
Simulation time 245388258 ps
CPU time 0.76 seconds
Started Oct 15 12:55:52 PM UTC 24
Finished Oct 15 12:55:57 PM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273886412 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_wakeup_race.273886412
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset.3714994549
Short name T758
Test name
Test status
Simulation time 111185292 ps
CPU time 0.74 seconds
Started Oct 15 12:55:52 PM UTC 24
Finished Oct 15 12:55:57 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714994549 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3714994549
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset_invalid.3436370517
Short name T787
Test name
Test status
Simulation time 167206328 ps
CPU time 0.93 seconds
Started Oct 15 12:55:58 PM UTC 24
Finished Oct 15 12:56:03 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436370517 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.3436370517
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.2743734711
Short name T762
Test name
Test status
Simulation time 197865892 ps
CPU time 0.67 seconds
Started Oct 15 12:55:55 PM UTC 24
Finished Oct 15 12:55:57 PM UTC 24
Peak memory 210412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743734711 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_ctrl_config_regwen.2743734711
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2157174843
Short name T770
Test name
Test status
Simulation time 1062041526 ps
CPU time 2.22 seconds
Started Oct 15 12:55:53 PM UTC 24
Finished Oct 15 12:56:00 PM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157174843 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2157174843
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1612011623
Short name T768
Test name
Test status
Simulation time 1089914603 ps
CPU time 2.1 seconds
Started Oct 15 12:55:53 PM UTC 24
Finished Oct 15 12:55:59 PM UTC 24
Peak memory 212536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612011623 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1612011623
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.2679909447
Short name T766
Test name
Test status
Simulation time 50339861 ps
CPU time 0.84 seconds
Started Oct 15 12:55:53 PM UTC 24
Finished Oct 15 12:55:58 PM UTC 24
Peak memory 210628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679909447 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_mubi.2679909447
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_smoke.3353246235
Short name T788
Test name
Test status
Simulation time 38482281 ps
CPU time 0.74 seconds
Started Oct 15 12:55:51 PM UTC 24
Finished Oct 15 12:56:03 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353246235 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.3353246235
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.4008978958
Short name T777
Test name
Test status
Simulation time 1588957397 ps
CPU time 2.78 seconds
Started Oct 15 12:55:58 PM UTC 24
Finished Oct 15 12:56:05 PM UTC 24
Peak memory 212468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008978958 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.4008978958
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.1418589207
Short name T71
Test name
Test status
Simulation time 5346957381 ps
CPU time 15.85 seconds
Started Oct 15 12:55:58 PM UTC 24
Finished Oct 15 12:56:18 PM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1418589207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmg
r_stress_all_with_rand_reset.1418589207
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup.4147497136
Short name T757
Test name
Test status
Simulation time 283460296 ps
CPU time 0.65 seconds
Started Oct 15 12:55:52 PM UTC 24
Finished Oct 15 12:55:57 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147497136 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.4147497136
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup_reset.3683194020
Short name T765
Test name
Test status
Simulation time 192980286 ps
CPU time 0.93 seconds
Started Oct 15 12:55:53 PM UTC 24
Finished Oct 15 12:55:58 PM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683194020 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.3683194020
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/38.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_aborted_low_power.2307544016
Short name T775
Test name
Test status
Simulation time 33542242 ps
CPU time 0.68 seconds
Started Oct 15 12:56:00 PM UTC 24
Finished Oct 15 12:56:02 PM UTC 24
Peak memory 211192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307544016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.2307544016
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_disable_rom_integrity_check.1929496000
Short name T802
Test name
Test status
Simulation time 61551036 ps
CPU time 0.99 seconds
Started Oct 15 12:56:03 PM UTC 24
Finished Oct 15 12:56:05 PM UTC 24
Peak memory 210224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929496000 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disable_rom_integrity_check.1929496000
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.4060517581
Short name T773
Test name
Test status
Simulation time 33181750 ps
CPU time 0.55 seconds
Started Oct 15 12:56:00 PM UTC 24
Finished Oct 15 12:56:02 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060517581 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_malfunc.4060517581
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_escalation_timeout.2860455073
Short name T803
Test name
Test status
Simulation time 204298449 ps
CPU time 1.25 seconds
Started Oct 15 12:56:03 PM UTC 24
Finished Oct 15 12:56:05 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860455073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.2860455073
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_glitch.2866028952
Short name T799
Test name
Test status
Simulation time 55887100 ps
CPU time 0.7 seconds
Started Oct 15 12:56:03 PM UTC 24
Finished Oct 15 12:56:04 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866028952 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.2866028952
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_global_esc.3325361242
Short name T800
Test name
Test status
Simulation time 44444237 ps
CPU time 0.78 seconds
Started Oct 15 12:56:03 PM UTC 24
Finished Oct 15 12:56:04 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325361242 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.3325361242
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_invalid.3387583977
Short name T785
Test name
Test status
Simulation time 43962722 ps
CPU time 0.99 seconds
Started Oct 15 12:56:03 PM UTC 24
Finished Oct 15 12:56:05 PM UTC 24
Peak memory 212968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387583977 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_invalid.3387583977
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_wakeup_race.705935808
Short name T776
Test name
Test status
Simulation time 316243868 ps
CPU time 0.86 seconds
Started Oct 15 12:55:59 PM UTC 24
Finished Oct 15 12:56:02 PM UTC 24
Peak memory 210084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705935808 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_wakeup_race.705935808
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset.19631559
Short name T772
Test name
Test status
Simulation time 35740682 ps
CPU time 0.62 seconds
Started Oct 15 12:55:59 PM UTC 24
Finished Oct 15 12:56:02 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19631559 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.19631559
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.812275691
Short name T756
Test name
Test status
Simulation time 100525048 ps
CPU time 1.02 seconds
Started Oct 15 12:56:03 PM UTC 24
Finished Oct 15 12:56:05 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812275691 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.812275691
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.2376187392
Short name T798
Test name
Test status
Simulation time 360591011 ps
CPU time 1.02 seconds
Started Oct 15 12:56:01 PM UTC 24
Finished Oct 15 12:56:04 PM UTC 24
Peak memory 210352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376187392 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_ctrl_config_regwen.2376187392
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3792905004
Short name T793
Test name
Test status
Simulation time 2015428756 ps
CPU time 1.77 seconds
Started Oct 15 12:56:00 PM UTC 24
Finished Oct 15 12:56:03 PM UTC 24
Peak memory 212688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792905004 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3792905004
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.207424323
Short name T797
Test name
Test status
Simulation time 2864018886 ps
CPU time 2.01 seconds
Started Oct 15 12:56:00 PM UTC 24
Finished Oct 15 12:56:03 PM UTC 24
Peak memory 212480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207424323 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.207424323
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.598347812
Short name T778
Test name
Test status
Simulation time 70051534 ps
CPU time 0.87 seconds
Started Oct 15 12:56:00 PM UTC 24
Finished Oct 15 12:56:02 PM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598347812 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_mubi.598347812
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.974463183
Short name T795
Test name
Test status
Simulation time 63135766 ps
CPU time 0.9 seconds
Started Oct 15 12:55:58 PM UTC 24
Finished Oct 15 12:56:03 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974463183 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.974463183
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.3546475082
Short name T823
Test name
Test status
Simulation time 4879306537 ps
CPU time 4.15 seconds
Started Oct 15 12:56:03 PM UTC 24
Finished Oct 15 12:56:08 PM UTC 24
Peak memory 212664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546475082 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.3546475082
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.3790997877
Short name T774
Test name
Test status
Simulation time 113533719 ps
CPU time 0.81 seconds
Started Oct 15 12:55:59 PM UTC 24
Finished Oct 15 12:56:02 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790997877 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.3790997877
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup_reset.3313554455
Short name T781
Test name
Test status
Simulation time 281474145 ps
CPU time 1.3 seconds
Started Oct 15 12:55:59 PM UTC 24
Finished Oct 15 12:56:02 PM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313554455 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.3313554455
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/39.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.1732170135
Short name T85
Test name
Test status
Simulation time 50559920 ps
CPU time 0.99 seconds
Started Oct 15 12:53:13 PM UTC 24
Finished Oct 15 12:53:15 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732170135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.1732170135
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.4058756705
Short name T159
Test name
Test status
Simulation time 147075674 ps
CPU time 1.08 seconds
Started Oct 15 12:53:16 PM UTC 24
Finished Oct 15 12:53:18 PM UTC 24
Peak memory 211312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058756705 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disable_rom_integrity_check.4058756705
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1437128737
Short name T89
Test name
Test status
Simulation time 38160584 ps
CPU time 0.91 seconds
Started Oct 15 12:53:14 PM UTC 24
Finished Oct 15 12:53:16 PM UTC 24
Peak memory 209180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437128737 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_malfunc.1437128737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.313462808
Short name T153
Test name
Test status
Simulation time 555090584 ps
CPU time 1.51 seconds
Started Oct 15 12:53:16 PM UTC 24
Finished Oct 15 12:53:18 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313462808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.313462808
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.976492005
Short name T200
Test name
Test status
Simulation time 78607557 ps
CPU time 0.94 seconds
Started Oct 15 12:53:16 PM UTC 24
Finished Oct 15 12:53:18 PM UTC 24
Peak memory 208932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976492005 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.976492005
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.3211495017
Short name T197
Test name
Test status
Simulation time 100489492 ps
CPU time 0.96 seconds
Started Oct 15 12:53:14 PM UTC 24
Finished Oct 15 12:53:16 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211495017 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.3211495017
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.1147130157
Short name T201
Test name
Test status
Simulation time 75993369 ps
CPU time 1.04 seconds
Started Oct 15 12:53:16 PM UTC 24
Finished Oct 15 12:53:18 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147130157 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invalid.1147130157
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.467446467
Short name T87
Test name
Test status
Simulation time 150171452 ps
CPU time 1.37 seconds
Started Oct 15 12:53:13 PM UTC 24
Finished Oct 15 12:53:15 PM UTC 24
Peak memory 209180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467446467 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wakeup_race.467446467
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.343258463
Short name T84
Test name
Test status
Simulation time 152195727 ps
CPU time 1.19 seconds
Started Oct 15 12:53:13 PM UTC 24
Finished Oct 15 12:53:15 PM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343258463 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.343258463
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.1965690171
Short name T203
Test name
Test status
Simulation time 108924493 ps
CPU time 1.56 seconds
Started Oct 15 12:53:16 PM UTC 24
Finished Oct 15 12:53:18 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965690171 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1965690171
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.3238151963
Short name T30
Test name
Test status
Simulation time 998710515 ps
CPU time 1.73 seconds
Started Oct 15 12:53:16 PM UTC 24
Finished Oct 15 12:53:19 PM UTC 24
Peak memory 238524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238151963 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.3238151963
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.520035629
Short name T199
Test name
Test status
Simulation time 143109248 ps
CPU time 1.66 seconds
Started Oct 15 12:53:14 PM UTC 24
Finished Oct 15 12:53:17 PM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520035629 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_ctrl_config_regwen.520035629
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1264869363
Short name T165
Test name
Test status
Simulation time 1173104354 ps
CPU time 2.63 seconds
Started Oct 15 12:53:13 PM UTC 24
Finished Oct 15 12:53:16 PM UTC 24
Peak memory 211728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264869363 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.1264869363
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1551228301
Short name T202
Test name
Test status
Simulation time 801770567 ps
CPU time 4.15 seconds
Started Oct 15 12:53:13 PM UTC 24
Finished Oct 15 12:53:18 PM UTC 24
Peak memory 212608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551228301 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.1551228301
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.3026428171
Short name T198
Test name
Test status
Simulation time 229517400 ps
CPU time 1.36 seconds
Started Oct 15 12:53:14 PM UTC 24
Finished Oct 15 12:53:16 PM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026428171 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_mubi.3026428171
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.2959179877
Short name T82
Test name
Test status
Simulation time 29760640 ps
CPU time 1.04 seconds
Started Oct 15 12:53:11 PM UTC 24
Finished Oct 15 12:53:13 PM UTC 24
Peak memory 208992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959179877 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.2959179877
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.1274897944
Short name T212
Test name
Test status
Simulation time 644840797 ps
CPU time 3.48 seconds
Started Oct 15 12:53:18 PM UTC 24
Finished Oct 15 12:53:22 PM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274897944 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.1274897944
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.60256459
Short name T91
Test name
Test status
Simulation time 7119626376 ps
CPU time 11.29 seconds
Started Oct 15 12:53:16 PM UTC 24
Finished Oct 15 12:53:28 PM UTC 24
Peak memory 212984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=60256459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_s
tress_all_with_rand_reset.60256459
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.1610460601
Short name T88
Test name
Test status
Simulation time 256382591 ps
CPU time 1.53 seconds
Started Oct 15 12:53:13 PM UTC 24
Finished Oct 15 12:53:15 PM UTC 24
Peak memory 210344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610460601 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.1610460601
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.2769153178
Short name T86
Test name
Test status
Simulation time 150980021 ps
CPU time 1.22 seconds
Started Oct 15 12:53:13 PM UTC 24
Finished Oct 15 12:53:15 PM UTC 24
Peak memory 211576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769153178 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.2769153178
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/4.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.1466965453
Short name T814
Test name
Test status
Simulation time 42981417 ps
CPU time 1.32 seconds
Started Oct 15 12:56:04 PM UTC 24
Finished Oct 15 12:56:07 PM UTC 24
Peak memory 211144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466965453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.1466965453
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.981927287
Short name T813
Test name
Test status
Simulation time 65974290 ps
CPU time 1.04 seconds
Started Oct 15 12:56:05 PM UTC 24
Finished Oct 15 12:56:07 PM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981927287 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disable_rom_integrity_check.981927287
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.2323221888
Short name T807
Test name
Test status
Simulation time 34710336 ps
CPU time 0.76 seconds
Started Oct 15 12:56:04 PM UTC 24
Finished Oct 15 12:56:06 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323221888 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_malfunc.2323221888
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.936724783
Short name T815
Test name
Test status
Simulation time 202256436 ps
CPU time 1.11 seconds
Started Oct 15 12:56:05 PM UTC 24
Finished Oct 15 12:56:07 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936724783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.936724783
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.2649890786
Short name T809
Test name
Test status
Simulation time 39054301 ps
CPU time 0.92 seconds
Started Oct 15 12:56:05 PM UTC 24
Finished Oct 15 12:56:07 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649890786 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.2649890786
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.1064253654
Short name T808
Test name
Test status
Simulation time 88772692 ps
CPU time 0.79 seconds
Started Oct 15 12:56:04 PM UTC 24
Finished Oct 15 12:56:06 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064253654 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.1064253654
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_invalid.293728743
Short name T811
Test name
Test status
Simulation time 45139681 ps
CPU time 0.79 seconds
Started Oct 15 12:56:05 PM UTC 24
Finished Oct 15 12:56:07 PM UTC 24
Peak memory 212904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293728743 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_invalid.293728743
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.2923610356
Short name T806
Test name
Test status
Simulation time 333099134 ps
CPU time 1 seconds
Started Oct 15 12:56:04 PM UTC 24
Finished Oct 15 12:56:06 PM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923610356 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_wakeup_race.2923610356
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.112099245
Short name T786
Test name
Test status
Simulation time 274788661 ps
CPU time 0.9 seconds
Started Oct 15 12:56:03 PM UTC 24
Finished Oct 15 12:56:05 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112099245 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.112099245
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.14790901
Short name T816
Test name
Test status
Simulation time 100432268 ps
CPU time 1.22 seconds
Started Oct 15 12:56:05 PM UTC 24
Finished Oct 15 12:56:07 PM UTC 24
Peak memory 221256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14790901 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.14790901
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.4217807899
Short name T812
Test name
Test status
Simulation time 289170917 ps
CPU time 1.22 seconds
Started Oct 15 12:56:04 PM UTC 24
Finished Oct 15 12:56:07 PM UTC 24
Peak memory 210616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217807899 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_ctrl_config_regwen.4217807899
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.896796072
Short name T827
Test name
Test status
Simulation time 802470704 ps
CPU time 3.21 seconds
Started Oct 15 12:56:04 PM UTC 24
Finished Oct 15 12:56:09 PM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896796072 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.896796072
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.453207813
Short name T819
Test name
Test status
Simulation time 1258471710 ps
CPU time 2.23 seconds
Started Oct 15 12:56:04 PM UTC 24
Finished Oct 15 12:56:08 PM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453207813 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.453207813
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.4003240887
Short name T810
Test name
Test status
Simulation time 134312977 ps
CPU time 1.16 seconds
Started Oct 15 12:56:04 PM UTC 24
Finished Oct 15 12:56:07 PM UTC 24
Peak memory 210620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003240887 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig_mubi.4003240887
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.1645090049
Short name T801
Test name
Test status
Simulation time 49132718 ps
CPU time 0.79 seconds
Started Oct 15 12:56:03 PM UTC 24
Finished Oct 15 12:56:05 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645090049 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.1645090049
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.722344287
Short name T828
Test name
Test status
Simulation time 501640347 ps
CPU time 2.51 seconds
Started Oct 15 12:56:06 PM UTC 24
Finished Oct 15 12:56:10 PM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722344287 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.722344287
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.2539513010
Short name T45
Test name
Test status
Simulation time 4401233363 ps
CPU time 11.43 seconds
Started Oct 15 12:56:05 PM UTC 24
Finished Oct 15 12:56:17 PM UTC 24
Peak memory 212940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2539513010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmg
r_stress_all_with_rand_reset.2539513010
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.2912411446
Short name T805
Test name
Test status
Simulation time 70245484 ps
CPU time 0.92 seconds
Started Oct 15 12:56:04 PM UTC 24
Finished Oct 15 12:56:06 PM UTC 24
Peak memory 209076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912411446 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.2912411446
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.1004830736
Short name T804
Test name
Test status
Simulation time 50972820 ps
CPU time 0.74 seconds
Started Oct 15 12:56:04 PM UTC 24
Finished Oct 15 12:56:06 PM UTC 24
Peak memory 210288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004830736 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.1004830736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/40.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.538026814
Short name T821
Test name
Test status
Simulation time 36708238 ps
CPU time 0.86 seconds
Started Oct 15 12:56:06 PM UTC 24
Finished Oct 15 12:56:08 PM UTC 24
Peak memory 211160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538026814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.538026814
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.2155418231
Short name T848
Test name
Test status
Simulation time 51166680 ps
CPU time 0.99 seconds
Started Oct 15 12:56:08 PM UTC 24
Finished Oct 15 12:56:13 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155418231 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disable_rom_integrity_check.2155418231
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.1874966483
Short name T842
Test name
Test status
Simulation time 38362391 ps
CPU time 0.89 seconds
Started Oct 15 12:56:08 PM UTC 24
Finished Oct 15 12:56:13 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874966483 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_malfunc.1874966483
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.518753039
Short name T849
Test name
Test status
Simulation time 490413369 ps
CPU time 1.16 seconds
Started Oct 15 12:56:08 PM UTC 24
Finished Oct 15 12:56:13 PM UTC 24
Peak memory 209184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518753039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.518753039
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.2694934305
Short name T839
Test name
Test status
Simulation time 26189781 ps
CPU time 0.68 seconds
Started Oct 15 12:56:08 PM UTC 24
Finished Oct 15 12:56:13 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694934305 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.2694934305
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.4124256913
Short name T845
Test name
Test status
Simulation time 95171244 ps
CPU time 0.9 seconds
Started Oct 15 12:56:08 PM UTC 24
Finished Oct 15 12:56:13 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124256913 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.4124256913
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_invalid.2870212894
Short name T846
Test name
Test status
Simulation time 56055754 ps
CPU time 0.8 seconds
Started Oct 15 12:56:08 PM UTC 24
Finished Oct 15 12:56:13 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870212894 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_invalid.2870212894
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.1710396632
Short name T826
Test name
Test status
Simulation time 303381819 ps
CPU time 1.37 seconds
Started Oct 15 12:56:06 PM UTC 24
Finished Oct 15 12:56:09 PM UTC 24
Peak memory 210096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710396632 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_wakeup_race.1710396632
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.2396690632
Short name T822
Test name
Test status
Simulation time 205901385 ps
CPU time 1.06 seconds
Started Oct 15 12:56:06 PM UTC 24
Finished Oct 15 12:56:08 PM UTC 24
Peak memory 210732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396690632 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.2396690632
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.208852335
Short name T850
Test name
Test status
Simulation time 157626777 ps
CPU time 1.02 seconds
Started Oct 15 12:56:08 PM UTC 24
Finished Oct 15 12:56:13 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208852335 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.208852335
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.2070038003
Short name T851
Test name
Test status
Simulation time 252853259 ps
CPU time 1.14 seconds
Started Oct 15 12:56:08 PM UTC 24
Finished Oct 15 12:56:13 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070038003 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_ctrl_config_regwen.2070038003
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2029006808
Short name T829
Test name
Test status
Simulation time 1061450723 ps
CPU time 2.33 seconds
Started Oct 15 12:56:06 PM UTC 24
Finished Oct 15 12:56:10 PM UTC 24
Peak memory 212432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029006808 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2029006808
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2432997040
Short name T830
Test name
Test status
Simulation time 854978393 ps
CPU time 3.37 seconds
Started Oct 15 12:56:06 PM UTC 24
Finished Oct 15 12:56:11 PM UTC 24
Peak memory 212404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432997040 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2432997040
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3374554019
Short name T831
Test name
Test status
Simulation time 54421423 ps
CPU time 0.86 seconds
Started Oct 15 12:56:06 PM UTC 24
Finished Oct 15 12:56:11 PM UTC 24
Peak memory 209812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374554019 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3374554019
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.3381007571
Short name T820
Test name
Test status
Simulation time 31981138 ps
CPU time 1.03 seconds
Started Oct 15 12:56:06 PM UTC 24
Finished Oct 15 12:56:08 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381007571 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.3381007571
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.1845658583
Short name T890
Test name
Test status
Simulation time 1389889589 ps
CPU time 3.72 seconds
Started Oct 15 12:56:08 PM UTC 24
Finished Oct 15 12:56:26 PM UTC 24
Peak memory 212272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845658583 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.1845658583
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.456949130
Short name T907
Test name
Test status
Simulation time 4507055405 ps
CPU time 9.12 seconds
Started Oct 15 12:56:08 PM UTC 24
Finished Oct 15 12:56:31 PM UTC 24
Peak memory 213004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=456949130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr
_stress_all_with_rand_reset.456949130
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.4193090770
Short name T824
Test name
Test status
Simulation time 193409581 ps
CPU time 1.09 seconds
Started Oct 15 12:56:06 PM UTC 24
Finished Oct 15 12:56:08 PM UTC 24
Peak memory 210084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193090770 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.4193090770
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.2119637782
Short name T825
Test name
Test status
Simulation time 322457172 ps
CPU time 1.28 seconds
Started Oct 15 12:56:06 PM UTC 24
Finished Oct 15 12:56:08 PM UTC 24
Peak memory 211144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119637782 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.2119637782
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/41.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.2548838610
Short name T836
Test name
Test status
Simulation time 23188504 ps
CPU time 0.87 seconds
Started Oct 15 12:56:09 PM UTC 24
Finished Oct 15 12:56:12 PM UTC 24
Peak memory 209920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548838610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.2548838610
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.1608553261
Short name T843
Test name
Test status
Simulation time 72397766 ps
CPU time 0.81 seconds
Started Oct 15 12:56:11 PM UTC 24
Finished Oct 15 12:56:13 PM UTC 24
Peak memory 208864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608553261 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disable_rom_integrity_check.1608553261
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.1386821357
Short name T835
Test name
Test status
Simulation time 29000570 ps
CPU time 0.57 seconds
Started Oct 15 12:56:09 PM UTC 24
Finished Oct 15 12:56:12 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386821357 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_malfunc.1386821357
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.387444395
Short name T838
Test name
Test status
Simulation time 361374594 ps
CPU time 0.77 seconds
Started Oct 15 12:56:10 PM UTC 24
Finished Oct 15 12:56:12 PM UTC 24
Peak memory 209184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387444395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.387444395
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.1431322017
Short name T837
Test name
Test status
Simulation time 115773185 ps
CPU time 0.55 seconds
Started Oct 15 12:56:11 PM UTC 24
Finished Oct 15 12:56:12 PM UTC 24
Peak memory 208720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431322017 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.1431322017
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.4257040844
Short name T840
Test name
Test status
Simulation time 134084296 ps
CPU time 0.77 seconds
Started Oct 15 12:56:10 PM UTC 24
Finished Oct 15 12:56:13 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257040844 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.4257040844
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_invalid.3026943852
Short name T863
Test name
Test status
Simulation time 45481574 ps
CPU time 0.77 seconds
Started Oct 15 12:56:12 PM UTC 24
Finished Oct 15 12:56:17 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026943852 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invalid.3026943852
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.1349660788
Short name T855
Test name
Test status
Simulation time 161377987 ps
CPU time 0.75 seconds
Started Oct 15 12:56:08 PM UTC 24
Finished Oct 15 12:56:16 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349660788 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wakeup_race.1349660788
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.1101376310
Short name T885
Test name
Test status
Simulation time 54425054 ps
CPU time 0.78 seconds
Started Oct 15 12:56:08 PM UTC 24
Finished Oct 15 12:56:23 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101376310 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.1101376310
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.1489910989
Short name T847
Test name
Test status
Simulation time 171107620 ps
CPU time 0.91 seconds
Started Oct 15 12:56:11 PM UTC 24
Finished Oct 15 12:56:13 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489910989 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.1489910989
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.3963192725
Short name T841
Test name
Test status
Simulation time 332592570 ps
CPU time 0.93 seconds
Started Oct 15 12:56:10 PM UTC 24
Finished Oct 15 12:56:13 PM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963192725 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_ctrl_config_regwen.3963192725
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.183593710
Short name T854
Test name
Test status
Simulation time 1436934769 ps
CPU time 2.32 seconds
Started Oct 15 12:56:09 PM UTC 24
Finished Oct 15 12:56:14 PM UTC 24
Peak memory 212436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183593710 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.183593710
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.113423497
Short name T853
Test name
Test status
Simulation time 980027058 ps
CPU time 2.14 seconds
Started Oct 15 12:56:09 PM UTC 24
Finished Oct 15 12:56:14 PM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113423497 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.113423497
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.820447856
Short name T844
Test name
Test status
Simulation time 100622898 ps
CPU time 1.01 seconds
Started Oct 15 12:56:09 PM UTC 24
Finished Oct 15 12:56:13 PM UTC 24
Peak memory 210424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820447856 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_mubi.820447856
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.4207288707
Short name T856
Test name
Test status
Simulation time 31697923 ps
CPU time 0.78 seconds
Started Oct 15 12:56:08 PM UTC 24
Finished Oct 15 12:56:16 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207288707 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.4207288707
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.880771692
Short name T876
Test name
Test status
Simulation time 173102800 ps
CPU time 1.34 seconds
Started Oct 15 12:56:13 PM UTC 24
Finished Oct 15 12:56:22 PM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880771692 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.880771692
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.1987110480
Short name T896
Test name
Test status
Simulation time 8956758925 ps
CPU time 10.59 seconds
Started Oct 15 12:56:12 PM UTC 24
Finished Oct 15 12:56:27 PM UTC 24
Peak memory 212748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1987110480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmg
r_stress_all_with_rand_reset.1987110480
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.3769325190
Short name T834
Test name
Test status
Simulation time 34779055 ps
CPU time 0.77 seconds
Started Oct 15 12:56:09 PM UTC 24
Finished Oct 15 12:56:12 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769325190 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.3769325190
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.2893670387
Short name T833
Test name
Test status
Simulation time 37158710 ps
CPU time 0.63 seconds
Started Oct 15 12:56:09 PM UTC 24
Finished Oct 15 12:56:12 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893670387 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.2893670387
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/42.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.2478819812
Short name T852
Test name
Test status
Simulation time 65014977 ps
CPU time 0.89 seconds
Started Oct 15 12:56:13 PM UTC 24
Finished Oct 15 12:56:21 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478819812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.2478819812
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.4272678985
Short name T858
Test name
Test status
Simulation time 92881281 ps
CPU time 0.75 seconds
Started Oct 15 12:56:15 PM UTC 24
Finished Oct 15 12:56:17 PM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272678985 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disable_rom_integrity_check.4272678985
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.1192787480
Short name T871
Test name
Test status
Simulation time 29824496 ps
CPU time 0.7 seconds
Started Oct 15 12:56:13 PM UTC 24
Finished Oct 15 12:56:21 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192787480 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_malfunc.1192787480
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.2682680633
Short name T818
Test name
Test status
Simulation time 250347469 ps
CPU time 0.81 seconds
Started Oct 15 12:56:14 PM UTC 24
Finished Oct 15 12:56:22 PM UTC 24
Peak memory 207596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682680633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.2682680633
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.4234170976
Short name T857
Test name
Test status
Simulation time 55691902 ps
CPU time 0.63 seconds
Started Oct 15 12:56:15 PM UTC 24
Finished Oct 15 12:56:17 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234170976 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.4234170976
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.827002068
Short name T872
Test name
Test status
Simulation time 25082809 ps
CPU time 0.69 seconds
Started Oct 15 12:56:14 PM UTC 24
Finished Oct 15 12:56:22 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827002068 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.827002068
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_invalid.2506308696
Short name T859
Test name
Test status
Simulation time 42802247 ps
CPU time 0.78 seconds
Started Oct 15 12:56:15 PM UTC 24
Finished Oct 15 12:56:17 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506308696 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invalid.2506308696
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.307348375
Short name T870
Test name
Test status
Simulation time 111770780 ps
CPU time 0.78 seconds
Started Oct 15 12:56:13 PM UTC 24
Finished Oct 15 12:56:21 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307348375 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_wakeup_race.307348375
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.888937450
Short name T864
Test name
Test status
Simulation time 69554639 ps
CPU time 1.01 seconds
Started Oct 15 12:56:13 PM UTC 24
Finished Oct 15 12:56:18 PM UTC 24
Peak memory 210732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888937450 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.888937450
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.3418532698
Short name T862
Test name
Test status
Simulation time 113134217 ps
CPU time 0.86 seconds
Started Oct 15 12:56:15 PM UTC 24
Finished Oct 15 12:56:17 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418532698 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.3418532698
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.4263845957
Short name T877
Test name
Test status
Simulation time 213513567 ps
CPU time 1.04 seconds
Started Oct 15 12:56:14 PM UTC 24
Finished Oct 15 12:56:22 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263845957 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_ctrl_config_regwen.4263845957
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1637550756
Short name T884
Test name
Test status
Simulation time 1219652732 ps
CPU time 2.14 seconds
Started Oct 15 12:56:13 PM UTC 24
Finished Oct 15 12:56:23 PM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637550756 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1637550756
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2711722861
Short name T887
Test name
Test status
Simulation time 1277490246 ps
CPU time 2.34 seconds
Started Oct 15 12:56:13 PM UTC 24
Finished Oct 15 12:56:23 PM UTC 24
Peak memory 212752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711722861 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2711722861
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.892962561
Short name T875
Test name
Test status
Simulation time 594048588 ps
CPU time 0.95 seconds
Started Oct 15 12:56:13 PM UTC 24
Finished Oct 15 12:56:22 PM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892962561 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig_mubi.892962561
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.3413335865
Short name T866
Test name
Test status
Simulation time 62964379 ps
CPU time 0.61 seconds
Started Oct 15 12:56:13 PM UTC 24
Finished Oct 15 12:56:21 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413335865 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.3413335865
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.481032808
Short name T865
Test name
Test status
Simulation time 1361343029 ps
CPU time 3.33 seconds
Started Oct 15 12:56:15 PM UTC 24
Finished Oct 15 12:56:19 PM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481032808 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.481032808
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.4139683948
Short name T904
Test name
Test status
Simulation time 8048905980 ps
CPU time 10.81 seconds
Started Oct 15 12:56:15 PM UTC 24
Finished Oct 15 12:56:27 PM UTC 24
Peak memory 212940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4139683948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmg
r_stress_all_with_rand_reset.4139683948
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.495763559
Short name T868
Test name
Test status
Simulation time 178650914 ps
CPU time 0.69 seconds
Started Oct 15 12:56:13 PM UTC 24
Finished Oct 15 12:56:21 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495763559 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.495763559
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.1093967379
Short name T867
Test name
Test status
Simulation time 37538748 ps
CPU time 0.69 seconds
Started Oct 15 12:56:13 PM UTC 24
Finished Oct 15 12:56:21 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093967379 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.1093967379
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/43.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.1996121983
Short name T882
Test name
Test status
Simulation time 69190563 ps
CPU time 0.84 seconds
Started Oct 15 12:56:17 PM UTC 24
Finished Oct 15 12:56:22 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996121983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.1996121983
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.3422922007
Short name T873
Test name
Test status
Simulation time 70165619 ps
CPU time 0.67 seconds
Started Oct 15 12:56:20 PM UTC 24
Finished Oct 15 12:56:22 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422922007 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disable_rom_integrity_check.3422922007
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.744379165
Short name T880
Test name
Test status
Simulation time 63284478 ps
CPU time 0.57 seconds
Started Oct 15 12:56:17 PM UTC 24
Finished Oct 15 12:56:22 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744379165 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_malfunc.744379165
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.877891470
Short name T874
Test name
Test status
Simulation time 1020161130 ps
CPU time 0.78 seconds
Started Oct 15 12:56:19 PM UTC 24
Finished Oct 15 12:56:22 PM UTC 24
Peak memory 209184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877891470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.877891470
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.2113727735
Short name T869
Test name
Test status
Simulation time 60412571 ps
CPU time 0.56 seconds
Started Oct 15 12:56:19 PM UTC 24
Finished Oct 15 12:56:21 PM UTC 24
Peak memory 208468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113727735 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.2113727735
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.1089479102
Short name T832
Test name
Test status
Simulation time 48709193 ps
CPU time 0.58 seconds
Started Oct 15 12:56:19 PM UTC 24
Finished Oct 15 12:56:21 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089479102 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.1089479102
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_invalid.687169021
Short name T895
Test name
Test status
Simulation time 80784997 ps
CPU time 0.7 seconds
Started Oct 15 12:56:22 PM UTC 24
Finished Oct 15 12:56:27 PM UTC 24
Peak memory 210836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687169021 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_invalid.687169021
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.1156526404
Short name T879
Test name
Test status
Simulation time 57945040 ps
CPU time 0.92 seconds
Started Oct 15 12:56:17 PM UTC 24
Finished Oct 15 12:56:22 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156526404 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_wakeup_race.1156526404
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.4084944040
Short name T861
Test name
Test status
Simulation time 109625860 ps
CPU time 0.73 seconds
Started Oct 15 12:56:15 PM UTC 24
Finished Oct 15 12:56:17 PM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084944040 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.4084944040
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset_invalid.2401026580
Short name T905
Test name
Test status
Simulation time 113252149 ps
CPU time 1.05 seconds
Started Oct 15 12:56:22 PM UTC 24
Finished Oct 15 12:56:27 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401026580 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.2401026580
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.773565488
Short name T881
Test name
Test status
Simulation time 132280038 ps
CPU time 0.62 seconds
Started Oct 15 12:56:17 PM UTC 24
Finished Oct 15 12:56:22 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773565488 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_ctrl_config_regwen.773565488
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.423988280
Short name T888
Test name
Test status
Simulation time 920288825 ps
CPU time 2.58 seconds
Started Oct 15 12:56:17 PM UTC 24
Finished Oct 15 12:56:24 PM UTC 24
Peak memory 212308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423988280 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.423988280
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3661419274
Short name T889
Test name
Test status
Simulation time 828981908 ps
CPU time 3.31 seconds
Started Oct 15 12:56:17 PM UTC 24
Finished Oct 15 12:56:25 PM UTC 24
Peak memory 212364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661419274 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3661419274
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.3056190028
Short name T883
Test name
Test status
Simulation time 144481185 ps
CPU time 0.82 seconds
Started Oct 15 12:56:17 PM UTC 24
Finished Oct 15 12:56:22 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056190028 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_mubi.3056190028
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.3922652926
Short name T860
Test name
Test status
Simulation time 51549159 ps
CPU time 0.59 seconds
Started Oct 15 12:56:15 PM UTC 24
Finished Oct 15 12:56:17 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922652926 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.3922652926
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all.4254489891
Short name T923
Test name
Test status
Simulation time 1470497710 ps
CPU time 3.19 seconds
Started Oct 15 12:56:22 PM UTC 24
Finished Oct 15 12:56:37 PM UTC 24
Peak memory 212680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254489891 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.4254489891
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all_with_rand_reset.1552198518
Short name T926
Test name
Test status
Simulation time 4624570523 ps
CPU time 10.03 seconds
Started Oct 15 12:56:22 PM UTC 24
Finished Oct 15 12:56:36 PM UTC 24
Peak memory 212908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1552198518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmg
r_stress_all_with_rand_reset.1552198518
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.3698444531
Short name T878
Test name
Test status
Simulation time 95142505 ps
CPU time 0.71 seconds
Started Oct 15 12:56:17 PM UTC 24
Finished Oct 15 12:56:22 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698444531 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.3698444531
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.717990709
Short name T886
Test name
Test status
Simulation time 181221505 ps
CPU time 1.31 seconds
Started Oct 15 12:56:17 PM UTC 24
Finished Oct 15 12:56:23 PM UTC 24
Peak memory 211384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717990709 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.717990709
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/44.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.1729358840
Short name T928
Test name
Test status
Simulation time 64131820 ps
CPU time 0.83 seconds
Started Oct 15 12:56:22 PM UTC 24
Finished Oct 15 12:56:34 PM UTC 24
Peak memory 211420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729358840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.1729358840
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.388989072
Short name T901
Test name
Test status
Simulation time 64913077 ps
CPU time 0.83 seconds
Started Oct 15 12:56:24 PM UTC 24
Finished Oct 15 12:56:27 PM UTC 24
Peak memory 211196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388989072 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disable_rom_integrity_check.388989072
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.2106665955
Short name T892
Test name
Test status
Simulation time 31052176 ps
CPU time 0.74 seconds
Started Oct 15 12:56:24 PM UTC 24
Finished Oct 15 12:56:26 PM UTC 24
Peak memory 208480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106665955 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst_malfunc.2106665955
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.2685703826
Short name T897
Test name
Test status
Simulation time 353792353 ps
CPU time 0.85 seconds
Started Oct 15 12:56:24 PM UTC 24
Finished Oct 15 12:56:27 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685703826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.2685703826
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.201521221
Short name T894
Test name
Test status
Simulation time 30568593 ps
CPU time 0.8 seconds
Started Oct 15 12:56:24 PM UTC 24
Finished Oct 15 12:56:27 PM UTC 24
Peak memory 208936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201521221 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.201521221
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_global_esc.3895259776
Short name T891
Test name
Test status
Simulation time 81353145 ps
CPU time 0.55 seconds
Started Oct 15 12:56:24 PM UTC 24
Finished Oct 15 12:56:26 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895259776 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.3895259776
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_invalid.965945645
Short name T899
Test name
Test status
Simulation time 120097747 ps
CPU time 0.72 seconds
Started Oct 15 12:56:24 PM UTC 24
Finished Oct 15 12:56:27 PM UTC 24
Peak memory 212904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965945645 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_invalid.965945645
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_wakeup_race.1303493783
Short name T932
Test name
Test status
Simulation time 273716746 ps
CPU time 1.02 seconds
Started Oct 15 12:56:22 PM UTC 24
Finished Oct 15 12:56:35 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303493783 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_wakeup_race.1303493783
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset.4038363430
Short name T924
Test name
Test status
Simulation time 38383424 ps
CPU time 0.79 seconds
Started Oct 15 12:56:22 PM UTC 24
Finished Oct 15 12:56:34 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038363430 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.4038363430
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.2055561762
Short name T902
Test name
Test status
Simulation time 103254275 ps
CPU time 0.95 seconds
Started Oct 15 12:56:24 PM UTC 24
Finished Oct 15 12:56:27 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055561762 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.2055561762
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.2867184033
Short name T898
Test name
Test status
Simulation time 136142791 ps
CPU time 1.01 seconds
Started Oct 15 12:56:24 PM UTC 24
Finished Oct 15 12:56:27 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867184033 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_ctrl_config_regwen.2867184033
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3561502030
Short name T946
Test name
Test status
Simulation time 1051396754 ps
CPU time 2.97 seconds
Started Oct 15 12:56:22 PM UTC 24
Finished Oct 15 12:56:37 PM UTC 24
Peak memory 212304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561502030 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3561502030
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1175712129
Short name T945
Test name
Test status
Simulation time 1490236844 ps
CPU time 2.09 seconds
Started Oct 15 12:56:22 PM UTC 24
Finished Oct 15 12:56:36 PM UTC 24
Peak memory 212416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175712129 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1175712129
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1159297425
Short name T893
Test name
Test status
Simulation time 378118574 ps
CPU time 0.81 seconds
Started Oct 15 12:56:24 PM UTC 24
Finished Oct 15 12:56:27 PM UTC 24
Peak memory 210868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159297425 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1159297425
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_smoke.3259034889
Short name T922
Test name
Test status
Simulation time 29237785 ps
CPU time 0.75 seconds
Started Oct 15 12:56:22 PM UTC 24
Finished Oct 15 12:56:34 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259034889 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.3259034889
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.808352622
Short name T906
Test name
Test status
Simulation time 430958087 ps
CPU time 1.6 seconds
Started Oct 15 12:56:24 PM UTC 24
Finished Oct 15 12:56:28 PM UTC 24
Peak memory 211344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808352622 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.808352622
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.2705662215
Short name T943
Test name
Test status
Simulation time 6803870570 ps
CPU time 9.55 seconds
Started Oct 15 12:56:24 PM UTC 24
Finished Oct 15 12:56:36 PM UTC 24
Peak memory 212668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2705662215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmg
r_stress_all_with_rand_reset.2705662215
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.1757154664
Short name T931
Test name
Test status
Simulation time 276987505 ps
CPU time 0.99 seconds
Started Oct 15 12:56:22 PM UTC 24
Finished Oct 15 12:56:35 PM UTC 24
Peak memory 210140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757154664 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.1757154664
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.3524038121
Short name T934
Test name
Test status
Simulation time 262484551 ps
CPU time 0.98 seconds
Started Oct 15 12:56:22 PM UTC 24
Finished Oct 15 12:56:35 PM UTC 24
Peak memory 211384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524038121 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.3524038121
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/45.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.2019048717
Short name T912
Test name
Test status
Simulation time 78298016 ps
CPU time 1.02 seconds
Started Oct 15 12:56:28 PM UTC 24
Finished Oct 15 12:56:33 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019048717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.2019048717
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.363405850
Short name T913
Test name
Test status
Simulation time 151776599 ps
CPU time 0.67 seconds
Started Oct 15 12:56:28 PM UTC 24
Finished Oct 15 12:56:33 PM UTC 24
Peak memory 209060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363405850 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disable_rom_integrity_check.363405850
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.4114208899
Short name T910
Test name
Test status
Simulation time 46595539 ps
CPU time 0.72 seconds
Started Oct 15 12:56:28 PM UTC 24
Finished Oct 15 12:56:33 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114208899 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_malfunc.4114208899
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.3188422951
Short name T918
Test name
Test status
Simulation time 205536528 ps
CPU time 1.03 seconds
Started Oct 15 12:56:28 PM UTC 24
Finished Oct 15 12:56:33 PM UTC 24
Peak memory 208912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188422951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.3188422951
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_glitch.2941087719
Short name T911
Test name
Test status
Simulation time 68431275 ps
CPU time 0.57 seconds
Started Oct 15 12:56:28 PM UTC 24
Finished Oct 15 12:56:33 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941087719 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.2941087719
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.1669894676
Short name T915
Test name
Test status
Simulation time 24425784 ps
CPU time 0.78 seconds
Started Oct 15 12:56:28 PM UTC 24
Finished Oct 15 12:56:33 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669894676 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.1669894676
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_invalid.2970151094
Short name T917
Test name
Test status
Simulation time 77843719 ps
CPU time 0.88 seconds
Started Oct 15 12:56:28 PM UTC 24
Finished Oct 15 12:56:33 PM UTC 24
Peak memory 212768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970151094 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invalid.2970151094
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.603549491
Short name T933
Test name
Test status
Simulation time 339956374 ps
CPU time 1.2 seconds
Started Oct 15 12:56:25 PM UTC 24
Finished Oct 15 12:56:35 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603549491 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_wakeup_race.603549491
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset.3354479009
Short name T903
Test name
Test status
Simulation time 58636539 ps
CPU time 0.82 seconds
Started Oct 15 12:56:24 PM UTC 24
Finished Oct 15 12:56:27 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354479009 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.3354479009
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.3836064076
Short name T919
Test name
Test status
Simulation time 101747590 ps
CPU time 0.98 seconds
Started Oct 15 12:56:28 PM UTC 24
Finished Oct 15 12:56:33 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836064076 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.3836064076
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.1506587350
Short name T916
Test name
Test status
Simulation time 464924069 ps
CPU time 1.01 seconds
Started Oct 15 12:56:28 PM UTC 24
Finished Oct 15 12:56:33 PM UTC 24
Peak memory 210352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506587350 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_ctrl_config_regwen.1506587350
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1184763200
Short name T920
Test name
Test status
Simulation time 1009524044 ps
CPU time 2.03 seconds
Started Oct 15 12:56:28 PM UTC 24
Finished Oct 15 12:56:34 PM UTC 24
Peak memory 212752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184763200 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1184763200
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3082024631
Short name T921
Test name
Test status
Simulation time 1746063523 ps
CPU time 2.23 seconds
Started Oct 15 12:56:28 PM UTC 24
Finished Oct 15 12:56:34 PM UTC 24
Peak memory 212488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082024631 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3082024631
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1656127554
Short name T914
Test name
Test status
Simulation time 168504850 ps
CPU time 0.99 seconds
Started Oct 15 12:56:28 PM UTC 24
Finished Oct 15 12:56:33 PM UTC 24
Peak memory 209824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656127554 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1656127554
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.3529947287
Short name T900
Test name
Test status
Simulation time 38598111 ps
CPU time 0.65 seconds
Started Oct 15 12:56:24 PM UTC 24
Finished Oct 15 12:56:27 PM UTC 24
Peak memory 209228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529947287 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.3529947287
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.3803822096
Short name T957
Test name
Test status
Simulation time 1810034638 ps
CPU time 6.43 seconds
Started Oct 15 12:56:28 PM UTC 24
Finished Oct 15 12:56:39 PM UTC 24
Peak memory 212404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803822096 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.3803822096
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.2613024115
Short name T973
Test name
Test status
Simulation time 2441443318 ps
CPU time 8.24 seconds
Started Oct 15 12:56:28 PM UTC 24
Finished Oct 15 12:56:40 PM UTC 24
Peak memory 212588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2613024115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmg
r_stress_all_with_rand_reset.2613024115
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.1320076552
Short name T930
Test name
Test status
Simulation time 144152035 ps
CPU time 1.08 seconds
Started Oct 15 12:56:25 PM UTC 24
Finished Oct 15 12:56:35 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320076552 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.1320076552
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.2804919774
Short name T941
Test name
Test status
Simulation time 159561608 ps
CPU time 1.05 seconds
Started Oct 15 12:56:26 PM UTC 24
Finished Oct 15 12:56:36 PM UTC 24
Peak memory 211276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804919774 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.2804919774
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/46.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.541900827
Short name T936
Test name
Test status
Simulation time 28977250 ps
CPU time 0.87 seconds
Started Oct 15 12:56:33 PM UTC 24
Finished Oct 15 12:56:35 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541900827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.541900827
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.2332674273
Short name T942
Test name
Test status
Simulation time 61669021 ps
CPU time 0.89 seconds
Started Oct 15 12:56:34 PM UTC 24
Finished Oct 15 12:56:36 PM UTC 24
Peak memory 209384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332674273 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_disable_rom_integrity_check.2332674273
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.1542988258
Short name T938
Test name
Test status
Simulation time 39850290 ps
CPU time 0.87 seconds
Started Oct 15 12:56:34 PM UTC 24
Finished Oct 15 12:56:35 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542988258 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_malfunc.1542988258
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.1707949082
Short name T939
Test name
Test status
Simulation time 406821612 ps
CPU time 0.85 seconds
Started Oct 15 12:56:34 PM UTC 24
Finished Oct 15 12:56:36 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707949082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.1707949082
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.810563983
Short name T940
Test name
Test status
Simulation time 22780588 ps
CPU time 0.79 seconds
Started Oct 15 12:56:34 PM UTC 24
Finished Oct 15 12:56:36 PM UTC 24
Peak memory 208932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810563983 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.810563983
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.4294442427
Short name T937
Test name
Test status
Simulation time 312813277 ps
CPU time 0.69 seconds
Started Oct 15 12:56:34 PM UTC 24
Finished Oct 15 12:56:35 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294442427 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.4294442427
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.2739965905
Short name T948
Test name
Test status
Simulation time 273210952 ps
CPU time 0.81 seconds
Started Oct 15 12:56:35 PM UTC 24
Finished Oct 15 12:56:37 PM UTC 24
Peak memory 212968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739965905 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_invalid.2739965905
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.3737054588
Short name T927
Test name
Test status
Simulation time 252444518 ps
CPU time 1.04 seconds
Started Oct 15 12:56:32 PM UTC 24
Finished Oct 15 12:56:34 PM UTC 24
Peak memory 211380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737054588 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_wakeup_race.3737054588
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.1640660105
Short name T909
Test name
Test status
Simulation time 48673006 ps
CPU time 0.59 seconds
Started Oct 15 12:56:29 PM UTC 24
Finished Oct 15 12:56:32 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640660105 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.1640660105
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.1739331265
Short name T947
Test name
Test status
Simulation time 117065143 ps
CPU time 0.83 seconds
Started Oct 15 12:56:35 PM UTC 24
Finished Oct 15 12:56:37 PM UTC 24
Peak memory 212900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739331265 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.1739331265
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.854732178
Short name T944
Test name
Test status
Simulation time 65713862 ps
CPU time 1.12 seconds
Started Oct 15 12:56:34 PM UTC 24
Finished Oct 15 12:56:36 PM UTC 24
Peak memory 210616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854732178 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_ctrl_config_regwen.854732178
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2104297693
Short name T956
Test name
Test status
Simulation time 841106294 ps
CPU time 3.68 seconds
Started Oct 15 12:56:33 PM UTC 24
Finished Oct 15 12:56:38 PM UTC 24
Peak memory 212304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104297693 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2104297693
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1367713304
Short name T952
Test name
Test status
Simulation time 1055377899 ps
CPU time 2.55 seconds
Started Oct 15 12:56:33 PM UTC 24
Finished Oct 15 12:56:37 PM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367713304 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1367713304
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.997755298
Short name T935
Test name
Test status
Simulation time 93482524 ps
CPU time 0.8 seconds
Started Oct 15 12:56:34 PM UTC 24
Finished Oct 15 12:56:35 PM UTC 24
Peak memory 209884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997755298 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig_mubi.997755298
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.1243622926
Short name T908
Test name
Test status
Simulation time 28112105 ps
CPU time 0.58 seconds
Started Oct 15 12:56:29 PM UTC 24
Finished Oct 15 12:56:32 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243622926 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.1243622926
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.3721094430
Short name T972
Test name
Test status
Simulation time 2709543869 ps
CPU time 3.99 seconds
Started Oct 15 12:56:35 PM UTC 24
Finished Oct 15 12:56:40 PM UTC 24
Peak memory 212484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721094430 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.3721094430
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.1623201673
Short name T55
Test name
Test status
Simulation time 3527172335 ps
CPU time 12.74 seconds
Started Oct 15 12:56:35 PM UTC 24
Finished Oct 15 12:56:49 PM UTC 24
Peak memory 212732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1623201673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmg
r_stress_all_with_rand_reset.1623201673
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.1243418842
Short name T929
Test name
Test status
Simulation time 280927785 ps
CPU time 1.27 seconds
Started Oct 15 12:56:32 PM UTC 24
Finished Oct 15 12:56:34 PM UTC 24
Peak memory 210396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243418842 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.1243418842
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.2255022968
Short name T925
Test name
Test status
Simulation time 33668125 ps
CPU time 0.93 seconds
Started Oct 15 12:56:32 PM UTC 24
Finished Oct 15 12:56:34 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255022968 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.2255022968
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/47.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.3915175036
Short name T953
Test name
Test status
Simulation time 38310106 ps
CPU time 0.8 seconds
Started Oct 15 12:56:35 PM UTC 24
Finished Oct 15 12:56:37 PM UTC 24
Peak memory 209560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915175036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.3915175036
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.4104373411
Short name T962
Test name
Test status
Simulation time 94223372 ps
CPU time 0.73 seconds
Started Oct 15 12:56:37 PM UTC 24
Finished Oct 15 12:56:39 PM UTC 24
Peak memory 209120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104373411 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disable_rom_integrity_check.4104373411
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.1887862344
Short name T958
Test name
Test status
Simulation time 29194331 ps
CPU time 0.74 seconds
Started Oct 15 12:56:37 PM UTC 24
Finished Oct 15 12:56:39 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887862344 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_malfunc.1887862344
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.1479634748
Short name T965
Test name
Test status
Simulation time 108465799 ps
CPU time 1 seconds
Started Oct 15 12:56:37 PM UTC 24
Finished Oct 15 12:56:39 PM UTC 24
Peak memory 208860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479634748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.1479634748
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.3522463711
Short name T960
Test name
Test status
Simulation time 72212993 ps
CPU time 0.73 seconds
Started Oct 15 12:56:37 PM UTC 24
Finished Oct 15 12:56:39 PM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522463711 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.3522463711
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.348022530
Short name T961
Test name
Test status
Simulation time 67514756 ps
CPU time 0.76 seconds
Started Oct 15 12:56:37 PM UTC 24
Finished Oct 15 12:56:39 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348022530 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.348022530
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_invalid.2917430201
Short name T966
Test name
Test status
Simulation time 52917535 ps
CPU time 0.74 seconds
Started Oct 15 12:56:37 PM UTC 24
Finished Oct 15 12:56:39 PM UTC 24
Peak memory 210840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917430201 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_invalid.2917430201
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.3257581606
Short name T955
Test name
Test status
Simulation time 342114518 ps
CPU time 1.13 seconds
Started Oct 15 12:56:35 PM UTC 24
Finished Oct 15 12:56:37 PM UTC 24
Peak memory 210420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257581606 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_wakeup_race.3257581606
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.325315634
Short name T954
Test name
Test status
Simulation time 87582882 ps
CPU time 1.03 seconds
Started Oct 15 12:56:35 PM UTC 24
Finished Oct 15 12:56:37 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325315634 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.325315634
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.1110431919
Short name T969
Test name
Test status
Simulation time 111580035 ps
CPU time 1.01 seconds
Started Oct 15 12:56:37 PM UTC 24
Finished Oct 15 12:56:40 PM UTC 24
Peak memory 221272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110431919 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.1110431919
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.3790202549
Short name T963
Test name
Test status
Simulation time 80574370 ps
CPU time 1.02 seconds
Started Oct 15 12:56:37 PM UTC 24
Finished Oct 15 12:56:39 PM UTC 24
Peak memory 210040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790202549 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_ctrl_config_regwen.3790202549
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1119447861
Short name T970
Test name
Test status
Simulation time 1123829978 ps
CPU time 2.04 seconds
Started Oct 15 12:56:37 PM UTC 24
Finished Oct 15 12:56:40 PM UTC 24
Peak memory 212736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119447861 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1119447861
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.328862740
Short name T974
Test name
Test status
Simulation time 1390851456 ps
CPU time 2.42 seconds
Started Oct 15 12:56:37 PM UTC 24
Finished Oct 15 12:56:41 PM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328862740 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.328862740
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3471339023
Short name T959
Test name
Test status
Simulation time 88919454 ps
CPU time 0.91 seconds
Started Oct 15 12:56:37 PM UTC 24
Finished Oct 15 12:56:39 PM UTC 24
Peak memory 210628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471339023 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3471339023
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.3936589801
Short name T949
Test name
Test status
Simulation time 88297154 ps
CPU time 0.85 seconds
Started Oct 15 12:56:35 PM UTC 24
Finished Oct 15 12:56:37 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936589801 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.3936589801
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.2262934970
Short name T971
Test name
Test status
Simulation time 84022996 ps
CPU time 1.52 seconds
Started Oct 15 12:56:38 PM UTC 24
Finished Oct 15 12:56:40 PM UTC 24
Peak memory 211024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262934970 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.2262934970
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all_with_rand_reset.3633744323
Short name T990
Test name
Test status
Simulation time 6436660700 ps
CPU time 7.78 seconds
Started Oct 15 12:56:37 PM UTC 24
Finished Oct 15 12:56:46 PM UTC 24
Peak memory 212732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3633744323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmg
r_stress_all_with_rand_reset.3633744323
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.3292001431
Short name T951
Test name
Test status
Simulation time 66728249 ps
CPU time 0.74 seconds
Started Oct 15 12:56:35 PM UTC 24
Finished Oct 15 12:56:37 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292001431 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.3292001431
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.1265269835
Short name T950
Test name
Test status
Simulation time 86161777 ps
CPU time 0.8 seconds
Started Oct 15 12:56:35 PM UTC 24
Finished Oct 15 12:56:37 PM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265269835 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.1265269835
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/48.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.934330386
Short name T976
Test name
Test status
Simulation time 425082217 ps
CPU time 0.87 seconds
Started Oct 15 12:56:39 PM UTC 24
Finished Oct 15 12:56:41 PM UTC 24
Peak memory 210680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934330386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.934330386
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.1384608795
Short name T977
Test name
Test status
Simulation time 69394799 ps
CPU time 0.68 seconds
Started Oct 15 12:56:39 PM UTC 24
Finished Oct 15 12:56:41 PM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384608795 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_disable_rom_integrity_check.1384608795
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.560077957
Short name T979
Test name
Test status
Simulation time 51839420 ps
CPU time 0.82 seconds
Started Oct 15 12:56:39 PM UTC 24
Finished Oct 15 12:56:41 PM UTC 24
Peak memory 209080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560077957 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_malfunc.560077957
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.855188969
Short name T983
Test name
Test status
Simulation time 405014078 ps
CPU time 0.94 seconds
Started Oct 15 12:56:39 PM UTC 24
Finished Oct 15 12:56:41 PM UTC 24
Peak memory 209184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855188969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.855188969
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.791153382
Short name T982
Test name
Test status
Simulation time 47642990 ps
CPU time 0.84 seconds
Started Oct 15 12:56:39 PM UTC 24
Finished Oct 15 12:56:41 PM UTC 24
Peak memory 208932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791153382 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.791153382
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.2381340938
Short name T978
Test name
Test status
Simulation time 96257828 ps
CPU time 0.75 seconds
Started Oct 15 12:56:39 PM UTC 24
Finished Oct 15 12:56:41 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381340938 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.2381340938
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_invalid.1010029307
Short name T985
Test name
Test status
Simulation time 135042359 ps
CPU time 0.69 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:43 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010029307 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_invalid.1010029307
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.3841074400
Short name T968
Test name
Test status
Simulation time 43112293 ps
CPU time 0.79 seconds
Started Oct 15 12:56:38 PM UTC 24
Finished Oct 15 12:56:39 PM UTC 24
Peak memory 208996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841074400 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_wakeup_race.3841074400
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.803137143
Short name T967
Test name
Test status
Simulation time 142947881 ps
CPU time 0.77 seconds
Started Oct 15 12:56:38 PM UTC 24
Finished Oct 15 12:56:39 PM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803137143 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.803137143
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.4118874699
Short name T986
Test name
Test status
Simulation time 105774667 ps
CPU time 0.96 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:43 PM UTC 24
Peak memory 212900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118874699 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.4118874699
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.2181875808
Short name T980
Test name
Test status
Simulation time 110903392 ps
CPU time 0.88 seconds
Started Oct 15 12:56:39 PM UTC 24
Finished Oct 15 12:56:41 PM UTC 24
Peak memory 210340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181875808 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_ctrl_config_regwen.2181875808
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1362132404
Short name T988
Test name
Test status
Simulation time 840014491 ps
CPU time 3.14 seconds
Started Oct 15 12:56:39 PM UTC 24
Finished Oct 15 12:56:43 PM UTC 24
Peak memory 212304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362132404 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1362132404
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3584727402
Short name T989
Test name
Test status
Simulation time 869945830 ps
CPU time 3.54 seconds
Started Oct 15 12:56:39 PM UTC 24
Finished Oct 15 12:56:44 PM UTC 24
Peak memory 212704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584727402 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3584727402
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1518330727
Short name T984
Test name
Test status
Simulation time 52123476 ps
CPU time 1.23 seconds
Started Oct 15 12:56:39 PM UTC 24
Finished Oct 15 12:56:42 PM UTC 24
Peak memory 209884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518330727 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1518330727
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.1364027538
Short name T964
Test name
Test status
Simulation time 59211454 ps
CPU time 0.64 seconds
Started Oct 15 12:56:38 PM UTC 24
Finished Oct 15 12:56:39 PM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364027538 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.1364027538
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.232108535
Short name T987
Test name
Test status
Simulation time 228524687 ps
CPU time 1.48 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:43 PM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232108535 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.232108535
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.401310054
Short name T991
Test name
Test status
Simulation time 15292955923 ps
CPU time 14.26 seconds
Started Oct 15 12:56:41 PM UTC 24
Finished Oct 15 12:56:56 PM UTC 24
Peak memory 212796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=401310054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr
_stress_all_with_rand_reset.401310054
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.3720440308
Short name T975
Test name
Test status
Simulation time 165187377 ps
CPU time 0.9 seconds
Started Oct 15 12:56:39 PM UTC 24
Finished Oct 15 12:56:41 PM UTC 24
Peak memory 209108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720440308 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.3720440308
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.666226330
Short name T981
Test name
Test status
Simulation time 171120313 ps
CPU time 1.15 seconds
Started Oct 15 12:56:39 PM UTC 24
Finished Oct 15 12:56:41 PM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666226330 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.666226330
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/49.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.837958346
Short name T138
Test name
Test status
Simulation time 25529703 ps
CPU time 0.97 seconds
Started Oct 15 12:53:19 PM UTC 24
Finished Oct 15 12:53:21 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837958346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.837958346
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.3003269888
Short name T160
Test name
Test status
Simulation time 91594997 ps
CPU time 1.05 seconds
Started Oct 15 12:53:21 PM UTC 24
Finished Oct 15 12:53:23 PM UTC 24
Peak memory 209056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003269888 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disable_rom_integrity_check.3003269888
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.2729320708
Short name T154
Test name
Test status
Simulation time 28961213 ps
CPU time 0.99 seconds
Started Oct 15 12:53:20 PM UTC 24
Finished Oct 15 12:53:22 PM UTC 24
Peak memory 209124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729320708 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_malfunc.2729320708
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.4192862361
Short name T155
Test name
Test status
Simulation time 335780912 ps
CPU time 1.44 seconds
Started Oct 15 12:53:20 PM UTC 24
Finished Oct 15 12:53:22 PM UTC 24
Peak memory 209240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192862361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.4192862361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.1677603970
Short name T213
Test name
Test status
Simulation time 55582349 ps
CPU time 0.92 seconds
Started Oct 15 12:53:21 PM UTC 24
Finished Oct 15 12:53:23 PM UTC 24
Peak memory 208932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677603970 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.1677603970
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.3142904946
Short name T210
Test name
Test status
Simulation time 33465998 ps
CPU time 1.02 seconds
Started Oct 15 12:53:20 PM UTC 24
Finished Oct 15 12:53:22 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142904946 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.3142904946
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.3327021337
Short name T214
Test name
Test status
Simulation time 66931124 ps
CPU time 1.02 seconds
Started Oct 15 12:53:21 PM UTC 24
Finished Oct 15 12:53:23 PM UTC 24
Peak memory 212848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327021337 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invalid.3327021337
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.3525988028
Short name T205
Test name
Test status
Simulation time 70619431 ps
CPU time 0.98 seconds
Started Oct 15 12:53:18 PM UTC 24
Finished Oct 15 12:53:20 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525988028 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wakeup_race.3525988028
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.1681070472
Short name T206
Test name
Test status
Simulation time 52103280 ps
CPU time 1.09 seconds
Started Oct 15 12:53:18 PM UTC 24
Finished Oct 15 12:53:20 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681070472 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.1681070472
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.89341854
Short name T215
Test name
Test status
Simulation time 88532907 ps
CPU time 1.64 seconds
Started Oct 15 12:53:21 PM UTC 24
Finished Oct 15 12:53:24 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89341854 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.89341854
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.366264927
Short name T209
Test name
Test status
Simulation time 156913881 ps
CPU time 1.04 seconds
Started Oct 15 12:53:20 PM UTC 24
Finished Oct 15 12:53:22 PM UTC 24
Peak memory 210344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366264927 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_ctrl_config_regwen.366264927
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3096447829
Short name T161
Test name
Test status
Simulation time 967680298 ps
CPU time 3.11 seconds
Started Oct 15 12:53:19 PM UTC 24
Finished Oct 15 12:53:24 PM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096447829 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.3096447829
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2348875244
Short name T216
Test name
Test status
Simulation time 852529422 ps
CPU time 3.35 seconds
Started Oct 15 12:53:19 PM UTC 24
Finished Oct 15 12:53:24 PM UTC 24
Peak memory 212496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348875244 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.2348875244
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1852509738
Short name T211
Test name
Test status
Simulation time 144782201 ps
CPU time 1.29 seconds
Started Oct 15 12:53:19 PM UTC 24
Finished Oct 15 12:53:22 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852509738 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1852509738
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.3393225636
Short name T204
Test name
Test status
Simulation time 31531232 ps
CPU time 1.1 seconds
Started Oct 15 12:53:18 PM UTC 24
Finished Oct 15 12:53:20 PM UTC 24
Peak memory 208992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393225636 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.3393225636
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.665617520
Short name T226
Test name
Test status
Simulation time 706263947 ps
CPU time 3.64 seconds
Started Oct 15 12:53:23 PM UTC 24
Finished Oct 15 12:53:27 PM UTC 24
Peak memory 212272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665617520 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.665617520
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.1591565241
Short name T141
Test name
Test status
Simulation time 4575109245 ps
CPU time 12.23 seconds
Started Oct 15 12:53:22 PM UTC 24
Finished Oct 15 12:53:36 PM UTC 24
Peak memory 212732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1591565241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr
_stress_all_with_rand_reset.1591565241
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.408250873
Short name T207
Test name
Test status
Simulation time 368904199 ps
CPU time 1.46 seconds
Started Oct 15 12:53:18 PM UTC 24
Finished Oct 15 12:53:20 PM UTC 24
Peak memory 210888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408250873 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.408250873
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.1227783386
Short name T208
Test name
Test status
Simulation time 192694943 ps
CPU time 1.98 seconds
Started Oct 15 12:53:18 PM UTC 24
Finished Oct 15 12:53:21 PM UTC 24
Peak memory 210976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227783386 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.1227783386
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/5.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.2253244324
Short name T139
Test name
Test status
Simulation time 67332310 ps
CPU time 1.13 seconds
Started Oct 15 12:53:23 PM UTC 24
Finished Oct 15 12:53:25 PM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253244324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.2253244324
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.2919195687
Short name T162
Test name
Test status
Simulation time 68517368 ps
CPU time 1.06 seconds
Started Oct 15 12:53:26 PM UTC 24
Finished Oct 15 12:53:28 PM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919195687 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disable_rom_integrity_check.2919195687
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2850801566
Short name T222
Test name
Test status
Simulation time 29803130 ps
CPU time 1.01 seconds
Started Oct 15 12:53:24 PM UTC 24
Finished Oct 15 12:53:26 PM UTC 24
Peak memory 209124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850801566 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_malfunc.2850801566
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.684928466
Short name T231
Test name
Test status
Simulation time 112907415 ps
CPU time 1.41 seconds
Started Oct 15 12:53:26 PM UTC 24
Finished Oct 15 12:53:28 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684928466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.684928466
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.862027430
Short name T228
Test name
Test status
Simulation time 54875239 ps
CPU time 0.97 seconds
Started Oct 15 12:53:26 PM UTC 24
Finished Oct 15 12:53:28 PM UTC 24
Peak memory 208932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862027430 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.862027430
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.3012467253
Short name T224
Test name
Test status
Simulation time 21045188 ps
CPU time 0.94 seconds
Started Oct 15 12:53:24 PM UTC 24
Finished Oct 15 12:53:26 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012467253 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.3012467253
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.3303703435
Short name T219
Test name
Test status
Simulation time 343078397 ps
CPU time 1.26 seconds
Started Oct 15 12:53:23 PM UTC 24
Finished Oct 15 12:53:25 PM UTC 24
Peak memory 209040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303703435 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wakeup_race.3303703435
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.1529935527
Short name T217
Test name
Test status
Simulation time 60104511 ps
CPU time 0.96 seconds
Started Oct 15 12:53:23 PM UTC 24
Finished Oct 15 12:53:25 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529935527 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.1529935527
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.763112295
Short name T230
Test name
Test status
Simulation time 136211636 ps
CPU time 1.3 seconds
Started Oct 15 12:53:26 PM UTC 24
Finished Oct 15 12:53:28 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763112295 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.763112295
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.4245486223
Short name T225
Test name
Test status
Simulation time 210264687 ps
CPU time 1.52 seconds
Started Oct 15 12:53:24 PM UTC 24
Finished Oct 15 12:53:27 PM UTC 24
Peak memory 211604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245486223 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_ctrl_config_regwen.4245486223
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.259820602
Short name T96
Test name
Test status
Simulation time 835005205 ps
CPU time 3.74 seconds
Started Oct 15 12:53:24 PM UTC 24
Finished Oct 15 12:53:29 PM UTC 24
Peak memory 212624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259820602 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig
_mubi.259820602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.174545071
Short name T227
Test name
Test status
Simulation time 1007682460 ps
CPU time 2.6 seconds
Started Oct 15 12:53:24 PM UTC 24
Finished Oct 15 12:53:28 PM UTC 24
Peak memory 212672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174545071 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_inters
ig_mubi.174545071
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2729967151
Short name T223
Test name
Test status
Simulation time 97873776 ps
CPU time 1.05 seconds
Started Oct 15 12:53:24 PM UTC 24
Finished Oct 15 12:53:26 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729967151 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2729967151
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.331732614
Short name T218
Test name
Test status
Simulation time 26797825 ps
CPU time 1.04 seconds
Started Oct 15 12:53:23 PM UTC 24
Finished Oct 15 12:53:25 PM UTC 24
Peak memory 208992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331732614 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.331732614
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.2544273842
Short name T237
Test name
Test status
Simulation time 2343145004 ps
CPU time 5.32 seconds
Started Oct 15 12:53:26 PM UTC 24
Finished Oct 15 12:53:33 PM UTC 24
Peak memory 212920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544273842 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.2544273842
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.1179915881
Short name T142
Test name
Test status
Simulation time 7194085319 ps
CPU time 12.52 seconds
Started Oct 15 12:53:26 PM UTC 24
Finished Oct 15 12:53:40 PM UTC 24
Peak memory 212940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1179915881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr
_stress_all_with_rand_reset.1179915881
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.3828115889
Short name T220
Test name
Test status
Simulation time 247299731 ps
CPU time 1.6 seconds
Started Oct 15 12:53:23 PM UTC 24
Finished Oct 15 12:53:25 PM UTC 24
Peak memory 211140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828115889 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.3828115889
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.3506950183
Short name T221
Test name
Test status
Simulation time 226471790 ps
CPU time 1.85 seconds
Started Oct 15 12:53:23 PM UTC 24
Finished Oct 15 12:53:26 PM UTC 24
Peak memory 211384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506950183 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.3506950183
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/6.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.727105626
Short name T104
Test name
Test status
Simulation time 40337689 ps
CPU time 1.24 seconds
Started Oct 15 12:53:29 PM UTC 24
Finished Oct 15 12:53:31 PM UTC 24
Peak memory 211156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727105626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.727105626
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.1548019334
Short name T163
Test name
Test status
Simulation time 60504117 ps
CPU time 1.22 seconds
Started Oct 15 12:53:30 PM UTC 24
Finished Oct 15 12:53:33 PM UTC 24
Peak memory 211252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548019334 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disable_rom_integrity_check.1548019334
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.1209096223
Short name T102
Test name
Test status
Simulation time 36248860 ps
CPU time 0.81 seconds
Started Oct 15 12:53:29 PM UTC 24
Finished Oct 15 12:53:31 PM UTC 24
Peak memory 209180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209096223 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_malfunc.1209096223
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.3397811796
Short name T234
Test name
Test status
Simulation time 384616806 ps
CPU time 1.39 seconds
Started Oct 15 12:53:29 PM UTC 24
Finished Oct 15 12:53:32 PM UTC 24
Peak memory 209240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397811796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.3397811796
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.297431684
Short name T235
Test name
Test status
Simulation time 31328064 ps
CPU time 0.96 seconds
Started Oct 15 12:53:30 PM UTC 24
Finished Oct 15 12:53:32 PM UTC 24
Peak memory 208932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297431684 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.297431684
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.1015746742
Short name T103
Test name
Test status
Simulation time 22032468 ps
CPU time 0.95 seconds
Started Oct 15 12:53:29 PM UTC 24
Finished Oct 15 12:53:31 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015746742 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.1015746742
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.3265125373
Short name T236
Test name
Test status
Simulation time 41870675 ps
CPU time 1.16 seconds
Started Oct 15 12:53:31 PM UTC 24
Finished Oct 15 12:53:33 PM UTC 24
Peak memory 212908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265125373 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invalid.3265125373
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1976922847
Short name T99
Test name
Test status
Simulation time 133979530 ps
CPU time 1.34 seconds
Started Oct 15 12:53:27 PM UTC 24
Finished Oct 15 12:53:30 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976922847 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wakeup_race.1976922847
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.2418501921
Short name T98
Test name
Test status
Simulation time 91382385 ps
CPU time 1.11 seconds
Started Oct 15 12:53:27 PM UTC 24
Finished Oct 15 12:53:30 PM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418501921 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.2418501921
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.711961176
Short name T239
Test name
Test status
Simulation time 111433545 ps
CPU time 1.17 seconds
Started Oct 15 12:53:30 PM UTC 24
Finished Oct 15 12:53:33 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711961176 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.711961176
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2783614811
Short name T233
Test name
Test status
Simulation time 153054101 ps
CPU time 1.06 seconds
Started Oct 15 12:53:29 PM UTC 24
Finished Oct 15 12:53:31 PM UTC 24
Peak memory 209788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783614811 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_ctrl_config_regwen.2783614811
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2140084530
Short name T244
Test name
Test status
Simulation time 751132011 ps
CPU time 4.56 seconds
Started Oct 15 12:53:29 PM UTC 24
Finished Oct 15 12:53:34 PM UTC 24
Peak memory 212432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140084530 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.2140084530
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.561803219
Short name T238
Test name
Test status
Simulation time 1149442348 ps
CPU time 2.7 seconds
Started Oct 15 12:53:29 PM UTC 24
Finished Oct 15 12:53:33 PM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561803219 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_inters
ig_mubi.561803219
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.752971831
Short name T232
Test name
Test status
Simulation time 140602660 ps
CPU time 1.08 seconds
Started Oct 15 12:53:29 PM UTC 24
Finished Oct 15 12:53:31 PM UTC 24
Peak memory 210624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752971831 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_mubi.752971831
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.1559865848
Short name T97
Test name
Test status
Simulation time 40913236 ps
CPU time 0.96 seconds
Started Oct 15 12:53:27 PM UTC 24
Finished Oct 15 12:53:29 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559865848 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.1559865848
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.2109554981
Short name T114
Test name
Test status
Simulation time 1597008285 ps
CPU time 7.87 seconds
Started Oct 15 12:53:31 PM UTC 24
Finished Oct 15 12:53:40 PM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109554981 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.2109554981
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.2152722225
Short name T143
Test name
Test status
Simulation time 6316304248 ps
CPU time 12.42 seconds
Started Oct 15 12:53:31 PM UTC 24
Finished Oct 15 12:53:44 PM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2152722225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr
_stress_all_with_rand_reset.2152722225
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.1647492864
Short name T100
Test name
Test status
Simulation time 283511101 ps
CPU time 1.26 seconds
Started Oct 15 12:53:27 PM UTC 24
Finished Oct 15 12:53:30 PM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647492864 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.1647492864
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2987068316
Short name T101
Test name
Test status
Simulation time 167170188 ps
CPU time 1.37 seconds
Started Oct 15 12:53:28 PM UTC 24
Finished Oct 15 12:53:30 PM UTC 24
Peak memory 211444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987068316 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.2987068316
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/7.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.4173138792
Short name T242
Test name
Test status
Simulation time 35394404 ps
CPU time 1.24 seconds
Started Oct 15 12:53:32 PM UTC 24
Finished Oct 15 12:53:34 PM UTC 24
Peak memory 210352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173138792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.4173138792
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.2608303158
Short name T181
Test name
Test status
Simulation time 55634221 ps
CPU time 1.39 seconds
Started Oct 15 12:53:35 PM UTC 24
Finished Oct 15 12:53:37 PM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608303158 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disable_rom_integrity_check.2608303158
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.2738360349
Short name T246
Test name
Test status
Simulation time 31339317 ps
CPU time 0.94 seconds
Started Oct 15 12:53:33 PM UTC 24
Finished Oct 15 12:53:35 PM UTC 24
Peak memory 209180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738360349 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_malfunc.2738360349
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.1198772692
Short name T250
Test name
Test status
Simulation time 1168646776 ps
CPU time 1.35 seconds
Started Oct 15 12:53:34 PM UTC 24
Finished Oct 15 12:53:36 PM UTC 24
Peak memory 209240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198772692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.1198772692
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.2933008127
Short name T247
Test name
Test status
Simulation time 62696575 ps
CPU time 0.85 seconds
Started Oct 15 12:53:34 PM UTC 24
Finished Oct 15 12:53:35 PM UTC 24
Peak memory 208932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933008127 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.2933008127
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.2250181903
Short name T248
Test name
Test status
Simulation time 23145070 ps
CPU time 0.94 seconds
Started Oct 15 12:53:34 PM UTC 24
Finished Oct 15 12:53:36 PM UTC 24
Peak memory 209176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250181903 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.2250181903
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.2977172388
Short name T253
Test name
Test status
Simulation time 49969562 ps
CPU time 1.08 seconds
Started Oct 15 12:53:35 PM UTC 24
Finished Oct 15 12:53:37 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977172388 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid.2977172388
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.2488234429
Short name T241
Test name
Test status
Simulation time 295034772 ps
CPU time 1.4 seconds
Started Oct 15 12:53:32 PM UTC 24
Finished Oct 15 12:53:34 PM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488234429 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wakeup_race.2488234429
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.402342558
Short name T243
Test name
Test status
Simulation time 58741282 ps
CPU time 1.43 seconds
Started Oct 15 12:53:32 PM UTC 24
Finished Oct 15 12:53:34 PM UTC 24
Peak memory 210848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402342558 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.402342558
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.2221746276
Short name T254
Test name
Test status
Simulation time 121478779 ps
CPU time 1.32 seconds
Started Oct 15 12:53:35 PM UTC 24
Finished Oct 15 12:53:37 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221746276 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.2221746276
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.1467557288
Short name T251
Test name
Test status
Simulation time 199767407 ps
CPU time 1.87 seconds
Started Oct 15 12:53:34 PM UTC 24
Finished Oct 15 12:53:36 PM UTC 24
Peak memory 210980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467557288 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_ctrl_config_regwen.1467557288
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3633227091
Short name T259
Test name
Test status
Simulation time 870034182 ps
CPU time 5.24 seconds
Started Oct 15 12:53:33 PM UTC 24
Finished Oct 15 12:53:40 PM UTC 24
Peak memory 212416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633227091 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.3633227091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.971406331
Short name T252
Test name
Test status
Simulation time 1201406777 ps
CPU time 2.44 seconds
Started Oct 15 12:53:33 PM UTC 24
Finished Oct 15 12:53:37 PM UTC 24
Peak memory 212448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971406331 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_inters
ig_mubi.971406331
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3559918748
Short name T249
Test name
Test status
Simulation time 56496706 ps
CPU time 1.4 seconds
Started Oct 15 12:53:33 PM UTC 24
Finished Oct 15 12:53:36 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559918748 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3559918748
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.2606535273
Short name T240
Test name
Test status
Simulation time 106786662 ps
CPU time 0.98 seconds
Started Oct 15 12:53:31 PM UTC 24
Finished Oct 15 12:53:33 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606535273 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.2606535273
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.445118303
Short name T273
Test name
Test status
Simulation time 3257405381 ps
CPU time 7.51 seconds
Started Oct 15 12:53:35 PM UTC 24
Finished Oct 15 12:53:44 PM UTC 24
Peak memory 212540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445118303 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.445118303
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.2987253831
Short name T76
Test name
Test status
Simulation time 3690572273 ps
CPU time 15.45 seconds
Started Oct 15 12:53:35 PM UTC 24
Finished Oct 15 12:53:52 PM UTC 24
Peak memory 212644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2987253831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr
_stress_all_with_rand_reset.2987253831
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.2881170638
Short name T229
Test name
Test status
Simulation time 392251223 ps
CPU time 1.35 seconds
Started Oct 15 12:53:32 PM UTC 24
Finished Oct 15 12:53:34 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881170638 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.2881170638
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.1829836102
Short name T245
Test name
Test status
Simulation time 128802565 ps
CPU time 1.44 seconds
Started Oct 15 12:53:32 PM UTC 24
Finished Oct 15 12:53:34 PM UTC 24
Peak memory 210352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829836102 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.1829836102
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/8.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.659570645
Short name T264
Test name
Test status
Simulation time 46850405 ps
CPU time 1.24 seconds
Started Oct 15 12:53:38 PM UTC 24
Finished Oct 15 12:53:40 PM UTC 24
Peak memory 211156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659570645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.659570645
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.3595679417
Short name T182
Test name
Test status
Simulation time 61222296 ps
CPU time 1.26 seconds
Started Oct 15 12:53:39 PM UTC 24
Finished Oct 15 12:53:42 PM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595679417 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disable_rom_integrity_check.3595679417
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.468248520
Short name T260
Test name
Test status
Simulation time 29705020 ps
CPU time 0.74 seconds
Started Oct 15 12:53:38 PM UTC 24
Finished Oct 15 12:53:40 PM UTC 24
Peak memory 209116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468248520 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_malfunc.468248520
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.1492163635
Short name T270
Test name
Test status
Simulation time 205608175 ps
CPU time 1.44 seconds
Started Oct 15 12:53:39 PM UTC 24
Finished Oct 15 12:53:42 PM UTC 24
Peak memory 209240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492163635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.1492163635
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.3113087853
Short name T266
Test name
Test status
Simulation time 52389338 ps
CPU time 0.93 seconds
Started Oct 15 12:53:39 PM UTC 24
Finished Oct 15 12:53:41 PM UTC 24
Peak memory 208932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113087853 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.3113087853
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.10075775
Short name T261
Test name
Test status
Simulation time 44985953 ps
CPU time 0.84 seconds
Started Oct 15 12:53:38 PM UTC 24
Finished Oct 15 12:53:40 PM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10075775 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.10075775
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.1673776755
Short name T272
Test name
Test status
Simulation time 41412687 ps
CPU time 1.12 seconds
Started Oct 15 12:53:41 PM UTC 24
Finished Oct 15 12:53:44 PM UTC 24
Peak memory 210844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673776755 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid.1673776755
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.889494628
Short name T258
Test name
Test status
Simulation time 279939365 ps
CPU time 1.53 seconds
Started Oct 15 12:53:36 PM UTC 24
Finished Oct 15 12:53:39 PM UTC 24
Peak memory 210356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889494628 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wakeup_race.889494628
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2599497693
Short name T256
Test name
Test status
Simulation time 75097620 ps
CPU time 1.54 seconds
Started Oct 15 12:53:36 PM UTC 24
Finished Oct 15 12:53:39 PM UTC 24
Peak memory 210468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599497693 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.2599497693
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.3382513719
Short name T269
Test name
Test status
Simulation time 87737643 ps
CPU time 1.3 seconds
Started Oct 15 12:53:39 PM UTC 24
Finished Oct 15 12:53:42 PM UTC 24
Peak memory 221276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382513719 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.3382513719
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.814207126
Short name T265
Test name
Test status
Simulation time 226876905 ps
CPU time 1.42 seconds
Started Oct 15 12:53:38 PM UTC 24
Finished Oct 15 12:53:40 PM UTC 24
Peak memory 210352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814207126 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_ctrl_config_regwen.814207126
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2039545926
Short name T268
Test name
Test status
Simulation time 2768403848 ps
CPU time 2.64 seconds
Started Oct 15 12:53:38 PM UTC 24
Finished Oct 15 12:53:41 PM UTC 24
Peak memory 212496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039545926 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.2039545926
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3590614606
Short name T267
Test name
Test status
Simulation time 985881918 ps
CPU time 2.35 seconds
Started Oct 15 12:53:38 PM UTC 24
Finished Oct 15 12:53:41 PM UTC 24
Peak memory 212472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590614606 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.3590614606
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2450769265
Short name T263
Test name
Test status
Simulation time 92020155 ps
CPU time 1.05 seconds
Started Oct 15 12:53:38 PM UTC 24
Finished Oct 15 12:53:40 PM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450769265 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2450769265
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.1969217833
Short name T255
Test name
Test status
Simulation time 32808067 ps
CPU time 1.03 seconds
Started Oct 15 12:53:36 PM UTC 24
Finished Oct 15 12:53:38 PM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969217833 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.1969217833
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.2489074619
Short name T115
Test name
Test status
Simulation time 2492667140 ps
CPU time 4.49 seconds
Started Oct 15 12:53:41 PM UTC 24
Finished Oct 15 12:53:47 PM UTC 24
Peak memory 212596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489074619 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.2489074619
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.605111909
Short name T144
Test name
Test status
Simulation time 6028951527 ps
CPU time 6.54 seconds
Started Oct 15 12:53:41 PM UTC 24
Finished Oct 15 12:53:49 PM UTC 24
Peak memory 212940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=605111909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_
stress_all_with_rand_reset.605111909
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.1113192023
Short name T257
Test name
Test status
Simulation time 400974916 ps
CPU time 1.49 seconds
Started Oct 15 12:53:36 PM UTC 24
Finished Oct 15 12:53:39 PM UTC 24
Peak memory 210204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113192023 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.1113192023
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.827031396
Short name T262
Test name
Test status
Simulation time 70348130 ps
CPU time 1.31 seconds
Started Oct 15 12:53:38 PM UTC 24
Finished Oct 15 12:53:40 PM UTC 24
Peak memory 210352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827031396 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.827031396
Directory /workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/9.pwrmgr_wakeup_reset/latest
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