Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	531968	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

209118

1

T1

14

T2

26

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	397252	1			T1	20		T2	87		T3	29
values[0x0]	171668	1			T1	4		T2	30		T3	8
values[0x1]	172166	1			T1	6		T2	20		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	420734	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

320352

1

T1

17

T2

49

T3

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2900	1			T2	5		T5	1		T14	4
valid_sources[0x01]	2006	1			T14	4		T29	3		T36	1
valid_sources[0x02]	2786	1			T14	3		T15	1		T36	1
valid_sources[0x03]	2743	1			T5	1		T13	1		T14	5
valid_sources[0x04]	3038	1			T14	4		T15	1		T33	3
valid_sources[0x05]	2360	1			T13	2		T14	2		T15	2
valid_sources[0x06]	5292	1			T14	1		T15	3		T32	1
valid_sources[0x07]	2154	1			T3	3		T14	5		T15	2
valid_sources[0x08]	3460	1			T2	1		T5	2		T14	4
valid_sources[0x09]	2794	1			T14	2		T15	1		T33	1
valid_sources[0x0a]	3309	1			T13	1		T14	4		T15	2
valid_sources[0x0b]	2621	1			T5	4		T8	5		T14	5
valid_sources[0x0c]	2496	1			T2	7		T14	3		T15	1
valid_sources[0x0d]	2532	1			T5	1		T14	5		T38	45
valid_sources[0x0e]	2315	1			T3	1		T14	2		T29	1
valid_sources[0x0f]	2575	1			T14	3		T29	1		T15	6
valid_sources[0x10]	2951	1			T14	3		T38	54		T29	1
valid_sources[0x11]	5195	1			T5	2		T13	3		T14	7
valid_sources[0x12]	2306	1			T14	3		T29	4		T15	1
valid_sources[0x13]	2694	1			T5	2		T14	7		T15	3
valid_sources[0x14]	8943	1			T14	4		T35	1		T36	1
valid_sources[0x15]	2051	1			T5	2		T14	8		T38	30
valid_sources[0x16]	2213	1			T14	3		T29	1		T15	2
valid_sources[0x17]	2349	1			T2	3		T5	2		T13	2
valid_sources[0x18]	2212	1			T5	4		T14	2		T29	8
valid_sources[0x19]	2340	1			T3	1		T5	2		T14	1
valid_sources[0x1a]	2279	1			T2	2		T14	3		T15	2
valid_sources[0x1b]	2897	1			T3	2		T5	3		T14	2
valid_sources[0x1c]	2835	1			T14	3		T15	2		T33	1
valid_sources[0x1d]	4100	1			T14	4		T29	4		T15	3
valid_sources[0x1e]	2974	1			T4	2		T5	2		T14	3
valid_sources[0x1f]	2275	1			T14	4		T15	4		T32	1
valid_sources[0x20]	2343	1			T3	2		T13	1		T14	2
valid_sources[0x21]	2599	1			T4	1		T14	5		T29	1
valid_sources[0x22]	2392	1			T2	1		T5	4		T14	5
valid_sources[0x23]	3591	1			T14	5		T29	1		T40	8
valid_sources[0x24]	2768	1			T14	3		T38	48		T60	1
valid_sources[0x25]	2145	1			T5	1		T14	3		T15	1
valid_sources[0x26]	2392	1			T2	1		T5	1		T14	5
valid_sources[0x27]	2804	1			T2	1		T3	3		T5	1
valid_sources[0x28]	2400	1			T5	1		T14	4		T15	1
valid_sources[0x29]	2244	1			T5	4		T14	4		T15	2
valid_sources[0x2a]	2533	1			T2	1		T13	1		T14	3
valid_sources[0x2b]	3968	1			T5	3		T14	5		T15	2
valid_sources[0x2c]	2318	1			T2	1		T5	2		T8	11
valid_sources[0x2d]	2333	1			T5	2		T14	6		T29	5
valid_sources[0x2e]	2241	1			T3	1		T14	4		T36	2
valid_sources[0x2f]	2193	1			T5	1		T14	7		T15	2
valid_sources[0x30]	5824	1			T2	1		T14	1		T78	1
valid_sources[0x31]	2137	1			T5	1		T14	1		T38	14
valid_sources[0x32]	2140	1			T5	1		T14	1		T29	4
valid_sources[0x33]	2827	1			T5	1		T14	2		T38	20
valid_sources[0x34]	2581	1			T8	19		T14	5		T15	2
valid_sources[0x35]	3077	1			T5	1		T14	2		T15	1
valid_sources[0x36]	3080	1			T5	3		T15	1		T36	1
valid_sources[0x37]	4016	1			T4	2		T5	2		T14	4
valid_sources[0x38]	3071	1			T3	1		T13	2		T14	4
valid_sources[0x39]	2694	1			T2	2		T5	3		T14	4
valid_sources[0x3a]	2755	1			T4	1		T5	3		T14	9
valid_sources[0x3b]	2289	1			T3	1		T5	1		T14	4
valid_sources[0x3c]	2584	1			T5	6		T14	3		T15	2
valid_sources[0x3d]	2241	1			T5	2		T14	2		T29	3
valid_sources[0x3e]	2814	1			T14	5		T29	8		T32	1
valid_sources[0x3f]	2199	1			T2	2		T5	1		T14	3
valid_sources[0x40]	5450	1			T14	4		T29	3		T15	1
valid_sources[0x41]	2511	1			T14	2		T38	46		T15	1
valid_sources[0x42]	2136	1			T4	1		T5	1		T14	7
valid_sources[0x43]	2088	1			T14	2		T38	25		T40	1
valid_sources[0x44]	2177	1			T14	3		T15	2		T33	1
valid_sources[0x45]	2820	1			T5	2		T14	5		T38	71
valid_sources[0x46]	2682	1			T2	2		T5	1		T14	2
valid_sources[0x47]	2344	1			T5	1		T14	3		T38	49
valid_sources[0x48]	4053	1			T2	1		T14	4		T15	2
valid_sources[0x49]	3161	1			T2	2		T5	1		T14	2
valid_sources[0x4a]	3170	1			T14	1		T15	1		T16	3
valid_sources[0x4b]	3999	1			T5	2		T32	1		T33	1
valid_sources[0x4c]	2444	1			T2	1		T4	1		T5	2
valid_sources[0x4d]	2531	1			T4	3		T7	244		T14	6
valid_sources[0x4e]	3382	1			T5	2		T13	2		T14	3
valid_sources[0x4f]	2642	1			T2	3		T5	1		T13	4
valid_sources[0x50]	2402	1			T5	1		T13	1		T14	1
valid_sources[0x51]	2253	1			T4	1		T5	1		T13	3
valid_sources[0x52]	6318	1			T14	5		T15	3		T36	2
valid_sources[0x53]	2421	1			T8	5		T14	3		T15	4
valid_sources[0x54]	2156	1			T14	2		T29	1		T15	2
valid_sources[0x55]	2727	1			T2	3		T8	18		T14	5
valid_sources[0x56]	2192	1			T4	1		T14	7		T29	1
valid_sources[0x57]	2414	1			T14	3		T15	4		T60	1
valid_sources[0x58]	2134	1			T2	3		T3	2		T5	1
valid_sources[0x59]	3388	1			T5	1		T15	1		T35	3
valid_sources[0x5a]	12372	1			T8	20		T14	4		T38	6
valid_sources[0x5b]	2301	1			T3	2		T14	5		T15	2
valid_sources[0x5c]	2972	1			T5	2		T78	1		T15	2
valid_sources[0x5d]	3458	1			T2	1		T14	1		T29	5
valid_sources[0x5e]	2729	1			T2	1		T14	3		T15	1
valid_sources[0x5f]	2207	1			T14	5		T29	1		T40	4
valid_sources[0x60]	2209	1			T5	3		T8	37		T14	3
valid_sources[0x61]	2238	1			T1	30		T2	3		T5	1
valid_sources[0x62]	2375	1			T5	1		T14	1		T38	34
valid_sources[0x63]	2001	1			T2	2		T15	2		T21	2
valid_sources[0x64]	2358	1			T13	6		T14	3		T29	2
valid_sources[0x65]	3302	1			T3	1		T14	3		T15	1
valid_sources[0x66]	3557	1			T14	3		T29	1		T15	1
valid_sources[0x67]	4494	1			T14	2		T36	1		T60	2
valid_sources[0x68]	5167	1			T14	5		T15	3		T36	1
valid_sources[0x69]	2559	1			T14	8		T15	1		T36	3
valid_sources[0x6a]	2190	1			T14	2		T15	2		T32	2
valid_sources[0x6b]	2531	1			T14	1		T15	1		T33	3
valid_sources[0x6c]	3253	1			T2	2		T5	3		T14	5
valid_sources[0x6d]	3237	1			T3	3		T14	2		T15	1
valid_sources[0x6e]	2348	1			T3	1		T5	2		T14	3
valid_sources[0x6f]	2271	1			T11	1		T14	4		T29	1
valid_sources[0x70]	2313	1			T4	2		T13	1		T14	8
valid_sources[0x71]	2466	1			T2	2		T14	5		T15	2
valid_sources[0x72]	3310	1			T4	4		T5	3		T8	21
valid_sources[0x73]	2960	1			T14	5		T33	1		T36	2
valid_sources[0x74]	2379	1			T5	2		T14	5		T15	2
valid_sources[0x75]	2290	1			T4	2		T5	1		T14	4
valid_sources[0x76]	2313	1			T2	3		T5	1		T13	3
valid_sources[0x77]	2321	1			T14	3		T29	5		T15	2
valid_sources[0x78]	2153	1			T14	7		T29	1		T15	2
valid_sources[0x79]	2411	1			T14	2		T29	5		T40	11
valid_sources[0x7a]	2126	1			T14	5		T15	2		T32	1
valid_sources[0x7b]	2660	1			T5	3		T14	7		T29	1
valid_sources[0x7c]	2254	1			T5	2		T13	1		T14	5
valid_sources[0x7d]	2210	1			T14	3		T29	1		T15	2
valid_sources[0x7e]	3733	1			T14	6		T29	8		T15	4
valid_sources[0x7f]	2322	1			T5	3		T14	7		T29	1
valid_sources[0x80]	2224	1			T5	1		T14	2		T29	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

110065

1

T1

11

T2

13

T3

13

values[0x0]

all_enables

biggest_size

64287

1

T1

1

T2

10

T3

1

values[0x1]

all_enables

biggest_size

34766

1

T1

2

T2

3

T3

2