Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	400941	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

158696

1

T1

8

T2

39

T3

60

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	295049	1			T1	14		T2	128		T3	115
values[0x0]	131992	1			T1	4		T2	43		T3	67
values[0x1]	132596	1			T1	6		T2	39		T3	67

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	317342	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

242295

1

T1

10

T2

76

T3

104

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1737	1			T8	3		T31	1		T15	1
valid_sources[0x01]	1652	1			T8	5		T37	4		T15	1
valid_sources[0x02]	1805	1			T7	1		T8	8		T37	4
valid_sources[0x03]	1759	1			T3	1		T7	1		T8	6
valid_sources[0x04]	1655	1			T7	1		T8	3		T37	4
valid_sources[0x05]	2671	1			T3	2		T7	1		T8	4
valid_sources[0x06]	2413	1			T3	2		T7	2		T8	6
valid_sources[0x07]	3917	1			T6	1		T8	10		T10	2
valid_sources[0x08]	2291	1			T3	1		T8	4		T37	2
valid_sources[0x09]	2129	1			T3	1		T7	1		T8	2
valid_sources[0x0a]	1752	1			T3	1		T6	2		T7	2
valid_sources[0x0b]	3253	1			T7	1		T37	4		T34	1
valid_sources[0x0c]	1664	1			T8	2		T37	4		T15	2
valid_sources[0x0d]	1705	1			T6	1		T7	1		T8	3
valid_sources[0x0e]	3540	1			T6	1		T8	2		T10	23
valid_sources[0x0f]	1700	1			T1	1		T7	3		T8	2
valid_sources[0x10]	1687	1			T3	3		T6	1		T7	1
valid_sources[0x11]	2187	1			T3	1		T7	1		T8	2
valid_sources[0x12]	1953	1			T3	3		T6	3		T8	7
valid_sources[0x13]	1915	1			T3	5		T6	2		T8	3
valid_sources[0x14]	2255	1			T7	1		T8	2		T37	4
valid_sources[0x15]	3632	1			T7	1		T8	3		T37	6
valid_sources[0x16]	1844	1			T3	2		T7	3		T37	3
valid_sources[0x17]	1668	1			T8	3		T37	4		T33	1
valid_sources[0x18]	1728	1			T1	1		T7	1		T8	6
valid_sources[0x19]	1789	1			T8	4		T37	2		T15	1
valid_sources[0x1a]	1565	1			T3	3		T6	3		T7	1
valid_sources[0x1b]	1920	1			T6	1		T8	6		T37	3
valid_sources[0x1c]	1922	1			T6	2		T7	2		T8	3
valid_sources[0x1d]	1865	1			T1	1		T3	3		T6	3
valid_sources[0x1e]	1698	1			T3	1		T7	1		T8	5
valid_sources[0x1f]	1753	1			T3	7		T4	1		T7	2
valid_sources[0x20]	1672	1			T3	4		T6	4		T8	7
valid_sources[0x21]	1698	1			T6	1		T8	6		T37	4
valid_sources[0x22]	2073	1			T3	1		T7	3		T8	3
valid_sources[0x23]	1683	1			T3	7		T8	4		T37	4
valid_sources[0x24]	1944	1			T3	1		T7	3		T8	1
valid_sources[0x25]	1937	1			T6	1		T7	1		T8	2
valid_sources[0x26]	1765	1			T8	3		T13	1		T37	5
valid_sources[0x27]	1515	1			T7	2		T37	5		T33	1
valid_sources[0x28]	1754	1			T1	7		T3	2		T6	1
valid_sources[0x29]	2354	1			T3	4		T6	1		T8	13
valid_sources[0x2a]	3300	1			T3	2		T6	4		T7	2
valid_sources[0x2b]	1858	1			T7	1		T8	3		T10	7
valid_sources[0x2c]	3100	1			T6	2		T8	3		T37	6
valid_sources[0x2d]	1764	1			T7	2		T8	3		T37	2
valid_sources[0x2e]	2895	1			T7	4		T8	2		T37	3
valid_sources[0x2f]	2224	1			T2	210		T3	3		T7	2
valid_sources[0x30]	1778	1			T8	3		T37	5		T15	1
valid_sources[0x31]	1674	1			T3	1		T6	1		T8	6
valid_sources[0x32]	2091	1			T7	1		T8	1		T37	5
valid_sources[0x33]	1986	1			T3	1		T8	5		T37	5
valid_sources[0x34]	2934	1			T7	1		T8	2		T37	3
valid_sources[0x35]	1876	1			T3	1		T6	1		T7	2
valid_sources[0x36]	1762	1			T8	2		T37	4		T33	3
valid_sources[0x37]	1857	1			T5	42		T7	2		T8	5
valid_sources[0x38]	3063	1			T7	2		T8	6		T10	18
valid_sources[0x39]	2314	1			T6	11		T8	4		T14	3
valid_sources[0x3a]	1558	1			T6	4		T7	1		T8	4
valid_sources[0x3b]	1581	1			T8	4		T37	4		T33	1
valid_sources[0x3c]	2069	1			T1	2		T4	93		T7	2
valid_sources[0x3d]	2360	1			T6	1		T7	2		T8	5
valid_sources[0x3e]	1511	1			T8	5		T37	1		T23	4
valid_sources[0x3f]	1682	1			T8	6		T37	6		T31	1
valid_sources[0x40]	3819	1			T8	6		T14	1		T37	8
valid_sources[0x41]	1936	1			T1	1		T3	2		T8	4
valid_sources[0x42]	2006	1			T3	5		T7	1		T8	2
valid_sources[0x43]	1664	1			T3	1		T6	2		T7	1
valid_sources[0x44]	1538	1			T7	1		T8	1		T37	6
valid_sources[0x45]	1938	1			T7	3		T8	3		T37	5
valid_sources[0x46]	2173	1			T3	2		T6	1		T7	3
valid_sources[0x47]	2710	1			T3	2		T14	3		T37	4
valid_sources[0x48]	1875	1			T3	2		T8	9		T37	2
valid_sources[0x49]	1641	1			T7	2		T8	5		T37	1
valid_sources[0x4a]	1773	1			T3	1		T7	4		T37	5
valid_sources[0x4b]	2360	1			T3	3		T8	1		T33	1
valid_sources[0x4c]	3313	1			T7	1		T8	2		T14	8
valid_sources[0x4d]	2056	1			T6	1		T7	1		T8	2
valid_sources[0x4e]	3525	1			T3	2		T6	1		T7	1
valid_sources[0x4f]	1779	1			T3	1		T8	4		T37	6
valid_sources[0x50]	4796	1			T8	3		T37	3		T33	2
valid_sources[0x51]	1554	1			T8	4		T14	3		T37	6
valid_sources[0x52]	2041	1			T3	6		T8	2		T37	2
valid_sources[0x53]	2086	1			T3	4		T7	1		T8	1
valid_sources[0x54]	1963	1			T3	1		T6	2		T7	3
valid_sources[0x55]	3099	1			T8	5		T37	6		T33	1
valid_sources[0x56]	1727	1			T3	3		T7	1		T8	5
valid_sources[0x57]	1646	1			T7	1		T8	4		T37	1
valid_sources[0x58]	2245	1			T6	2		T7	2		T8	2
valid_sources[0x59]	2958	1			T4	13		T6	3		T7	2
valid_sources[0x5a]	2515	1			T6	1		T7	3		T8	7
valid_sources[0x5b]	1821	1			T7	1		T8	2		T37	3
valid_sources[0x5c]	2953	1			T6	1		T8	5		T37	2
valid_sources[0x5d]	1784	1			T7	1		T8	2		T37	4
valid_sources[0x5e]	1716	1			T7	3		T8	7		T37	3
valid_sources[0x5f]	1705	1			T8	3		T37	5		T15	1
valid_sources[0x60]	1706	1			T6	1		T7	1		T8	2
valid_sources[0x61]	2605	1			T7	1		T8	1		T23	4
valid_sources[0x62]	1660	1			T8	12		T37	6		T33	2
valid_sources[0x63]	1519	1			T8	9		T37	4		T33	1
valid_sources[0x64]	1686	1			T3	1		T6	1		T7	1
valid_sources[0x65]	3156	1			T8	3		T37	2		T33	3
valid_sources[0x66]	1708	1			T6	1		T7	2		T8	3
valid_sources[0x67]	2059	1			T3	1		T7	1		T8	3
valid_sources[0x68]	4811	1			T7	2		T8	6		T10	6
valid_sources[0x69]	2202	1			T3	1		T7	1		T8	3
valid_sources[0x6a]	2171	1			T3	2		T7	2		T8	4
valid_sources[0x6b]	3190	1			T7	2		T37	5		T33	2
valid_sources[0x6c]	2984	1			T7	1		T8	3		T37	4
valid_sources[0x6d]	1890	1			T3	1		T8	3		T37	4
valid_sources[0x6e]	1757	1			T3	1		T7	2		T8	4
valid_sources[0x6f]	2118	1			T7	1		T8	6		T37	8
valid_sources[0x70]	4593	1			T8	3		T37	3		T23	12
valid_sources[0x71]	2647	1			T7	1		T8	3		T15	1
valid_sources[0x72]	1839	1			T3	2		T6	1		T8	3
valid_sources[0x73]	1663	1			T6	6		T8	2		T37	2
valid_sources[0x74]	1776	1			T7	1		T8	1		T37	2
valid_sources[0x75]	1520	1			T3	1		T8	3		T10	2
valid_sources[0x76]	1872	1			T3	3		T7	1		T8	4
valid_sources[0x77]	1550	1			T4	60		T7	1		T37	1
valid_sources[0x78]	2222	1			T3	1		T6	3		T7	4
valid_sources[0x79]	1785	1			T3	1		T8	3		T37	1
valid_sources[0x7a]	1682	1			T4	35		T8	5		T34	1
valid_sources[0x7b]	1778	1			T7	1		T8	2		T14	2
valid_sources[0x7c]	1626	1			T7	2		T8	6		T37	4
valid_sources[0x7d]	1786	1			T37	2		T33	1		T15	2
valid_sources[0x7e]	4556	1			T6	4		T7	1		T8	2
valid_sources[0x7f]	1799	1			T7	2		T8	2		T37	4
valid_sources[0x80]	1769	1			T3	3		T7	1		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

81007

1

T1

5

T2

15

T3

25

values[0x0]

all_enables

biggest_size

49902

1

T1

1

T2

15

T3

27

values[0x1]

all_enables

biggest_size

27787

1

T1

2

T2

9

T3

8