SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35009 | 1 | T8 | 275 | T37 | 364 | T26 | 304 | ||||
others[1] | 35107 | 1 | T8 | 332 | T14 | 1 | T37 | 418 | ||||
others[2] | 35145 | 1 | T8 | 285 | T37 | 392 | T26 | 303 | ||||
others[3] | 58191 | 1 | T8 | 507 | T37 | 687 | T23 | 1 | ||||
false | 14531 | 1 | T5 | 4 | T8 | 50 | T14 | 3 | ||||
true | 23367 | 1 | T1 | 1 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35177 | 1 | T8 | 297 | T37 | 368 | T26 | 300 | ||||
others[1] | 34914 | 1 | T8 | 313 | T14 | 1 | T37 | 381 | ||||
others[2] | 35225 | 1 | T8 | 298 | T37 | 435 | T23 | 2 | ||||
others[3] | 58176 | 1 | T8 | 502 | T37 | 692 | T26 | 502 | ||||
false | 9877 | 1 | T5 | 2 | T8 | 50 | T14 | 3 | ||||
true | 18773 | 1 | T1 | 1 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 590 | 1 | T2 | 1 | T7 | 4 | T32 | 1 | ||||
others[1] | 566 | 1 | T2 | 1 | T7 | 8 | T32 | 2 | ||||
others[2] | 560 | 1 | T2 | 1 | T7 | 7 | T14 | 1 | ||||
others[3] | 963 | 1 | T2 | 4 | T7 | 6 | T14 | 2 | ||||
false | 10908 | 1 | T1 | 1 | T2 | 16 | T3 | 1 | ||||
true | 2994 | 1 | T2 | 7 | T7 | 4 | T14 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |