Unified Coverage Report :: Module :: prim_generic_flop

Module : prim_generic_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ndm_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_ndm_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_esc_timeout.u_out.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_esc_timeout_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_esc_timeout_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_cfg_cdc_sync0_qe.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_req_pwrdn_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_req_pwrdn_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ack_pwrup_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ack_pwrup_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_slow_ext_req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_slow_ext_req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ip_clk_status_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ip_clk_status_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ast_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ast_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_req_pwrup_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_req_pwrup_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ack_pwrdn_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ack_pwrdn_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_int_fsm_invalid_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_int_fsm_invalid_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_pwrup_chg_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_pwrup_chg_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ip_clk_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ip_clk_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sleeping_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sleeping_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ext_req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_ext_req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sync_flash_idle.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sync_flash_idle.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sync_otp.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sync_otp.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_clr_req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_cdc.u_clr_req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_slow_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_slow_fsm.u_main_pok_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_slow_fsm.u_main_pok_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_slow_fsm.u_usb_clk_en.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_fetch_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_slow_sync_lc_done.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_slow_sync_lc_done.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_sync_lc_done.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_sync_lc_done.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_usb_ip_clk_en.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_reg_otp_init.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_fsm.u_reg_lc_init.gen_generic.u_impl_generic	100.00	100.00				100.00

---

Module Instance : tb.dut.u_ndm_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ndm_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_esc_timeout.u_out.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_out

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_esc_timeout_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_esc_timeout_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_cfg_cdc_sync0_qe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_cfg_cdc_sync0_qe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_req_pwrdn_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_req_pwrdn_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_ack_pwrup_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_ack_pwrup_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_slow_ext_req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_slow_ext_req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_ip_clk_status_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_ip_clk_status_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_ast_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_ast_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_req_pwrup_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_req_pwrup_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_ack_pwrdn_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_ack_pwrdn_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_int_fsm_invalid_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_int_fsm_invalid_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_pwrup_chg_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_pwrup_chg_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_ip_clk_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_ip_clk_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_sleeping_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_sleeping_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_ext_req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_ext_req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_sync_flash_idle.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_sync_flash_idle.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_sync_otp.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_sync_otp.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.gen_stable_chks.u_prim_flop_3rd_stage

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_clr_req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_cdc.u_clr_req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_slow_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_state_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_slow_fsm.u_main_pok_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_slow_fsm.u_main_pok_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_slow_fsm.u_usb_clk_en.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_usb_clk_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_state_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fsm.u_fetch_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_flop

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fsm.u_slow_sync_lc_done.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fsm.u_slow_sync_lc_done.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fsm.u_sync_lc_done.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fsm.u_sync_lc_done.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_sync_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fsm.u_usb_ip_clk_en.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_usb_ip_clk_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fsm.u_reg_otp_init.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_reg_otp_init

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fsm.u_reg_lc_init.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_reg_lc_init

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_flop

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Module : prim_generic_flop

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_ndm_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_ndm_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_ndm_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_ndm_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_esc_timeout.u_ref_timeout.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_esc_timeout.u_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_esc_timeout.u_out.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_esc_timeout_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_esc_timeout_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_esc_timeout_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_esc_timeout_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cfg_cdc_sync0_qe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_reg.u_cfg_cdc_sync0_qe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_req_pwrdn_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_req_pwrdn_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_req_pwrdn_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_req_pwrdn_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ack_pwrup_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_ack_pwrup_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ack_pwrup_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_ack_pwrup_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_slow_cdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_slow_ext_req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_slow_ext_req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_slow_ext_req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_slow_ext_req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ip_clk_status_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_ip_clk_status_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ip_clk_status_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_ip_clk_status_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ast_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_ast_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ast_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_ast_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_req_pwrup_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_req_pwrup_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_req_pwrup_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_req_pwrup_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ack_pwrdn_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_ack_pwrdn_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ack_pwrdn_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_ack_pwrdn_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_int_fsm_invalid_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_int_fsm_invalid_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_int_fsm_invalid_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_int_fsm_invalid_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_pwrup_chg_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_pwrup_chg_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_pwrup_chg_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_pwrup_chg_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ip_clk_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_ip_clk_en_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ip_clk_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_ip_clk_en_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sleeping_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_sleeping_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sleeping_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_sleeping_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_scdc_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ext_req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_ext_req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_ext_req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_ext_req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_flash_idle.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_sync_flash_idle.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_flash_idle.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_sync_flash_idle.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_otp.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_sync_otp.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_otp.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_sync_otp.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.u_prim_flop_3rd_stage.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_clr_req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_clr_req_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_cdc.u_clr_req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_cdc.u_clr_req_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_slow_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_slow_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_slow_fsm.u_main_pok_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_slow_fsm.u_main_pok_sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_slow_fsm.u_main_pok_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_slow_fsm.u_main_pok_sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_slow_fsm.u_usb_clk_en.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_slow_fsm.u_usb_clk_en.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_fetch_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_fsm.u_fetch_en.gen_flops.u_prim_flop.u_secure_anchor_flop.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_slow_sync_lc_done.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_fsm.u_slow_sync_lc_done.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_slow_sync_lc_done.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_fsm.u_slow_sync_lc_done.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_sync_lc_done.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_fsm.u_sync_lc_done.gen_generic.u_impl_generic.u_sync_1.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_sync_lc_done.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_fsm.u_sync_lc_done.gen_generic.u_impl_generic.u_sync_2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_usb_ip_clk_en.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_fsm.u_usb_ip_clk_en.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_reg_otp_init.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_fsm.u_reg_otp_init.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_fsm.u_reg_lc_init.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

17                        always_ff @(posedge clk_i or negedge rst_ni) begin
18         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
19         1/1                q_o <= ResetValue;
           Tests:       T1 T2 T3 
20                          end else begin
21         1/1                q_o <= d_i;
           Tests:       T1 T2 T3 

---

Branch Coverage for Instance : tb.dut.u_fsm.u_reg_lc_init.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

18             if (!rst_ni) begin
               -1-  
19               q_o <= ResetValue;
                 ==>
20             end else begin
21               q_o <= d_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3