Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T38,T40

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	23247996	6348	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	23247996	254179	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	23247996	9452395	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	23247996	254198	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	23247996	6348	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	23247996	254179	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	23247996	9452395	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	23247996	254198	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	6348	0	0
T1	2458	1	0	0
T2	3451	0	0	0
T3	1983	0	0	0
T4	3429	0	0	0
T5	7593	6	0	0
T6	2288	0	0	0
T7	3960	0	0	0
T8	2262	0	0	0
T9	5328	0	0	0
T10	1299	0	0	0
T14	0	23	0	0
T33	0	6	0	0
T38	0	23	0	0
T40	0	2	0	0
T44	0	1	0	0
T78	0	1	0	0
T79	0	24	0	0
T80	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	254179	0	0
T1	2458	12	0	0
T2	3451	0	0	0
T3	1983	0	0	0
T4	3429	0	0	0
T5	7593	147	0	0
T6	2288	0	0	0
T7	3960	0	0	0
T8	2262	0	0	0
T9	5328	0	0	0
T10	1299	0	0	0
T14	0	595	0	0
T33	0	134	0	0
T38	0	641	0	0
T40	0	463	0	0
T44	0	111	0	0
T78	0	11	0	0
T79	0	1569	0	0
T80	0	13	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	9452395	0	0
T1	2458	1517	0	0
T2	3451	0	0	0
T3	1983	0	0	0
T4	3429	0	0	0
T5	7593	3445	0	0
T6	2288	0	0	0
T7	3960	0	0	0
T8	2262	444	0	0
T9	5328	2949	0	0
T10	1299	0	0	0
T14	0	8450	0	0
T15	0	3382	0	0
T32	0	1875	0	0
T38	0	14078	0	0
T40	0	236	0	0
T78	0	1029	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	254198	0	0
T1	2458	12	0	0
T2	3451	0	0	0
T3	1983	0	0	0
T4	3429	0	0	0
T5	7593	147	0	0
T6	2288	0	0	0
T7	3960	0	0	0
T8	2262	0	0	0
T9	5328	0	0	0
T10	1299	0	0	0
T14	0	595	0	0
T33	0	134	0	0
T38	0	641	0	0
T40	0	463	0	0
T44	0	111	0	0
T78	0	11	0	0
T79	0	1569	0	0
T80	0	13	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	6348	0	0
T1	2458	1	0	0
T2	3451	0	0	0
T3	1983	0	0	0
T4	3429	0	0	0
T5	7593	6	0	0
T6	2288	0	0	0
T7	3960	0	0	0
T8	2262	0	0	0
T9	5328	0	0	0
T10	1299	0	0	0
T14	0	23	0	0
T33	0	6	0	0
T38	0	23	0	0
T40	0	2	0	0
T44	0	1	0	0
T78	0	1	0	0
T79	0	24	0	0
T80	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	254179	0	0
T1	2458	12	0	0
T2	3451	0	0	0
T3	1983	0	0	0
T4	3429	0	0	0
T5	7593	147	0	0
T6	2288	0	0	0
T7	3960	0	0	0
T8	2262	0	0	0
T9	5328	0	0	0
T10	1299	0	0	0
T14	0	595	0	0
T33	0	134	0	0
T38	0	641	0	0
T40	0	463	0	0
T44	0	111	0	0
T78	0	11	0	0
T79	0	1569	0	0
T80	0	13	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	9452395	0	0
T1	2458	1517	0	0
T2	3451	0	0	0
T3	1983	0	0	0
T4	3429	0	0	0
T5	7593	3445	0	0
T6	2288	0	0	0
T7	3960	0	0	0
T8	2262	444	0	0
T9	5328	2949	0	0
T10	1299	0	0	0
T14	0	8450	0	0
T15	0	3382	0	0
T32	0	1875	0	0
T38	0	14078	0	0
T40	0	236	0	0
T78	0	1029	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	254198	0	0
T1	2458	12	0	0
T2	3451	0	0	0
T3	1983	0	0	0
T4	3429	0	0	0
T5	7593	147	0	0
T6	2288	0	0	0
T7	3960	0	0	0
T8	2262	0	0	0
T9	5328	0	0	0
T10	1299	0	0	0
T14	0	595	0	0
T33	0	134	0	0
T38	0	641	0	0
T40	0	463	0	0
T44	0	111	0	0
T78	0	11	0	0
T79	0	1569	0	0
T80	0	13	0	0