Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23814782	18325	0	0
intr_enable_rd_A	23814782	26920	0	0
reset_en_rd_A	23814782	1146	0	0
reset_en_regwen_rd_A	23814782	894	0	0
wake_info_capture_dis_rd_A	23814782	1061	0	0
wakeup_en_rd_A	23814782	1929	0	0
wakeup_en_regwen_rd_A	23814782	969	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23814782	18325	0	0
T24	378020	30	0	0
T25	0	18	0	0
T26	0	8	0	0
T46	0	72	0	0
T49	0	68	0	0
T50	0	2	0	0
T59	0	133	0	0
T89	0	19	0	0
T108	72911	0	0	0
T130	0	20	0	0
T131	0	23	0	0
T132	15753	0	0	0
T133	1819	0	0	0
T134	2405	0	0	0
T135	5008	0	0	0
T136	54342	0	0	0
T137	9035	0	0	0
T138	2079	0	0	0
T139	2632	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23814782	26920	0	0
T1	2458	8	0	0
T2	3451	0	0	0
T3	1983	0	0	0
T4	3429	6	0	0
T5	7593	0	0	0
T6	2288	0	0	0
T7	3960	109	0	0
T8	2262	0	0	0
T9	5328	9	0	0
T10	1299	0	0	0
T16	0	13	0	0
T38	0	201	0	0
T61	0	32	0	0
T82	0	72	0	0
T140	0	62	0	0
T141	0	107	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23814782	1146	0	0
T57	0	78	0	0
T63	0	139	0	0
T66	0	18	0	0
T113	0	5	0	0
T124	0	15	0	0
T142	205261	9	0	0
T143	0	11	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	7	0	0
T147	2286	0	0	0
T148	5733	0	0	0
T149	4137	0	0	0
T150	1333	0	0	0
T151	4991	0	0	0
T152	2406	0	0	0
T153	1711	0	0	0
T154	2955	0	0	0
T155	4974	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23814782	894	0	0
T53	0	1	0	0
T57	0	38	0	0
T63	0	110	0	0
T66	0	24	0	0
T113	0	12	0	0
T142	205261	6	0	0
T143	0	22	0	0
T145	0	5	0	0
T146	0	6	0	0
T147	2286	0	0	0
T148	5733	0	0	0
T149	4137	0	0	0
T150	1333	0	0	0
T151	4991	0	0	0
T152	2406	0	0	0
T153	1711	0	0	0
T154	2955	0	0	0
T155	4974	0	0	0
T156	0	8	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23814782	1061	0	0
T53	0	3	0	0
T57	0	41	0	0
T63	0	140	0	0
T66	0	23	0	0
T113	0	13	0	0
T142	205261	5	0	0
T143	0	18	0	0
T144	0	3	0	0
T145	0	4	0	0
T147	2286	0	0	0
T148	5733	0	0	0
T149	4137	0	0	0
T150	1333	0	0	0
T151	4991	0	0	0
T152	2406	0	0	0
T153	1711	0	0	0
T154	2955	0	0	0
T155	4974	0	0	0
T156	0	7	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23814782	1929	0	0
T53	0	9	0	0
T57	0	146	0	0
T63	0	107	0	0
T66	0	18	0	0
T113	0	39	0	0
T142	205261	14	0	0
T143	0	11	0	0
T144	0	16	0	0
T145	0	9	0	0
T146	0	1	0	0
T147	2286	0	0	0
T148	5733	0	0	0
T149	4137	0	0	0
T150	1333	0	0	0
T151	4991	0	0	0
T152	2406	0	0	0
T153	1711	0	0	0
T154	2955	0	0	0
T155	4974	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23814782	969	0	0
T53	0	4	0	0
T57	0	27	0	0
T63	0	114	0	0
T66	0	9	0	0
T113	0	6	0	0
T142	205261	1	0	0
T143	0	5	0	0
T144	0	6	0	0
T145	0	9	0	0
T146	0	3	0	0
T147	2286	0	0	0
T148	5733	0	0	0
T149	4137	0	0	0
T150	1333	0	0	0
T151	4991	0	0	0
T152	2406	0	0	0
T153	1711	0	0	0
T154	2955	0	0	0
T155	4974	0	0	0