Unified Coverage Report :: Module :: prim_clock_timeout

Module : prim_clock_timeout

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	100.00			75.00

Source File(s) :
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_esc_timeout	91.67	100.00	100.00			75.00

---

Module Instance : tb.dut.u_esc_timeout

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	100.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.79	100.00	75.00			96.15	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_out	100.00	100.00				100.00
u_ref_timeout	90.00	100.00	60.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_clock_timeout

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	30	0	0
ALWAYS	32	7	7	100.00

29                        logic timeout;
30         unreachable    assign timeout = int'(cnt) >= TimeOutCnt;
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
33         1/1                cnt <= '0;
           Tests:       T1 T2 T3 
34         1/1              end else if (ack || !en_i) begin
           Tests:       T1 T2 T3 
35         1/1                cnt <= '0;
           Tests:       T1 T2 T3 
36         1/1              end else if (timeout) begin
           Tests:       T1 T2 T3 
37         unreachable        cnt <= '{default: '1};
38         1/1              end else if (en_i) begin
           Tests:       T1 T2 T3 
39         1/1                cnt <= cnt + 1'b1;
           Tests:       T1 T2 T3 
40                          end
                   ==>  MISSING_ELSE

---

Cond Coverage for Module : prim_clock_timeout

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_clock_timeout

	Line No.	Total	Covered	Percent
Branches		4	3	75.00
IF	32	4	3	75.00

32             if (!rst_ni) begin
               -1-  
33               cnt <= '0;
                 ==>
34             end else if (ack || !en_i) begin
                        -2-  
35               cnt <= '0;
                 ==>
36             end else if (timeout) begin
                        -3-  
37               cnt <= '{default: '1};
                 ==> (Unreachable)
38             end else if (en_i) begin
                        -4-  
39               cnt <= cnt + 1'b1;
                 ==>
40             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Unreachable	T6,T11,T12
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Not Covered