Unified Coverage Report :: Module :: prim_buf

Module : prim_buf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_abstract_buf_0/prim_buf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sw_req_buf
tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf
tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf
tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

---

Module Instance : tb.dut.u_sw_req_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_sync_rom_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_sync_rom_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_sync_rom_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_sync_rom_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	100.00	100.00