Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	69743988	148888	0	0
StatusRise_A	69743988	166084	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69743988	148888	0	0
T1	7374	6	0	0
T2	10353	51	0	0
T3	5949	6	0	0
T4	10287	11	0	0
T5	22779	64	0	0
T6	6864	3	0	0
T7	11880	3	0	0
T8	6786	51	0	0
T9	15984	12	0	0
T10	3897	0	0	0
T13	0	15	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69743988	166084	0	0
T1	7374	9	0	0
T2	10353	54	0	0
T3	5949	9	0	0
T4	10287	13	0	0
T5	22779	67	0	0
T6	6864	9	0	0
T7	11880	6	0	0
T8	6786	53	0	0
T9	15984	14	0	0
T10	3897	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23247996	55244	0	0
StatusRise_A	23247996	61454	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	55244	0	0
T1	2458	2	0	0
T2	3451	17	0	0
T3	1983	2	0	0
T4	3429	4	0	0
T5	7593	24	0	0
T6	2288	1	0	0
T7	3960	1	0	0
T8	2262	18	0	0
T9	5328	4	0	0
T10	1299	0	0	0
T13	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	61454	0	0
T1	2458	3	0	0
T2	3451	18	0	0
T3	1983	3	0	0
T4	3429	5	0	0
T5	7593	25	0	0
T6	2288	3	0	0
T7	3960	2	0	0
T8	2262	19	0	0
T9	5328	5	0	0
T10	1299	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23247996	55244	0	0
StatusRise_A	23247996	61460	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	55244	0	0
T1	2458	2	0	0
T2	3451	17	0	0
T3	1983	2	0	0
T4	3429	4	0	0
T5	7593	24	0	0
T6	2288	1	0	0
T7	3960	1	0	0
T8	2262	18	0	0
T9	5328	4	0	0
T10	1299	0	0	0
T13	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	61460	0	0
T1	2458	3	0	0
T2	3451	18	0	0
T3	1983	3	0	0
T4	3429	5	0	0
T5	7593	25	0	0
T6	2288	3	0	0
T7	3960	2	0	0
T8	2262	19	0	0
T9	5328	5	0	0
T10	1299	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23247996	38400	0	0
StatusRise_A	23247996	43170	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	38400	0	0
T1	2458	2	0	0
T2	3451	17	0	0
T3	1983	2	0	0
T4	3429	3	0	0
T5	7593	16	0	0
T6	2288	1	0	0
T7	3960	1	0	0
T8	2262	15	0	0
T9	5328	4	0	0
T10	1299	0	0	0
T13	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	43170	0	0
T1	2458	3	0	0
T2	3451	18	0	0
T3	1983	3	0	0
T4	3429	3	0	0
T5	7593	17	0	0
T6	2288	3	0	0
T7	3960	2	0	0
T8	2262	15	0	0
T9	5328	4	0	0
T10	1299	4	0	0