Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	83.87	99.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	52969803	111039	0	0
StatusRise_A	52969803	124792	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52969803	111039	0	0
T1	4392	6	0	0
T2	7995	63	0	0
T3	11490	45	0	0
T4	51195	50	0	0
T5	5130	12	0	0
T6	9750	27	0	0
T7	20844	12	0	0
T8	50073	214	0	0
T9	7314	3	0	0
T10	19944	25	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52969803	124792	0	0
T1	4392	9	0	0
T2	7995	69	0	0
T3	11490	47	0	0
T4	51195	52	0	0
T5	5130	15	0	0
T6	9750	29	0	0
T7	20844	15	0	0
T8	50073	216	0	0
T9	7314	9	0	0
T10	19944	28	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17656601	41317	0	0
StatusRise_A	17656601	46242	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	41317	0	0
T1	1464	2	0	0
T2	2665	21	0	0
T3	3830	19	0	0
T4	17065	18	0	0
T5	1710	4	0	0
T6	3250	10	0	0
T7	6948	4	0	0
T8	16691	84	0	0
T9	2438	1	0	0
T10	6648	10	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	46242	0	0
T1	1464	3	0	0
T2	2665	23	0	0
T3	3830	20	0	0
T4	17065	19	0	0
T5	1710	5	0	0
T6	3250	11	0	0
T7	6948	5	0	0
T8	16691	85	0	0
T9	2438	3	0	0
T10	6648	11	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17656601	41317	0	0
StatusRise_A	17656601	46241	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	41317	0	0
T1	1464	2	0	0
T2	2665	21	0	0
T3	3830	19	0	0
T4	17065	18	0	0
T5	1710	4	0	0
T6	3250	10	0	0
T7	6948	4	0	0
T8	16691	84	0	0
T9	2438	1	0	0
T10	6648	10	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	46241	0	0
T1	1464	3	0	0
T2	2665	23	0	0
T3	3830	20	0	0
T4	17065	19	0	0
T5	1710	5	0	0
T6	3250	11	0	0
T7	6948	5	0	0
T8	16691	85	0	0
T9	2438	3	0	0
T10	6648	11	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	17656601	28405	0	0
StatusRise_A	17656601	32309	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	28405	0	0
T1	1464	2	0	0
T2	2665	21	0	0
T3	3830	7	0	0
T4	17065	14	0	0
T5	1710	4	0	0
T6	3250	7	0	0
T7	6948	4	0	0
T8	16691	46	0	0
T9	2438	1	0	0
T10	6648	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17656601	32309	0	0
T1	1464	3	0	0
T2	2665	23	0	0
T3	3830	7	0	0
T4	17065	14	0	0
T5	1710	5	0	0
T6	3250	7	0	0
T7	6948	5	0	0
T8	16691	46	0	0
T9	2438	3	0	0
T10	6648	6	0	0