Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

41                      
42         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T1 T2 T3 
43         1/1            always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva;
           Tests:       T1 T2 T3 
44         1/1            always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	23248606	6204	0	0
EscTimeoutStoppedByClReset_A	23247996	3303603	0	0
EscTimeoutTriggersReset_A	5144859	323	0	0
RomAllowActiveState_A	23247996	61053	0	0
RomAllowCheckGoodState_A	23247996	61103	0	0
RomBlockActiveState_A	23247996	26218	0	0
RomBlockCheckGoodState_A	23247996	413210	0	0
RomIntgChkDisFalse_A	23247996	22612794	0	0
RomIntgChkDisTrue_A	23247996	106151	0	0
RstreqChkEsctimeout_A	23247996	4883	0	0
RstreqChkFsmterm_A	23247996	120	0	0
RstreqChkGlbesc_A	23247996	4883	0	0
RstreqChkMainpd_A	23247996	981191	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23248606	6204	0	0
T11	15164	13	0	0
T14	16496	0	0	0
T15	10644	0	0	0
T16	1310	0	0	0
T21	16010	0	0	0
T29	7197	0	0	0
T32	2893	0	0	0
T38	26322	0	0	0
T40	2946	0	0	0
T78	1298	0	0	0
T132	0	277	0	0
T157	0	46	0	0
T158	0	56	0	0
T159	0	236	0	0
T160	0	19	0	0
T161	0	106	0	0
T162	0	5	0	0
T163	0	117	0	0
T164	0	8	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	3303603	0	0
T1	2458	25	0	0
T2	3451	552	0	0
T3	1983	427	0	0
T4	3429	761	0	0
T5	7593	1149	0	0
T6	2288	16	0	0
T7	3960	9	0	0
T8	2262	32	0	0
T9	5328	317	0	0
T10	1299	13	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5144859	323	0	0
T6	216	3	0	0
T7	1562	0	0	0
T8	350	0	0	0
T9	480	0	0	0
T10	632	0	0	0
T11	1341	2	0	0
T12	0	3	0	0
T13	531	0	0	0
T14	6623	0	0	0
T20	239	0	0	0
T38	9118	0	0	0
T132	0	3	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	3	0	0
T160	0	2	0	0
T165	0	3	0	0
T166	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	61053	0	0
T1	2458	3	0	0
T2	3451	18	0	0
T3	1983	3	0	0
T4	3429	5	0	0
T5	7593	25	0	0
T6	2288	3	0	0
T7	3960	2	0	0
T8	2262	19	0	0
T9	5328	5	0	0
T10	1299	4	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	61103	0	0
T1	2458	3	0	0
T2	3451	18	0	0
T3	1983	3	0	0
T4	3429	5	0	0
T5	7593	25	0	0
T6	2288	3	0	0
T7	3960	2	0	0
T8	2262	19	0	0
T9	5328	5	0	0
T10	1299	4	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	26218	0	0
T11	15164	0	0	0
T13	1774	222	0	0
T14	16496	0	0	0
T15	10643	0	0	0
T20	2620	0	0	0
T21	16010	0	0	0
T28	0	515	0	0
T29	7197	0	0	0
T38	26321	20	0	0
T40	2945	0	0	0
T64	0	13	0	0
T78	1298	0	0	0
T133	0	126	0	0
T167	0	34	0	0
T168	0	9	0	0
T169	0	408	0	0
T170	0	1115	0	0
T171	0	336	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	413210	0	0
T5	7593	322	0	0
T6	2288	0	0	0
T7	3960	0	0	0
T8	2262	0	0	0
T9	5328	0	0	0
T10	1299	0	0	0
T11	15164	0	0	0
T13	1774	112	0	0
T14	16496	1281	0	0
T20	2620	0	0	0
T28	0	364	0	0
T33	0	184	0	0
T38	0	1293	0	0
T64	0	1277	0	0
T79	0	4118	0	0
T82	0	437	0	0
T172	0	3611	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	22612794	0	0
T1	2458	2379	0	0
T2	3451	3382	0	0
T3	1983	1932	0	0
T4	3429	3365	0	0
T5	7593	7515	0	0
T6	2288	2128	0	0
T7	3960	3880	0	0
T8	2262	2199	0	0
T9	5328	5229	0	0
T10	1299	986	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	106151	0	0
T11	15164	0	0	0
T13	1774	522	0	0
T14	16496	284	0	0
T15	10643	0	0	0
T20	2620	0	0	0
T21	16010	0	0	0
T28	0	111	0	0
T29	7197	0	0	0
T38	26321	0	0	0
T40	2945	0	0	0
T78	1298	0	0	0
T79	0	2196	0	0
T133	0	1117	0	0
T136	0	963	0	0
T167	0	252	0	0
T170	0	2213	0	0
T173	0	792	0	0
T174	0	1490	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	4883	0	0
T2	3451	9	0	0
T3	1983	0	0	0
T4	3429	0	0	0
T5	7593	0	0	0
T6	2288	1	0	0
T7	3960	0	0	0
T8	2262	0	0	0
T9	5328	0	0	0
T10	1299	3	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	1774	2	0	0
T15	0	15	0	0
T21	0	10	0	0
T29	0	4	0	0
T35	0	6	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	120	0	0
T12	2497	0	0	0
T16	1309	0	0	0
T21	16010	20	0	0
T22	0	20	0	0
T23	0	40	0	0
T28	3124	0	0	0
T30	0	20	0	0
T31	0	20	0	0
T32	2892	0	0	0
T33	2687	0	0	0
T34	4326	0	0	0
T35	3839	0	0	0
T36	4162	0	0	0
T37	1532	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	4883	0	0
T2	3451	9	0	0
T3	1983	0	0	0
T4	3429	0	0	0
T5	7593	0	0	0
T6	2288	1	0	0
T7	3960	0	0	0
T8	2262	0	0	0
T9	5328	0	0	0
T10	1299	3	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	1774	2	0	0
T15	0	15	0	0
T21	0	10	0	0
T29	0	4	0	0
T35	0	6	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23247996	981191	0	0
T2	3451	576	0	0
T3	1983	0	0	0
T4	3429	0	0	0
T5	7593	466	0	0
T6	2288	0	0	0
T7	3960	0	0	0
T8	2262	0	0	0
T9	5328	0	0	0
T10	1299	0	0	0
T13	1774	18	0	0
T14	0	1855	0	0
T15	0	272	0	0
T20	0	5	0	0
T29	0	152	0	0
T33	0	214	0	0
T35	0	559	0	0
T38	0	2546	0	0