RSTMGR Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.640s 255.328us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.970s 149.869us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.910s 92.873us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 9.410s 2.026ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.560s 407.992us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.740s 182.447us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.910s 92.873us 20 20 100.00
rstmgr_csr_aliasing 2.560s 407.992us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 0.960s 211.821us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.850s 568.290us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.590s 246.617us 50 50 100.00
V2 reset_info rstmgr_reset 8.600s 1.906ms 50 50 100.00
V2 cpu_info rstmgr_reset 8.600s 1.906ms 50 50 100.00
V2 alert_info rstmgr_reset 8.600s 1.906ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 8.600s 1.906ms 50 50 100.00
V2 stress_all rstmgr_stress_all 1.079m 19.213ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.940s 88.990us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 4.550s 662.085us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 4.550s 662.085us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.970s 149.869us 5 5 100.00
rstmgr_csr_rw 0.910s 92.873us 20 20 100.00
rstmgr_csr_aliasing 2.560s 407.992us 5 5 100.00
rstmgr_same_csr_outstanding 1.710s 244.692us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.970s 149.869us 5 5 100.00
rstmgr_csr_rw 0.910s 92.873us 20 20 100.00
rstmgr_csr_aliasing 2.560s 407.992us 5 5 100.00
rstmgr_same_csr_outstanding 1.710s 244.692us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 27.860s 16.515ms 5 5 100.00
rstmgr_tl_intg_err 6.020s 2.545ms 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 27.860s 16.515ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 27.860s 16.515ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 6.020s 2.545ms 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.390s 181.707us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.220s 2.360ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.210s 244.700us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 27.860s 16.515ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.910s 92.873us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.910s 92.873us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.44 99.40 99.31 99.88 -- 99.83 99.46 98.77

Past Results