RSTMGR Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.630s	245.329us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.960s	148.498us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.910s	90.113us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	6.320s	487.124us	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.630s	413.154us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.950s	194.914us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.910s	90.113us	20	20	100.00
		rstmgr_csr_aliasing	2.630s	413.154us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.000s	262.240us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.790s	525.322us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.610s	276.582us	50	50	100.00
V2	reset_info	rstmgr_reset	7.720s	1.996ms	50	50	100.00
V2	cpu_info	rstmgr_reset	7.720s	1.996ms	50	50	100.00
V2	alert_info	rstmgr_reset	7.720s	1.996ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	7.720s	1.996ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	50.640s	15.438ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	1.060s	202.190us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.640s	468.539us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.640s	468.539us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.960s	148.498us	5	5	100.00
		rstmgr_csr_rw	0.910s	90.113us	20	20	100.00
		rstmgr_csr_aliasing	2.630s	413.154us	5	5	100.00
		rstmgr_same_csr_outstanding	1.610s	246.862us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.960s	148.498us	5	5	100.00
		rstmgr_csr_rw	0.910s	90.113us	20	20	100.00
		rstmgr_csr_aliasing	2.630s	413.154us	5	5	100.00
		rstmgr_same_csr_outstanding	1.610s	246.862us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	29.640s	16.520ms	5	5	100.00
		rstmgr_tl_intg_err	3.610s	1.153ms	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	29.640s	16.520ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	29.640s	16.520ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.610s	1.153ms	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.290s	172.700us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	9.470s	2.358ms	49	50	98.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.200s	244.607us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	29.640s	16.520ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.910s	90.113us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.910s	90.113us	20	20	100.00
V2S		TOTAL			174	175	99.43
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			619	620	99.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	4	80.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.87	--	99.83	99.46	98.77

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:* has 1 failures:
  • Test rstmgr_leaf_rst_cnsty has 1 failures.

    • 36.rstmgr_leaf_rst_cnsty.94912529147021712634170335402969697246498419037149155575887616192569973445157
      Line 305, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest/run.log

        UVM_ERROR @ 435230587 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
        UVM_INFO @ 435230587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• rstmgr_cnsty_chk
• lint
• 2024.06.30_11.40.19
• 2024.06.29_10.01.24
• 2024.06.28_12.18.51
• 2024.06.27_11.35.32
• 2024.06.26_11.33.06