RSTMGR Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 2.550s 247.362us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.520s 136.328us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 44.853s 14 20 70.00
V1 csr_bit_bash rstmgr_csr_bit_bash 10.360s 2.306ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.620s 266.873us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 44.838s 14 20 70.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 44.853s 14 20 70.00
rstmgr_csr_aliasing 2.620s 266.873us 5 5 100.00
V1 TOTAL 93 105 88.57
V2 reset_stretcher rstmgr_por_stretcher 41.458s 49 50 98.00
V2 sw_rst rstmgr_sw_rst 4.560s 557.859us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 2.300s 257.203us 50 50 100.00
V2 reset_info rstmgr_reset 41.424s 49 50 98.00
V2 cpu_info rstmgr_reset 41.424s 49 50 98.00
V2 alert_info rstmgr_reset 41.424s 49 50 98.00
V2 reset_info_capture rstmgr_reset 41.424s 49 50 98.00
V2 stress_all rstmgr_stress_all 1.310m 49 50 98.00
V2 alert_test rstmgr_alert_test 1.240s 74.040us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 44.860s 14 20 70.00
V2 tl_d_illegal_access rstmgr_tl_errors 44.860s 14 20 70.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.520s 136.328us 5 5 100.00
rstmgr_csr_rw 44.853s 14 20 70.00
rstmgr_csr_aliasing 2.620s 266.873us 5 5 100.00
rstmgr_same_csr_outstanding 49.466s 15 20 75.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.520s 136.328us 5 5 100.00
rstmgr_csr_rw 44.853s 14 20 70.00
rstmgr_csr_aliasing 2.620s 266.873us 5 5 100.00
rstmgr_same_csr_outstanding 49.466s 15 20 75.00
V2 TOTAL 326 340 95.88
V2S tl_intg_err rstmgr_sec_cm 43.100s 17.634ms 5 5 100.00
rstmgr_tl_intg_err 44.863s 14 20 70.00
V2S prim_count_check rstmgr_sec_cm 43.100s 17.634ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 43.100s 17.634ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 44.863s 14 20 70.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 41.548s 49 50 98.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 16.180s 2.464ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 41.463s 49 50 98.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 43.100s 17.634ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 44.853s 14 20 70.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 44.853s 14 20 70.00
V2S TOTAL 167 175 95.43
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 586 620 94.52

Testplan Progress

Items Total Written Passing Progress
V1 6 6 4 66.67
V2 8 8 3 37.50
V2S 5 5 2 40.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.45 99.40 99.24 100.00 -- 99.83 99.46 98.77

Failure Buckets

Past Results