KEYMGR Simulation Results

Monday February 19 2024 20:02:26 UTC

GitHub Revision: `fadd169974`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2804340808

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	28.080s	5.140ms	50	50	100.00
V1	random	keymgr_random	1.447m	5.198ms	48	50	96.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.110s	77.932us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.330s	16.894us	14	20	70.00
V1	csr_bit_bash	keymgr_csr_bit_bash	13.450s	2.411ms	4	5	80.00
V1	csr_aliasing	keymgr_csr_aliasing	7.270s	511.655us	3	5	60.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.750s	33.882us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.330s	16.894us	14	20	70.00
		keymgr_csr_aliasing	7.270s	511.655us	3	5	60.00
V1		TOTAL			144	155	92.90
V2	cfgen_during_op	keymgr_cfg_regwen	2.684m	12.030ms	48	50	96.00
V2	sideload	keymgr_sideload	33.570s	1.352ms	50	50	100.00
		keymgr_sideload_kmac	58.770s	2.060ms	50	50	100.00
		keymgr_sideload_aes	1.384m	2.300ms	50	50	100.00
		keymgr_sideload_otbn	48.190s	7.180ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	34.760s	3.633ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	15.870s	496.062us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.099m	14.210ms	46	50	92.00
V2	invalid_sw_input	keymgr_sw_invalid_input	21.450s	1.040ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.210m	2.306ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	43.350s	4.803ms	50	50	100.00
V2	stress_all	keymgr_stress_all	16.229m	32.365ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.030s	19.498us	50	50	100.00
V2	alert_test	keymgr_alert_test	0.990s	21.442us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.630s	714.780us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.630s	714.780us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.110s	77.932us	5	5	100.00
		keymgr_csr_rw	1.330s	16.894us	14	20	70.00
		keymgr_csr_aliasing	7.270s	511.655us	3	5	60.00
		keymgr_same_csr_outstanding	3.690s	349.342us	15	20	75.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.110s	77.932us	5	5	100.00
		keymgr_csr_rw	1.330s	16.894us	14	20	70.00
		keymgr_csr_aliasing	7.270s	511.655us	3	5	60.00
		keymgr_same_csr_outstanding	3.690s	349.342us	15	20	75.00
V2		TOTAL			726	740	98.11
V2S	sec_cm_additional_check	keymgr_sec_cm	3.547m	56.935ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	3.547m	56.935ms	5	5	100.00
		keymgr_tl_intg_err	1.204m	11.220ms	14	20	70.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	41.420s	1.940ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	41.420s	1.940ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	41.420s	1.940ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	41.420s	1.940ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.110s	428.424us	16	20	80.00
V2S	prim_count_check	keymgr_sec_cm	3.547m	56.935ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	3.547m	56.935ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.204m	11.220ms	14	20	70.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	41.420s	1.940ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.684m	12.030ms	48	50	96.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.447m	5.198ms	48	50	96.00
		keymgr_csr_rw	1.330s	16.894us	14	20	70.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.447m	5.198ms	48	50	96.00
		keymgr_csr_rw	1.330s	16.894us	14	20	70.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.447m	5.198ms	48	50	96.00
		keymgr_csr_rw	1.330s	16.894us	14	20	70.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	15.870s	496.062us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.210m	2.306ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.210m	2.306ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.447m	5.198ms	48	50	96.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	24.820s	1.239ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	3.547m	56.935ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	3.547m	56.935ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	3.547m	56.935ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	55.930s	8.923ms	48	50	96.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	15.870s	496.062us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	3.547m	56.935ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	3.547m	56.935ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	3.547m	56.935ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	55.930s	8.923ms	48	50	96.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	55.930s	8.923ms	48	50	96.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	3.547m	56.935ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	55.930s	8.923ms	48	50	96.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	3.547m	56.935ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	55.930s	8.923ms	48	50	96.00
V2S		TOTAL			153	165	92.73
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	20.070s	1.363ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1071	1110	96.49

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	3	42.86
V2	16	16	11	68.75
V2S	6	6	3	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.48	99.10	97.95	98.37	97.67	99.02	98.41	91.83

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 24 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 4 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.835367490
Line 261, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @ 112869467 ps: (keymgr_csr_assert_fpv.sv:431) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @ 112869467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_shadow_reg_errors_with_csr_rw.2184368761
Line 257, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @  73336014 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @  73336014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test keymgr_csr_rw has 6 failures.

0.keymgr_csr_rw.1655434705
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @  28854459 ps: (keymgr_csr_assert_fpv.sv:426) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @  28854459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_csr_rw.4294119161
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @   8643118 ps: (keymgr_csr_assert_fpv.sv:431) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @   8643118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_tl_intg_err has 6 failures.

1.keymgr_tl_intg_err.753112388
Line 276, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
  UVM_ERROR @  83142087 ps: (keymgr_csr_assert_fpv.sv:371) [ASSERT FAILED] sealing_sw_binding_1_rd_A
  UVM_INFO @  83142087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.keymgr_tl_intg_err.3826065966
Line 265, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @  41962303 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @  41962303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_csr_bit_bash has 1 failures.

1.keymgr_csr_bit_bash.860788003
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
  UVM_ERROR @ 145557208 ps: (keymgr_csr_assert_fpv.sv:371) [ASSERT FAILED] sealing_sw_binding_1_rd_A
  UVM_INFO @ 145557208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_aliasing has 2 failures.

2.keymgr_csr_aliasing.3298963078
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @ 298187891 ps: (keymgr_csr_assert_fpv.sv:366) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @ 298187891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_csr_aliasing.200207323
Line 255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
  UVM_ERROR @ 732038480 ps: (keymgr_csr_assert_fpv.sv:371) [ASSERT FAILED] sealing_sw_binding_1_rd_A
  UVM_INFO @ 732038480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more tests.

UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 5 failures:

Test keymgr_custom_cm has 1 failures.

13.keymgr_custom_cm.553576174
Line 343, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/13.keymgr_custom_cm/latest/run.log

  UVM_ERROR @  14473349 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  14473349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_random has 2 failures.

20.keymgr_random.2557661984
Line 263, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/20.keymgr_random/latest/run.log

  UVM_ERROR @   2578754 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   2578754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.keymgr_random.2899254881
Line 268, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/23.keymgr_random/latest/run.log

  UVM_ERROR @   7028200 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   7028200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_kmac_rsp_err has 1 failures.

31.keymgr_kmac_rsp_err.1690387314
Line 538, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  71905998 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  71905998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_lc_disable has 1 failures.

49.keymgr_lc_disable.1821134733
Line 331, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/49.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  70043759 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @  70043759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:1019) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 3 failures:

Test keymgr_kmac_rsp_err has 3 failures.

4.keymgr_kmac_rsp_err.3117818747
Line 431, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 196779796 ps: (keymgr_scoreboard.sv:1019) [uvm_test_top.env.scoreboard] Check failed act != exp (175939498812201022907626206367943064602501634567437082466085190989828971053257239602693986269894465995087422763187589420795803272529145411351995466452162449092629826048425726475213241712756452752205382785097785271941095949148321126805372135102603559996415173016609079460722357827149943043592187567420776732632906934421085967995056501274719184182895556833273055850026329141647364075011915188628564291201670623995701322522689332850618500033396195972794012152426415059139303073031666069025161036 [0xebdb9e14a9efdcb17a6898a5c65e8bb9db3efb13ee2466f81e5012073a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9f36c4359171bc638574900598da49dcca1f35964b7c5e72090c629dd7cbeb84991930ba554728d9b6fff53d6ffa992499419d47c945db71a9aab0b784f48611793ce020b0478d713d2aeb31336ea639d44125f0e9b547f8b86cbaa50a6b69616c0f5ee253972f315e3034f9bb53156f2932275d109899f3016f68d7bb4d1611f65493cbc61f5b1e1716d6e7e19917f4c] vs 175939498812201022907626206367943064602501634567437082466085190989828971053257239602693986269894465995087422763187589420795803272529145411351995466452162449092629826048425726475213241712756452752205382785097785271941095949148321126805372135102603559996415173016609079460722357827149943043592187567420776732632906934421085967995056501274719184182895556833273055850026329141647364075011915188628564291201670623995701322522689332850618500033396195972794012152426415059139303073031666069025161036 [0xebdb9e14a9efdcb17a6898a5c65e8bb9db3efb13ee2466f81e5012073a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9f36c4359171bc638574900598da49dcca1f35964b7c5e72090c629dd7cbeb84991930ba554728d9b6fff53d6ffa992499419d47c945db71a9aab0b784f48611793ce020b0478d713d2aeb31336ea639d44125f0e9b547f8b86cbaa50a6b69616c0f5ee253972f315e3034f9bb53156f2932275d109899f3016f68d7bb4d1611f65493cbc61f5b1e1716d6e7e19917f4c]) cdi_type: Attestation
  
   DiversificationKey act: 0x932275d109899f3016f68d7bb4d1611f65493cbc61f5b1e1716d6e7e19917f4c, exp: 0x932275d109899f3016f68d7bb4d1611f65493cbc61f5b1e1716d6e7e19917f4c
   RomDigests act: 0x9419d47c945db71a9aab0b784f48611793ce020b0478d713d2aeb31336ea639d44125f0e9b547f8b86cbaa50a6b69616c0f5ee253972f315e3034f9bb53156f2, exp: 0x9419d47c945db71a9aab0b784f48611793ce020b0478d713d2aeb31336ea639d44125f0e9b547f8b86cbaa50a6b69616c0f5ee253972f315e3034f9bb53156f2
   HealthMeasurement act: 0x91930ba554728d9b6fff53d6ffa99249, exp: 0x91930ba554728d9b6fff53d6ffa99249

30.keymgr_kmac_rsp_err.3790542943
Line 299, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  54586957 ps: (keymgr_scoreboard.sv:1019) [uvm_test_top.env.scoreboard] Check failed act != exp (1605930754565491250042339328357387143542526556207941497641627338815315533913343515646265808005671685584271954598417583170859399892381523661621958049756735861810402198756932994732246733374662691869384690517716124107010419659528850180762346545724968078610592122102067074818706749717552002587094718233992628884362987470171799828805954676579509541792247087374262776688172790660235434784258077967949577008308386870891866729508642 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f97f548943535c2d92f58c86b6678f8c6905cebb664837484e790be5f50bece816ec017f5d08bd08899a47323b5eaf83c234b524d202fff68f44b9a82b6638436e1e7395943927a5c31f3136b1cf01a1307610147d5556365b31f5fae6e2191779dbd38eb784268436792f8aaf0e456f7192db5eec2e0f0387f0011121a81cdecccd2b00dc80b607e366f362254f786f22] vs 1605930754565491250042339328357387143542526556207941497641627338815315533913343515646265808005671685584271954598417583170859399892381523661621958049756735861810402198756932994732246733374662691869384690517716124107010419659528850180762346545724968078610592122102067074818706749717552002587094718233992628884362987470171799828805954676579509541792247087374262776688172790660235434784258077967949577008308386870891866729508642 [0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f97f548943535c2d92f58c86b6678f8c6905cebb664837484e790be5f50bece816ec017f5d08bd08899a47323b5eaf83c234b524d202fff68f44b9a82b6638436e1e7395943927a5c31f3136b1cf01a1307610147d5556365b31f5fae6e2191779dbd38eb784268436792f8aaf0e456f7192db5eec2e0f0387f0011121a81cdecccd2b00dc80b607e366f362254f786f22]) cdi_type: Attestation
  
   DiversificationKey act: 0x92db5eec2e0f0387f0011121a81cdecccd2b00dc80b607e366f362254f786f22, exp: 0x92db5eec2e0f0387f0011121a81cdecccd2b00dc80b607e366f362254f786f22
   RomDigests act: 0x34b524d202fff68f44b9a82b6638436e1e7395943927a5c31f3136b1cf01a1307610147d5556365b31f5fae6e2191779dbd38eb784268436792f8aaf0e456f71, exp: 0x34b524d202fff68f44b9a82b6638436e1e7395943927a5c31f3136b1cf01a1307610147d5556365b31f5fae6e2191779dbd38eb784268436792f8aaf0e456f71
   HealthMeasurement act: 0xec017f5d08bd08899a47323b5eaf83c2, exp: 0xec017f5d08bd08899a47323b5eaf83c2

... and 1 more failures.

UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 2 failures:

Test keymgr_cfg_regwen has 2 failures.

0.keymgr_cfg_regwen.4050874180
Line 308, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @   7305649 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @   7305649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.keymgr_cfg_regwen.284320346
Line 477, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @  14708881 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @  14708881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 4.keymgr_stress_all.753091310
    Line 397, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @  23734179 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (3469598362 [0xcecdde9a] vs 3538167966 [0xd2e4289e]) reg name: keymgr_reg_block.sw_share1_output_0
  UVM_INFO @  23734179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 20.keymgr_stress_all.3469080139
    Line 949, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/20.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 985043910 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1940082084 [0x73a34da4] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_0
  UVM_INFO @ 985043910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_scoreboard.sv:1017) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation has 1 failures:

Test keymgr_stress_all_with_rand_reset has 1 failures.

22.keymgr_stress_all_with_rand_reset.4122712391
Line 799, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/22.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  70693337 ps: (keymgr_scoreboard.sv:1017) [uvm_test_top.env.scoreboard] Check failed act == exp (326133465016236683187709325500480403919454291211073073082024343213253399400683328367543526311894110979905280036001419091939297106375527466844116441905125650029214616306552188944400760017907900824613001636664124116857398698564021944751837988688008644399317496836415615393187779973502023328975747401773574381765266869784798388221290299661701636543333439432259479684349605209892240733990918888463202199162655279600735241556985140506820296952944245134315442476819177796758046977968736910582369250169752559 [0x65cb4930000000000000000000000000000000002505cb2900000000000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9e602c9c4b057f678500b99d498e3102b70939c7c5dd265a272b862a5f022b96d83d3b33eac116e41500354bafc7a6c5948a19f4d7d583e28e40ec57264c0949def224f72fc706ca0746d8a181ca69806d05e023991f1f592f23414392bce83b96ab63d922872072489a97df1a36ece9712a1e50bce11477f239fa3b2316decad3daf8a2410af96952bc3f42a1df28bef] vs 111747944902835106936324195662851743709431191398200446276310817520089545187255015625147890483932046787588623705551454229148552836942349319027081508834204191932309373161857444213103400705049293713344126885579361732064834032535268513907105206433459565211205050576046622512151782172007234248889999000760283610601367645051332846449829418455684491124112817284241691916496676352947582931942087778583439059805447115078869801213850405807698711658508359220544134107586781570107637459329273538605648879 [0x95ce1ac24fdb267d00000000000000000000000000000000000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9e602c9c4b057f678500b99d498e3102b70939c7c5dd265a272b862a5f022b96d83d3b33eac116e41500354bafc7a6c5948a19f4d7d583e28e40ec57264c0949def224f72fc706ca0746d8a181ca69806d05e023991f1f592f23414392bce83b96ab63d922872072489a97df1a36ece9712a1e50bce11477f239fa3b2316decad3daf8a2410af96952bc3f42a1df28bef]) cdi_type: Attestation
  
   DiversificationKey act: 0x12a1e50bce11477f239fa3b2316decad3daf8a2410af96952bc3f42a1df28bef, exp: 0x12a1e50bce11477f239fa3b2316decad3daf8a2410af96952bc3f42a1df28bef
   RomDigests act: 0x48a19f4d7d583e28e40ec57264c0949def224f72fc706ca0746d8a181ca69806d05e023991f1f592f23414392bce83b96ab63d922872072489a97df1a36ece97, exp: 0x48a19f4d7d583e28e40ec57264c0949def224f72fc706ca0746d8a181ca69806d05e023991f1f592f23414392bce83b96ab63d922872072489a97df1a36ece97
   HealthMeasurement act: 0x83d3b33eac116e41500354bafc7a6c59, exp: 0x83d3b33eac116e41500354bafc7a6c59

UVM_ERROR (keymgr_scoreboard.sv:674) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 33.keymgr_stress_all_with_rand_reset.2507318002
    Line 843, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1071180743 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 1071180743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (keymgr_custom_cm_vseq.sv:37) [keymgr_custom_cm_vseq] wait timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 37.keymgr_custom_cm.2920053025
    Line 301, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 10670507344 ps: (keymgr_custom_cm_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
  UVM_INFO @ 10670507344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```