KEYMGR Simulation Results

Saturday May 11 2024 19:02:11 UTC

GitHub Revision: d3914e529e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2197522926

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 39.660s 1.429ms 50 50 100.00
V1 random keymgr_random 49.210s 8.708ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.830s 101.570us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.310s 94.782us 17 20 85.00
V1 csr_bit_bash keymgr_csr_bit_bash 25.260s 6.114ms 4 5 80.00
V1 csr_aliasing keymgr_csr_aliasing 9.370s 531.219us 3 5 60.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 2.020s 52.145us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.310s 94.782us 17 20 85.00
keymgr_csr_aliasing 9.370s 531.219us 3 5 60.00
V1 TOTAL 149 155 96.13
V2 cfgen_during_op keymgr_cfg_regwen 2.244m 5.058ms 50 50 100.00
V2 sideload keymgr_sideload 53.280s 3.851ms 50 50 100.00
keymgr_sideload_kmac 1.374m 45.710ms 50 50 100.00
keymgr_sideload_aes 1.169m 3.545ms 50 50 100.00
keymgr_sideload_otbn 1.348m 8.187ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 23.370s 2.347ms 50 50 100.00
V2 lc_disable keymgr_lc_disable 6.500s 794.908us 49 50 98.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.310m 2.401ms 46 50 92.00
V2 invalid_sw_input keymgr_sw_invalid_input 2.048m 35.219ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.818m 11.394ms 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 33.040s 2.086ms 49 50 98.00
V2 stress_all keymgr_stress_all 5.702m 20.712ms 49 50 98.00
V2 intr_test keymgr_intr_test 0.920s 142.552us 50 50 100.00
V2 alert_test keymgr_alert_test 1.050s 22.061us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 6.500s 691.876us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 6.500s 691.876us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.830s 101.570us 5 5 100.00
keymgr_csr_rw 1.310s 94.782us 17 20 85.00
keymgr_csr_aliasing 9.370s 531.219us 3 5 60.00
keymgr_same_csr_outstanding 2.610s 35.234us 16 20 80.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.830s 101.570us 5 5 100.00
keymgr_csr_rw 1.310s 94.782us 17 20 85.00
keymgr_csr_aliasing 9.370s 531.219us 3 5 60.00
keymgr_same_csr_outstanding 2.610s 35.234us 16 20 80.00
V2 TOTAL 729 740 98.51
V2S sec_cm_additional_check keymgr_sec_cm 1.200m 3.959ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 1.200m 3.959ms 5 5 100.00
keymgr_tl_intg_err 57.300s 6.180ms 16 20 80.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 6.460s 207.650us 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 6.460s 207.650us 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 6.460s 207.650us 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 6.460s 207.650us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 18.100s 641.369us 17 20 85.00
V2S prim_count_check keymgr_sec_cm 1.200m 3.959ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 1.200m 3.959ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 57.300s 6.180ms 16 20 80.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 6.460s 207.650us 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.244m 5.058ms 50 50 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 49.210s 8.708ms 50 50 100.00
keymgr_csr_rw 1.310s 94.782us 17 20 85.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 49.210s 8.708ms 50 50 100.00
keymgr_csr_rw 1.310s 94.782us 17 20 85.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 49.210s 8.708ms 50 50 100.00
keymgr_csr_rw 1.310s 94.782us 17 20 85.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 6.500s 794.908us 49 50 98.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.818m 11.394ms 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.818m 11.394ms 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 49.210s 8.708ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 21.990s 7.023ms 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 1.200m 3.959ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 1.200m 3.959ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 1.200m 3.959ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 35.090s 1.033ms 50 50 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 6.500s 794.908us 49 50 98.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 1.200m 3.959ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 1.200m 3.959ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 1.200m 3.959ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 35.090s 1.033ms 50 50 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 35.090s 1.033ms 50 50 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 1.200m 3.959ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 35.090s 1.033ms 50 50 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 1.200m 3.959ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 35.090s 1.033ms 50 50 100.00
V2S TOTAL 158 165 95.76
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 13.540s 1.327ms 40 50 80.00
V3 TOTAL 40 50 80.00
TOTAL 1076 1110 96.94

Testplan Progress

Items Total Written Passing Progress
V1 7 7 4 57.14
V2 16 16 11 68.75
V2S 6 6 4 66.67
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.81 99.10 98.07 98.42 100.00 99.11 98.41 91.54

Failure Buckets

Past Results