KEYMGR Simulation Results

Saturday March 16 2024 19:02:18 UTC

GitHub Revision: 67a5ccc959

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3339976940

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 43.180s 9.452ms 50 50 100.00
V1 random keymgr_random 1.595m 10.036ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.450s 31.566us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.420s 35.686us 15 20 75.00
V1 csr_bit_bash keymgr_csr_bit_bash 23.290s 12.151ms 2 5 40.00
V1 csr_aliasing keymgr_csr_aliasing 12.190s 716.375us 4 5 80.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 2.230s 112.603us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.420s 35.686us 15 20 75.00
keymgr_csr_aliasing 12.190s 716.375us 4 5 80.00
V1 TOTAL 146 155 94.19
V2 cfgen_during_op keymgr_cfg_regwen 2.711m 21.018ms 50 50 100.00
V2 sideload keymgr_sideload 1.057m 34.500ms 50 50 100.00
keymgr_sideload_kmac 52.850s 1.646ms 50 50 100.00
keymgr_sideload_aes 54.590s 2.157ms 50 50 100.00
keymgr_sideload_otbn 1.309m 35.224ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 19.530s 3.893ms 50 50 100.00
V2 lc_disable keymgr_lc_disable 48.780s 10.806ms 50 50 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.111m 2.057ms 45 50 90.00
V2 invalid_sw_input keymgr_sw_invalid_input 1.103m 13.366ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.109m 2.640ms 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 22.740s 1.156ms 50 50 100.00
V2 stress_all keymgr_stress_all 7.020m 178.755ms 50 50 100.00
V2 intr_test keymgr_intr_test 0.960s 20.276us 50 50 100.00
V2 alert_test keymgr_alert_test 1.040s 32.231us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 4.400s 484.940us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 4.400s 484.940us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.450s 31.566us 5 5 100.00
keymgr_csr_rw 1.420s 35.686us 15 20 75.00
keymgr_csr_aliasing 12.190s 716.375us 4 5 80.00
keymgr_same_csr_outstanding 4.230s 432.585us 17 20 85.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.450s 31.566us 5 5 100.00
keymgr_csr_rw 1.420s 35.686us 15 20 75.00
keymgr_csr_aliasing 12.190s 716.375us 4 5 80.00
keymgr_same_csr_outstanding 4.230s 432.585us 17 20 85.00
V2 TOTAL 732 740 98.92
V2S sec_cm_additional_check keymgr_sec_cm 2.093m 10.857ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 2.093m 10.857ms 5 5 100.00
keymgr_tl_intg_err 1.851m 10.982ms 14 20 70.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 11.660s 2.596ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 11.660s 2.596ms 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 11.660s 2.596ms 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 11.660s 2.596ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 16.400s 518.199us 16 20 80.00
V2S prim_count_check keymgr_sec_cm 2.093m 10.857ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 2.093m 10.857ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 1.851m 10.982ms 14 20 70.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 11.660s 2.596ms 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.711m 21.018ms 50 50 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 1.595m 10.036ms 50 50 100.00
keymgr_csr_rw 1.420s 35.686us 15 20 75.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 1.595m 10.036ms 50 50 100.00
keymgr_csr_rw 1.420s 35.686us 15 20 75.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 1.595m 10.036ms 50 50 100.00
keymgr_csr_rw 1.420s 35.686us 15 20 75.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 48.780s 10.806ms 50 50 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.109m 2.640ms 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.109m 2.640ms 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 1.595m 10.036ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 27.160s 4.596ms 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 2.093m 10.857ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 2.093m 10.857ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 2.093m 10.857ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 1.491m 4.051ms 50 50 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 48.780s 10.806ms 50 50 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 2.093m 10.857ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 2.093m 10.857ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 2.093m 10.857ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 1.491m 4.051ms 50 50 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 1.491m 4.051ms 50 50 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 2.093m 10.857ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 1.491m 4.051ms 50 50 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 2.093m 10.857ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 1.491m 4.051ms 50 50 100.00
V2S TOTAL 155 165 93.94
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 18.580s 320.381us 45 50 90.00
V3 TOTAL 45 50 90.00
TOTAL 1078 1110 97.12

Testplan Progress

Items Total Written Passing Progress
V1 7 7 4 57.14
V2 16 16 14 87.50
V2S 6 6 4 66.67
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.84 99.10 98.03 98.70 100.00 99.11 98.41 91.56

Failure Buckets

Past Results