KEYMGR_DPE Simulation Results

Saturday April 27 2024 19:02:11 UTC

GitHub Revision: d4aa482ae5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2436371151

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_dpe_smoke 4.329m 11.082ms 50 50 100.00
V1 csr_hw_reset keymgr_dpe_csr_hw_reset 1.400s 58.332us 5 5 100.00
V1 csr_rw keymgr_dpe_csr_rw 1.470s 48.515us 20 20 100.00
V1 csr_bit_bash keymgr_dpe_csr_bit_bash 17.660s 5.208ms 5 5 100.00
V1 csr_aliasing keymgr_dpe_csr_aliasing 5.960s 527.714us 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_dpe_csr_mem_rw_with_rand_reset 1.840s 105.729us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_dpe_csr_rw 1.470s 48.515us 20 20 100.00
keymgr_dpe_csr_aliasing 5.960s 527.714us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 intr_test keymgr_dpe_intr_test 0.980s 19.522us 50 50 100.00
V2 alert_test keymgr_dpe_alert_test 1.020s 20.134us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_dpe_tl_errors 6.210s 779.301us 20 20 100.00
V2 tl_d_illegal_access keymgr_dpe_tl_errors 6.210s 779.301us 20 20 100.00
V2 tl_d_outstanding_access keymgr_dpe_csr_hw_reset 1.400s 58.332us 5 5 100.00
keymgr_dpe_csr_rw 1.470s 48.515us 20 20 100.00
keymgr_dpe_csr_aliasing 5.960s 527.714us 5 5 100.00
keymgr_dpe_same_csr_outstanding 3.340s 92.530us 20 20 100.00
V2 tl_d_partial_access keymgr_dpe_csr_hw_reset 1.400s 58.332us 5 5 100.00
keymgr_dpe_csr_rw 1.470s 48.515us 20 20 100.00
keymgr_dpe_csr_aliasing 5.960s 527.714us 5 5 100.00
keymgr_dpe_same_csr_outstanding 3.340s 92.530us 20 20 100.00
V2 TOTAL 140 140 100.00
V2S tl_intg_err keymgr_dpe_sec_cm 23.560s 1.029ms 5 5 100.00
keymgr_dpe_tl_intg_err 8.940s 1.028ms 20 20 100.00
V2S shadow_reg_update_error keymgr_dpe_shadow_reg_errors 4.720s 200.441us 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_dpe_shadow_reg_errors 4.720s 200.441us 20 20 100.00
V2S shadow_reg_storage_error keymgr_dpe_shadow_reg_errors 4.720s 200.441us 20 20 100.00
V2S shadowed_reset_glitch keymgr_dpe_shadow_reg_errors 4.720s 200.441us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_dpe_shadow_reg_errors_with_csr_rw 9.620s 737.179us 20 20 100.00
V2S prim_count_check keymgr_dpe_sec_cm 23.560s 1.029ms 5 5 100.00
V2S prim_fsm_check keymgr_dpe_sec_cm 23.560s 1.029ms 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset keymgr_dpe_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 310 310 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 4 4 4 100.00
V2S 4 4 4 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
76.27 97.70 90.67 57.52 76.92 94.94 98.34 17.82

Past Results