ADC_CTRL Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.340s	6.182ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.210s	1.315ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.570s	418.831us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.871m	52.743ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.700s	1.111ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.090s	525.454us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.570s	418.831us	20	20	100.00
		adc_ctrl_csr_aliasing	5.700s	1.111ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.003m	492.605ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.988m	490.890ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.422m	487.777ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.308m	487.958ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	19.589m	537.067ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	20.489m	493.021ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.726m	509.311ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	19.028m	478.549ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.400s	5.850ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.690m	43.277ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.200m	151.230ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	34.588m	793.219ms	43	50	86.00
V2	alert_test	adc_ctrl_alert_test	1.880s	507.685us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.840s	497.672us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.860s	531.329us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.860s	531.329us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.210s	1.315ms	5	5	100.00
		adc_ctrl_csr_rw	1.570s	418.831us	20	20	100.00
		adc_ctrl_csr_aliasing	5.700s	1.111ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	14.380s	4.716ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.210s	1.315ms	5	5	100.00
		adc_ctrl_csr_rw	1.570s	418.831us	20	20	100.00
		adc_ctrl_csr_aliasing	5.700s	1.111ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	14.380s	4.716ms	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	tl_intg_err	adc_ctrl_sec_cm	19.510s	7.954ms	5	5	100.00
		adc_ctrl_tl_intg_err	24.310s	8.719ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	24.310s	8.719ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.190m	502.770ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			892	920	96.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.51	99.01	95.70	100.00	100.00	98.18	98.64	91.05

Failure Buckets

Offending '(wakeup_time == cfg_wakeup_time)' has 20 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 20 failures.
  - 2.adc_ctrl_stress_all_with_rand_reset.382814579
    Line 516, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 654484594594 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 654484594594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 3.adc_ctrl_stress_all_with_rand_reset.2159449477
    Line 338, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 11863810089 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 11863810089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 18 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 8 failures:

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

0.adc_ctrl_stress_all_with_rand_reset.3729227515
Line 389, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 80149190211 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 80149190211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all has 7 failures.

24.adc_ctrl_stress_all.2381158596
Line 367, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 429919154631 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 429919154631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.adc_ctrl_stress_all.2261692756
Line 327, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 323806021153 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 323806021153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.