ADC_CTRL Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: `748235cbb6`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.770s	6.184ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.300s	1.039ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.030s	573.967us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	3.150m	37.012ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.840s	1.211ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.100s	555.145us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.030s	573.967us	20	20	100.00
		adc_ctrl_csr_aliasing	2.840s	1.211ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.604m	488.188ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.587m	500.532ms	49	50	98.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.334m	501.726ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.155m	504.962ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	20.303m	509.829ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	18.547m	497.019ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.957m	510.777ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	19.647m	494.191ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.530s	5.807ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.562m	39.594ms	49	50	98.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.424m	134.668ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	23.242m	470.679ms	42	50	84.00
V2	alert_test	adc_ctrl_alert_test	1.830s	528.604us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.880s	512.832us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.610s	490.816us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.610s	490.816us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.300s	1.039ms	5	5	100.00
		adc_ctrl_csr_rw	2.030s	573.967us	20	20	100.00
		adc_ctrl_csr_aliasing	2.840s	1.211ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.050s	4.834ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.300s	1.039ms	5	5	100.00
		adc_ctrl_csr_rw	2.030s	573.967us	20	20	100.00
		adc_ctrl_csr_aliasing	2.840s	1.211ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.050s	4.834ms	20	20	100.00
V2		TOTAL			730	740	98.65
V2S	tl_intg_err	adc_ctrl_sec_cm	20.010s	8.089ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.590s	8.635ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.590s	8.635ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	7.898m	178.049ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			905	920	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	13	81.25
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.49	98.98	95.70	100.00	100.00	98.18	98.64	90.95

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 9 failures:

Test adc_ctrl_stress_all has 8 failures.

0.adc_ctrl_stress_all.99055898587838289092996552339952957936740372365205972244709798993667963208541
Line 371, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 327455945530 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 327455945530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.adc_ctrl_stress_all.99304834185656731117267430970545999375444188690080759951383923071679752682336
Line 374, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 335873761546 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 335873761546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

15.adc_ctrl_stress_all_with_rand_reset.4666187041212415745421352166425545564752622285023937946085830678656337132764
Line 401, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 41244259358 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 41244259358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:99) [adc_ctrl_common_vseq] wait timeout occurred! has 3 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 1.adc_ctrl_stress_all_with_rand_reset.100805985445626769179094432084482693606733503081103133269778550676624710131291
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 87697581063 ps: (cip_base_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.adc_ctrl_common_vseq] wait timeout occurred!
  UVM_INFO @ 87697581063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.adc_ctrl_stress_all_with_rand_reset.31720996336903280050008848685972046940378624280865708172748912592617608060383
    Line 335, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10747880774 ps: (cip_base_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.adc_ctrl_common_vseq] wait timeout occurred!
  UVM_INFO @ 10747880774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test adc_ctrl_lowpower_counter has 1 failures.

42.adc_ctrl_lowpower_counter.110170834570504649948943459084209552022193058107675330018035790700934275341717
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_lowpower_counter/latest/run.log

  [make]: simulate
  cd /workspace/42.adc_ctrl_lowpower_counter/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49880469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.49880469
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan  3 13:18 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

42.adc_ctrl_stress_all_with_rand_reset.90536252481944455921281080277775534117183981260564448805904196913196715181827
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  [make]: simulate
  cd /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest && /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544259331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1544259331
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan  3 13:18 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

Test adc_ctrl_filters_polled_fixed has 1 failures.

43.adc_ctrl_filters_polled_fixed.106189254026312778608054165628726215396277325229258593926138770910355900035685
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled_fixed/latest/run.log

  [make]: simulate
  cd /workspace/43.adc_ctrl_filters_polled_fixed/latest && /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770643045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed.3770643045
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan  3 13:18 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255