AES/MASKED Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 3002339765

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 3.000s 60.414us 1 1 100.00
V1 smoke aes_smoke 8.000s 406.579us 50 50 100.00
V1 csr_hw_reset aes_csr_hw_reset 4.000s 54.646us 5 5 100.00
V1 csr_rw aes_csr_rw 4.000s 156.018us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 10.000s 1.547ms 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 5.000s 218.245us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 4.000s 64.892us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 4.000s 156.018us 20 20 100.00
aes_csr_aliasing 5.000s 218.245us 5 5 100.00
V1 TOTAL 106 106 100.00
V2 algorithm aes_smoke 8.000s 406.579us 50 50 100.00
aes_config_error 17.000s 1.050ms 50 50 100.00
aes_stress 3.600m 3.285ms 50 50 100.00
V2 key_length aes_smoke 8.000s 406.579us 50 50 100.00
aes_config_error 17.000s 1.050ms 50 50 100.00
aes_stress 3.600m 3.285ms 50 50 100.00
V2 back2back aes_stress 3.600m 3.285ms 50 50 100.00
aes_b2b 1.033m 945.911us 50 50 100.00
V2 backpressure aes_stress 3.600m 3.285ms 50 50 100.00
V2 multi_message aes_smoke 8.000s 406.579us 50 50 100.00
aes_config_error 17.000s 1.050ms 50 50 100.00
aes_stress 3.600m 3.285ms 50 50 100.00
aes_alert_reset 20.000s 532.703us 50 50 100.00
V2 failure_test aes_config_error 17.000s 1.050ms 50 50 100.00
aes_alert_reset 20.000s 532.703us 50 50 100.00
aes_man_cfg_err 26.000s 1.013ms 50 50 100.00
V2 trigger_clear_test aes_clear 1.600m 3.645ms 50 50 100.00
V2 nist_test_vectors aes_nist_vectors 13.000s 365.292us 1 1 100.00
V2 reset_recovery aes_alert_reset 20.000s 532.703us 50 50 100.00
V2 stress aes_stress 3.600m 3.285ms 50 50 100.00
V2 sideload aes_stress 3.600m 3.285ms 50 50 100.00
aes_sideload 25.000s 1.738ms 50 50 100.00
V2 deinitialization aes_deinit 14.000s 1.130ms 50 50 100.00
V2 alert_test aes_alert_test 5.000s 77.590us 50 50 100.00
V2 tl_d_oob_addr_access aes_tl_errors 7.000s 443.882us 20 20 100.00
V2 tl_d_illegal_access aes_tl_errors 7.000s 443.882us 20 20 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 4.000s 54.646us 5 5 100.00
aes_csr_rw 4.000s 156.018us 20 20 100.00
aes_csr_aliasing 5.000s 218.245us 5 5 100.00
aes_same_csr_outstanding 4.000s 260.551us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 4.000s 54.646us 5 5 100.00
aes_csr_rw 4.000s 156.018us 20 20 100.00
aes_csr_aliasing 5.000s 218.245us 5 5 100.00
aes_same_csr_outstanding 4.000s 260.551us 20 20 100.00
V2 TOTAL 491 491 100.00
V2S reseeding aes_reseed 2.517m 1.968ms 50 50 100.00
V2S fault_inject aes_fi 11.000s 1.037ms 50 50 100.00
aes_control_fi 29.000s 10.009ms 281 300 93.67
aes_cipher_fi 48.000s 10.005ms 335 350 95.71
V2S shadow_reg_update_error aes_shadow_reg_errors 4.000s 96.518us 20 20 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 4.000s 96.518us 20 20 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 4.000s 96.518us 20 20 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 4.000s 96.518us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 5.000s 116.773us 20 20 100.00
V2S tl_intg_err aes_sec_cm 11.000s 761.989us 5 5 100.00
aes_tl_intg_err 7.000s 1.666ms 20 20 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 7.000s 1.666ms 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 20.000s 532.703us 50 50 100.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 4.000s 96.518us 20 20 100.00
V2S sec_cm_main_config_sparse aes_smoke 8.000s 406.579us 50 50 100.00
aes_stress 3.600m 3.285ms 50 50 100.00
aes_alert_reset 20.000s 532.703us 50 50 100.00
aes_core_fi 3.467m 10.025ms 67 70 95.71
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 4.000s 96.518us 20 20 100.00
V2S sec_cm_aux_config_regwen aes_stress 3.600m 3.285ms 50 50 100.00
aes_readability 6.000s 67.048us 50 50 100.00
V2S sec_cm_key_sideload aes_stress 3.600m 3.285ms 50 50 100.00
aes_sideload 25.000s 1.738ms 50 50 100.00
V2S sec_cm_key_sw_unreadable aes_readability 6.000s 67.048us 50 50 100.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 6.000s 67.048us 50 50 100.00
V2S sec_cm_key_sec_wipe aes_readability 6.000s 67.048us 50 50 100.00
V2S sec_cm_iv_config_sec_wipe aes_readability 6.000s 67.048us 50 50 100.00
V2S sec_cm_data_reg_sec_wipe aes_readability 6.000s 67.048us 50 50 100.00
V2S sec_cm_data_reg_key_sca aes_stress 3.600m 3.285ms 50 50 100.00
V2S sec_cm_key_masking aes_stress 3.600m 3.285ms 50 50 100.00
V2S sec_cm_main_fsm_sparse aes_fi 11.000s 1.037ms 50 50 100.00
V2S sec_cm_main_fsm_redun aes_fi 11.000s 1.037ms 50 50 100.00
aes_control_fi 29.000s 10.009ms 281 300 93.67
aes_cipher_fi 48.000s 10.005ms 335 350 95.71
aes_ctr_fi 6.000s 210.110us 50 50 100.00
V2S sec_cm_cipher_fsm_sparse aes_fi 11.000s 1.037ms 50 50 100.00
V2S sec_cm_cipher_fsm_redun aes_fi 11.000s 1.037ms 50 50 100.00
aes_control_fi 29.000s 10.009ms 281 300 93.67
aes_cipher_fi 48.000s 10.005ms 335 350 95.71
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 48.000s 10.005ms 335 350 95.71
V2S sec_cm_ctr_fsm_sparse aes_fi 11.000s 1.037ms 50 50 100.00
V2S sec_cm_ctr_fsm_redun aes_fi 11.000s 1.037ms 50 50 100.00
aes_control_fi 29.000s 10.009ms 281 300 93.67
aes_ctr_fi 6.000s 210.110us 50 50 100.00
V2S sec_cm_ctrl_sparse aes_fi 11.000s 1.037ms 50 50 100.00
aes_control_fi 29.000s 10.009ms 281 300 93.67
aes_cipher_fi 48.000s 10.005ms 335 350 95.71
aes_ctr_fi 6.000s 210.110us 50 50 100.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 20.000s 532.703us 50 50 100.00
V2S sec_cm_main_fsm_local_esc aes_fi 11.000s 1.037ms 50 50 100.00
aes_control_fi 29.000s 10.009ms 281 300 93.67
aes_cipher_fi 48.000s 10.005ms 335 350 95.71
aes_ctr_fi 6.000s 210.110us 50 50 100.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 11.000s 1.037ms 50 50 100.00
aes_control_fi 29.000s 10.009ms 281 300 93.67
aes_cipher_fi 48.000s 10.005ms 335 350 95.71
aes_ctr_fi 6.000s 210.110us 50 50 100.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 11.000s 1.037ms 50 50 100.00
aes_control_fi 29.000s 10.009ms 281 300 93.67
aes_ctr_fi 6.000s 210.110us 50 50 100.00
V2S sec_cm_data_reg_local_esc aes_fi 11.000s 1.037ms 50 50 100.00
aes_control_fi 29.000s 10.009ms 281 300 93.67
aes_cipher_fi 48.000s 10.005ms 335 350 95.71
V2S TOTAL 948 985 96.24
V3 TOTAL 0 0 --
TOTAL 1545 1582 97.66

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 12 12 12 100.00
V2S 11 11 8 72.73

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.48 99.02 97.58 99.41 95.89 95.66 97.78 98.67 92.90

Failure Buckets

Past Results