AES/MASKED Simulation Results

Wednesday October 11 2023 19:03:00 UTC

GitHub Revision: `f600eccc2`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 1737291072

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	6.000s	57.037us	1	1	100.00
V1	smoke	aes_smoke	18.000s	429.586us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	7.000s	133.375us	5	5	100.00
V1	csr_rw	aes_csr_rw	11.000s	108.702us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	1.305ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	70.527us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	77.218us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	11.000s	108.702us	20	20	100.00
		aes_csr_aliasing	7.000s	70.527us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	18.000s	429.586us	50	50	100.00
		aes_config_error	28.000s	734.856us	50	50	100.00
		aes_stress	18.000s	675.990us	50	50	100.00
V2	key_length	aes_smoke	18.000s	429.586us	50	50	100.00
		aes_config_error	28.000s	734.856us	50	50	100.00
		aes_stress	18.000s	675.990us	50	50	100.00
V2	back2back	aes_stress	18.000s	675.990us	50	50	100.00
		aes_b2b	34.000s	328.079us	50	50	100.00
V2	backpressure	aes_stress	18.000s	675.990us	50	50	100.00
V2	multi_message	aes_smoke	18.000s	429.586us	50	50	100.00
		aes_config_error	28.000s	734.856us	50	50	100.00
		aes_stress	18.000s	675.990us	50	50	100.00
		aes_alert_reset	1.367m	4.981ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	88.667us	50	50	100.00
		aes_config_error	28.000s	734.856us	50	50	100.00
		aes_alert_reset	1.367m	4.981ms	50	50	100.00
V2	trigger_clear_test	aes_clear	25.000s	1.481ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	15.000s	3.701ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.367m	4.981ms	50	50	100.00
V2	stress	aes_stress	18.000s	675.990us	50	50	100.00
V2	sideload	aes_stress	18.000s	675.990us	50	50	100.00
		aes_sideload	14.000s	1.618ms	50	50	100.00
V2	deinitialization	aes_deinit	54.000s	1.782ms	50	50	100.00
V2	stress_all	aes_stress_all	1.600m	2.457ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	80.370us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	12.000s	129.874us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	12.000s	129.874us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	7.000s	133.375us	5	5	100.00
		aes_csr_rw	11.000s	108.702us	20	20	100.00
		aes_csr_aliasing	7.000s	70.527us	5	5	100.00
		aes_same_csr_outstanding	8.000s	266.557us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	7.000s	133.375us	5	5	100.00
		aes_csr_rw	11.000s	108.702us	20	20	100.00
		aes_csr_aliasing	7.000s	70.527us	5	5	100.00
		aes_same_csr_outstanding	8.000s	266.557us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	21.000s	2.475ms	49	50	98.00
V2S	fault_inject	aes_fi	54.000s	1.841ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	280	300	93.33
		aes_cipher_fi	56.000s	10.017ms	335	350	95.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	13.000s	174.003us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	13.000s	174.003us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	13.000s	174.003us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	13.000s	174.003us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	10.000s	310.971us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.063ms	5	5	100.00
		aes_tl_intg_err	15.000s	132.127us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	15.000s	132.127us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.367m	4.981ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	13.000s	174.003us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	18.000s	429.586us	50	50	100.00
		aes_stress	18.000s	675.990us	50	50	100.00
		aes_alert_reset	1.367m	4.981ms	50	50	100.00
		aes_core_fi	14.000s	841.739us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	13.000s	174.003us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	66.541us	50	50	100.00
		aes_stress	18.000s	675.990us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	18.000s	675.990us	50	50	100.00
		aes_sideload	14.000s	1.618ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	66.541us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	66.541us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	66.541us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	66.541us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	66.541us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	18.000s	675.990us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	18.000s	675.990us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	54.000s	1.841ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	54.000s	1.841ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	280	300	93.33
		aes_cipher_fi	56.000s	10.017ms	335	350	95.71
		aes_ctr_fi	14.000s	66.114us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	54.000s	1.841ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	54.000s	1.841ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	280	300	93.33
		aes_cipher_fi	56.000s	10.017ms	335	350	95.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	56.000s	10.017ms	335	350	95.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	54.000s	1.841ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	54.000s	1.841ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	280	300	93.33
		aes_ctr_fi	14.000s	66.114us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	54.000s	1.841ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	280	300	93.33
		aes_cipher_fi	56.000s	10.017ms	335	350	95.71
		aes_ctr_fi	14.000s	66.114us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.367m	4.981ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	54.000s	1.841ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	280	300	93.33
		aes_cipher_fi	56.000s	10.017ms	335	350	95.71
		aes_ctr_fi	14.000s	66.114us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	54.000s	1.841ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	280	300	93.33
		aes_cipher_fi	56.000s	10.017ms	335	350	95.71
		aes_ctr_fi	14.000s	66.114us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	54.000s	1.841ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	280	300	93.33
		aes_ctr_fi	14.000s	66.114us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	54.000s	1.841ms	50	50	100.00
		aes_control_fi	50.000s	10.008ms	280	300	93.33
		aes_cipher_fi	56.000s	10.017ms	335	350	95.71
V2S		TOTAL			949	985	96.35
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.700m	15.002ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1556	1602	97.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.55	99.03	97.58	99.43	95.90	95.60	97.78	98.97	98.17

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test aes_control_fi has 14 failures.
  - 4.aes_control_fi.3562122497
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job ID: smart:9ffec699-7d9e-4f56-b920-f9a2e7b7b983
```
  - 20.aes_control_fi.3652636367
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:a8e77c6e-8fa5-4fa3-a963-ac4724af65df
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 7 failures.
  - 5.aes_cipher_fi.456260915
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f95d7c03-9fc3-4a02-a3d1-0e5ec9964454
```
  - 46.aes_cipher_fi.3923145546
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/46.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4bdd870b-75ab-4cf6-ad3b-bed339581aa0
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

1.aes_stress_all_with_rand_reset.572644511
Line 1698, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3525398859 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3525398859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.1519701395
Line 1694, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1738380033 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1738380033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:

Test aes_cipher_fi has 8 failures.

16.aes_cipher_fi.2668596229
Line 278, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10016871438 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016871438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

142.aes_cipher_fi.2205766928
Line 276, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/142.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10019164398 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019164398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:

Test aes_control_fi has 6 failures.

61.aes_control_fi.3467968865
Line 277, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/61.aes_control_fi/latest/run.log

  UVM_FATAL @ 10036605186 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10036605186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

69.aes_control_fi.3897271321
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/69.aes_control_fi/latest/run.log

  UVM_FATAL @ 10007734431 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007734431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (cip_base_vseq.sv:520) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

0.aes_stress_all_with_rand_reset.3394714119
Line 372, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3769680692 ps: (cip_base_vseq.sv:520) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 3769680692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.3758751494
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  83557634 ps: (cip_base_vseq.sv:520) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  83557634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 27.aes_reseed.1341804588
    Line 1077, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_reseed/latest/run.log
```
  UVM_FATAL @  69758362 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  69758362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```