AES/MASKED Simulation Results

Sunday January 07 2024 20:02:41 UTC

GitHub Revision: `042415198f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 94802583296605211241780338187580260959003534163885373932116464911642413280689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	419.171us	1	1	100.00
V1	smoke	aes_smoke	14.000s	715.507us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	88.448us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	125.294us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	622.675us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	1.133m	10.253ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	98.487us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	125.294us	20	20	100.00
		aes_csr_aliasing	1.133m	10.253ms	4	5	80.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	14.000s	715.507us	50	50	100.00
		aes_config_error	10.000s	387.452us	50	50	100.00
		aes_stress	11.000s	480.881us	50	50	100.00
V2	key_length	aes_smoke	14.000s	715.507us	50	50	100.00
		aes_config_error	10.000s	387.452us	50	50	100.00
		aes_stress	11.000s	480.881us	50	50	100.00
V2	back2back	aes_stress	11.000s	480.881us	50	50	100.00
		aes_b2b	28.000s	314.813us	50	50	100.00
V2	backpressure	aes_stress	11.000s	480.881us	50	50	100.00
V2	multi_message	aes_smoke	14.000s	715.507us	50	50	100.00
		aes_config_error	10.000s	387.452us	50	50	100.00
		aes_stress	11.000s	480.881us	50	50	100.00
		aes_alert_reset	13.000s	414.655us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	100.697us	50	50	100.00
		aes_config_error	10.000s	387.452us	50	50	100.00
		aes_alert_reset	13.000s	414.655us	50	50	100.00
V2	trigger_clear_test	aes_clear	29.000s	1.665ms	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	1.264ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	414.655us	50	50	100.00
V2	stress	aes_stress	11.000s	480.881us	50	50	100.00
V2	sideload	aes_stress	11.000s	480.881us	50	50	100.00
		aes_sideload	17.000s	1.005ms	50	50	100.00
V2	deinitialization	aes_deinit	28.000s	805.307us	50	50	100.00
V2	stress_all	aes_stress_all	1.967m	9.369ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	60.782us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	13.000s	96.825us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	13.000s	96.825us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	88.448us	5	5	100.00
		aes_csr_rw	8.000s	125.294us	20	20	100.00
		aes_csr_aliasing	1.133m	10.253ms	4	5	80.00
		aes_same_csr_outstanding	4.000s	131.563us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	88.448us	5	5	100.00
		aes_csr_rw	8.000s	125.294us	20	20	100.00
		aes_csr_aliasing	1.133m	10.253ms	4	5	80.00
		aes_same_csr_outstanding	4.000s	131.563us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	14.000s	406.983us	49	50	98.00
V2S	fault_inject	aes_fi	11.000s	212.165us	50	50	100.00
		aes_control_fi	47.000s	10.007ms	287	300	95.67
		aes_cipher_fi	51.000s	10.014ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	12.000s	144.459us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	12.000s	144.459us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	12.000s	144.459us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	12.000s	144.459us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	169.931us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	793.548us	5	5	100.00
		aes_tl_intg_err	13.000s	188.624us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	13.000s	188.624us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	414.655us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	12.000s	144.459us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	715.507us	50	50	100.00
		aes_stress	11.000s	480.881us	50	50	100.00
		aes_alert_reset	13.000s	414.655us	50	50	100.00
		aes_core_fi	1.517m	10.006ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	12.000s	144.459us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	72.525us	50	50	100.00
		aes_stress	11.000s	480.881us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	11.000s	480.881us	50	50	100.00
		aes_sideload	17.000s	1.005ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	72.525us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	72.525us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	72.525us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	72.525us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	72.525us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	11.000s	480.881us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	11.000s	480.881us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	11.000s	212.165us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	11.000s	212.165us	50	50	100.00
		aes_control_fi	47.000s	10.007ms	287	300	95.67
		aes_cipher_fi	51.000s	10.014ms	341	350	97.43
		aes_ctr_fi	9.000s	63.736us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	11.000s	212.165us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	11.000s	212.165us	50	50	100.00
		aes_control_fi	47.000s	10.007ms	287	300	95.67
		aes_cipher_fi	51.000s	10.014ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.014ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	11.000s	212.165us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	11.000s	212.165us	50	50	100.00
		aes_control_fi	47.000s	10.007ms	287	300	95.67
		aes_ctr_fi	9.000s	63.736us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	11.000s	212.165us	50	50	100.00
		aes_control_fi	47.000s	10.007ms	287	300	95.67
		aes_cipher_fi	51.000s	10.014ms	341	350	97.43
		aes_ctr_fi	9.000s	63.736us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	414.655us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	11.000s	212.165us	50	50	100.00
		aes_control_fi	47.000s	10.007ms	287	300	95.67
		aes_cipher_fi	51.000s	10.014ms	341	350	97.43
		aes_ctr_fi	9.000s	63.736us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	11.000s	212.165us	50	50	100.00
		aes_control_fi	47.000s	10.007ms	287	300	95.67
		aes_cipher_fi	51.000s	10.014ms	341	350	97.43
		aes_ctr_fi	9.000s	63.736us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	11.000s	212.165us	50	50	100.00
		aes_control_fi	47.000s	10.007ms	287	300	95.67
		aes_ctr_fi	9.000s	63.736us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	11.000s	212.165us	50	50	100.00
		aes_control_fi	47.000s	10.007ms	287	300	95.67
		aes_cipher_fi	51.000s	10.014ms	341	350	97.43
V2S		TOTAL			956	985	97.06
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.200m	16.289ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1561	1602	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.51	98.99	97.47	99.43	95.77	95.60	97.78	98.97	97.97

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test aes_control_fi has 10 failures.
  - 12.aes_control_fi.86853523338589719924668152984355904947893728423376554984809590946727413809398
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  Job ID: smart:d07b110b-c45a-463e-ac2d-36273e1a5e0a
```
  - 15.aes_control_fi.106635484699191712593643115216331388821386297217821888827091944175633627395448
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  Job ID: smart:bf3f38eb-d8a3-4e4c-bb38-c8161815d402
```
  - ... and 8 more failures.
- Test aes_cipher_fi has 2 failures.
  - 148.aes_cipher_fi.23516599618187014665305255279932289458456531674411493963392504355563909525466
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/148.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1a2e6a84-662e-4f38-a3bd-2f65e58b262a
```
  - 286.aes_cipher_fi.42486254221301447861902541840789952607816119511921207309099447139753275386179
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/286.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9202dcf7-9d4e-430d-ae4a-6684d3a7d346
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.40122762691257658862589157760046153939839922743991678921737118932373985010989
Line 1685, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2613870233 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2613870233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.66892735909492800083935884207213124388641414150205367750431228303894917123229
Line 754, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1122600506 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1122600506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 147.aes_cipher_fi.9780111775867984255085538221520209135248457361996382390303691450829593897520
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/147.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016469123 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016469123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 167.aes_cipher_fi.95128067418156451004391665440821246535248696020545984399649755937790045004790
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/167.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011065484 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011065484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_core_fi has 6 failures.
  - 11.aes_core_fi.61607484898251443807202288211630817032488395546017099196840333236604820066046
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006378011 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006378011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.aes_core_fi.23748260896442061736816224087070366287417410049489456802817002177778765694662
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/22.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008685537 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008685537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 1.aes_control_fi.52607796824893224536940000729244313219788153496161598971183572813422001310621
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013831221 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013831221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 228.aes_control_fi.51554824754325039534344822344916991450110559235829988193803042963339594328549
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/228.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006968120 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006968120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_aliasing has 1 failures.
  - 1.aes_csr_aliasing.46980108241248556640362620107805794875638715197610094909191442107415717656585
    Line 289, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_csr_aliasing/latest/run.log
```
  UVM_FATAL @ 10252509651 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x1fd66084) == 0x0
  UVM_INFO @ 10252509651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.50012334518440587815772604508077374923063658575119473658409104726703396093964
    Line 872, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 335968727 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 335968727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:714) scoreboard [scoreboard] has 1 failures:
- Test aes_clear has 1 failures.
  - 13.aes_clear.103683153075722436014786125724851068643960047780436047244609663475702666111039
    Line 14325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_clear/latest/run.log
```
  UVM_FATAL @ 215607333 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       ----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
       ----| Expected:           5
       ----| Seen:               6
       ----| Expected corrupted: 0
```
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 34.aes_reseed.75768555130492525423470372290056783035580986580103999506553187060716243720661
    Line 1032, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_reseed/latest/run.log
```
  UVM_FATAL @  68227804 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  68227804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```