93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 0 | 1 | 0.00 | ||
| V1 | smoke | aes_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | aes_csr_hw_reset | 3.000s | 70.574us | 5 | 5 | 100.00 |
| V1 | csr_rw | aes_csr_rw | 4.000s | 53.590us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aes_csr_bit_bash | 13.000s | 3.325ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aes_csr_aliasing | 5.000s | 252.003us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 5.000s | 31.685us | 1 | 20 | 5.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 4.000s | 53.590us | 20 | 20 | 100.00 |
| aes_csr_aliasing | 5.000s | 252.003us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 36 | 106 | 33.96 | |||
| V2 | algorithm | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2 | key_length | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2 | back2back | aes_stress | 0 | 50 | 0.00 | ||
| aes_b2b | 0 | 50 | 0.00 | ||||
| V2 | backpressure | aes_stress | 0 | 50 | 0.00 | ||
| V2 | multi_message | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| V2 | failure_test | aes_man_cfg_err | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| V2 | trigger_clear_test | aes_clear | 0 | 50 | 0.00 | ||
| V2 | nist_test_vectors | aes_nist_vectors | 0 | 1 | 0.00 | ||
| V2 | reset_recovery | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2 | stress | aes_stress | 0 | 50 | 0.00 | ||
| V2 | sideload | aes_stress | 0 | 50 | 0.00 | ||
| aes_sideload | 0 | 50 | 0.00 | ||||
| V2 | deinitialization | aes_deinit | 0 | 50 | 0.00 | ||
| V2 | stress_all | aes_stress_all | 0 | 10 | 0.00 | ||
| V2 | alert_test | aes_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | aes_tl_errors | 6.000s | 518.146us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aes_tl_errors | 6.000s | 518.146us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 3.000s | 70.574us | 5 | 5 | 100.00 |
| aes_csr_rw | 4.000s | 53.590us | 20 | 20 | 100.00 | ||
| aes_csr_aliasing | 5.000s | 252.003us | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 4.000s | 864.845us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 3.000s | 70.574us | 5 | 5 | 100.00 |
| aes_csr_rw | 4.000s | 53.590us | 20 | 20 | 100.00 | ||
| aes_csr_aliasing | 5.000s | 252.003us | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 4.000s | 864.845us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 40 | 501 | 7.98 | |||
| V2S | reseeding | aes_reseed | 0 | 50 | 0.00 | ||
| V2S | fault_inject | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 3.000s | 61.380us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 3.000s | 61.380us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 3.000s | 61.380us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 3.000s | 61.380us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 5.000s | 88.290us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | aes_sec_cm | 0 | 5 | 0.00 | ||
| aes_tl_intg_err | 7.000s | 515.720us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 7.000s | 515.720us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 3.000s | 61.380us | 20 | 20 | 100.00 |
| V2S | sec_cm_main_config_sparse | aes_smoke | 0 | 50 | 0.00 | ||
| aes_stress | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| aes_core_fi | 0 | 70 | 0.00 | ||||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 3.000s | 61.380us | 20 | 20 | 100.00 |
| V2S | sec_cm_aux_config_regwen | aes_readability | 0 | 50 | 0.00 | ||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_key_sideload | aes_stress | 0 | 50 | 0.00 | ||
| aes_sideload | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_key_sca | aes_stress | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_masking | aes_stress | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 0 | 350 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_ctrl_sparse | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | TOTAL | 60 | 985 | 6.09 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 0 | 10 | 0.00 | ||
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 136 | 1602 | 8.49 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 4 | 57.14 |
| V2 | 13 | 13 | 2 | 15.38 |
| V2S | 11 | 11 | 3 | 27.27 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 83.99 | 99.38 | 98.15 | 99.87 | 99.74 | 44.47 | -- | 98.03 | 43.64 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 724 failures:
Test aes_wake_up has 1 failures.
Test aes_deinit has 28 failures.
0.aes_deinit.111041218879998039795905262660083492060713593185773294562552703606763952051611
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_deinit/latest/run.log
1.aes_deinit.56445416258067161196477764088643464151274440532818831152040066451571981581394
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_deinit/latest/run.log
... and 26 more failures.
Test aes_readability has 28 failures.
0.aes_readability.106687807385131779034203226506663398414407458123228320882443329815794127973969
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_readability/latest/run.log
1.aes_readability.11450335750336322547352716009080393223679310752192841880831760744015060897488
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_readability/latest/run.log
... and 26 more failures.
Test aes_config_error has 28 failures.
0.aes_config_error.90049803172099377718390523431082620027509687872310680595336980977726439937880
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_config_error/latest/run.log
1.aes_config_error.106750833719117991510154795207949465904400500099393187865556957553472738603341
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_config_error/latest/run.log
... and 26 more failures.
Test aes_b2b has 28 failures.
0.aes_b2b.73520052296424123671346397741581662959929666922523996051991509550201198582921
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_b2b/latest/run.log
1.aes_b2b.95396605412271096019583964036576390278377942722527359653485064489624503968077
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_b2b/latest/run.log
... and 26 more failures.
... and 16 more tests.
Job killed most likely because its dependent job failed. has 723 failures:
Test aes_nist_vectors has 1 failures.
Test aes_man_cfg_err has 28 failures.
0.aes_man_cfg_err.102779846984303422840878902174865122114633323380525530209263345040168369980722
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
1.aes_man_cfg_err.113918808763618569825194309041263865433635929905700704328252028087973128897116
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
... and 26 more failures.
Test aes_smoke has 28 failures.
0.aes_smoke.70684714412029718467774802272478414949616527777951885432223455701048323832186
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_smoke/latest/run.log
1.aes_smoke.8438247571211148949255746722542819262810754393372752542630609563321468205710
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_smoke/latest/run.log
... and 26 more failures.
Test aes_stress has 28 failures.
0.aes_stress.70068413695582693132441507657096936905558155450930155130492287530332213035529
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress/latest/run.log
1.aes_stress.64566601258494049028465771916557187890129294524926172230082950701684189434299
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress/latest/run.log
... and 26 more failures.
Test aes_clear has 28 failures.
0.aes_clear.106130016133675904179400334935757561738657797990865007122189971008240532189170
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_clear/latest/run.log
1.aes_clear.107112488878911072755604076819969958617531329919062004327866853646917311914626
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_clear/latest/run.log
... and 26 more failures.
... and 15 more tests.
UVM_ERROR (cip_base_vseq.sv:757) [aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 10 failures:
1.aes_csr_mem_rw_with_rand_reset.91647480435900537656246619857217221537769075730558853847161477371309925024033
Line 292, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 31684584 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 31684584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.aes_csr_mem_rw_with_rand_reset.69035257512907806766777409101044043084810601043005845241937702997427294614149
Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 80606505 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 80606505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:757) [aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 9 failures:
0.aes_csr_mem_rw_with_rand_reset.106646936201571408191992815252550901500123106167068982046266108009807857866361
Line 284, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 65597393 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 65597393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.aes_csr_mem_rw_with_rand_reset.71429375393913451828230980714876999979731039562870672213569781910176374296255
Line 291, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 45625456 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 45625456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.