AES/MASKED Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	97.049us	1	1	100.00
V1	smoke	aes_smoke	15.000s	1.006ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	104.072us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	51.069us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	380.708us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	172.762us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	60.239us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	51.069us	20	20	100.00
		aes_csr_aliasing	5.000s	172.762us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	15.000s	1.006ms	50	50	100.00
		aes_config_error	22.000s	390.470us	50	50	100.00
		aes_stress	28.000s	866.805us	50	50	100.00
V2	key_length	aes_smoke	15.000s	1.006ms	50	50	100.00
		aes_config_error	22.000s	390.470us	50	50	100.00
		aes_stress	28.000s	866.805us	50	50	100.00
V2	back2back	aes_stress	28.000s	866.805us	50	50	100.00
		aes_b2b	38.000s	1.252ms	50	50	100.00
V2	backpressure	aes_stress	28.000s	866.805us	50	50	100.00
V2	multi_message	aes_smoke	15.000s	1.006ms	50	50	100.00
		aes_config_error	22.000s	390.470us	50	50	100.00
		aes_stress	28.000s	866.805us	50	50	100.00
		aes_alert_reset	26.000s	2.104ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	131.744us	50	50	100.00
		aes_config_error	22.000s	390.470us	50	50	100.00
		aes_alert_reset	26.000s	2.104ms	50	50	100.00
V2	trigger_clear_test	aes_clear	28.000s	2.357ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	564.881us	1	1	100.00
V2	reset_recovery	aes_alert_reset	26.000s	2.104ms	50	50	100.00
V2	stress	aes_stress	28.000s	866.805us	50	50	100.00
V2	sideload	aes_stress	28.000s	866.805us	50	50	100.00
		aes_sideload	18.000s	545.542us	50	50	100.00
V2	deinitialization	aes_deinit	15.000s	74.861us	50	50	100.00
V2	stress_all	aes_stress_all	2.500m	59.534ms	10	10	100.00
V2	alert_test	aes_alert_test	15.000s	226.605us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	182.433us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	182.433us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	104.072us	5	5	100.00
		aes_csr_rw	4.000s	51.069us	20	20	100.00
		aes_csr_aliasing	5.000s	172.762us	5	5	100.00
		aes_same_csr_outstanding	4.000s	228.814us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	104.072us	5	5	100.00
		aes_csr_rw	4.000s	51.069us	20	20	100.00
		aes_csr_aliasing	5.000s	172.762us	5	5	100.00
		aes_same_csr_outstanding	4.000s	228.814us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	36.000s	823.888us	49	50	98.00
V2S	fault_inject	aes_fi	23.000s	1.780ms	50	50	100.00
		aes_control_fi	47.000s	10.007ms	278	300	92.67
		aes_cipher_fi	49.000s	10.007ms	343	350	98.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	54.540us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	54.540us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	54.540us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	54.540us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	147.696us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	18.000s	1.410ms	5	5	100.00
		aes_tl_intg_err	9.000s	211.486us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	211.486us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	26.000s	2.104ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	54.540us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	15.000s	1.006ms	50	50	100.00
		aes_stress	28.000s	866.805us	50	50	100.00
		aes_alert_reset	26.000s	2.104ms	50	50	100.00
		aes_core_fi	1.567m	10.003ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	54.540us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	162.940us	50	50	100.00
		aes_stress	28.000s	866.805us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	28.000s	866.805us	50	50	100.00
		aes_sideload	18.000s	545.542us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	162.940us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	162.940us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	162.940us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	162.940us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	162.940us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	28.000s	866.805us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	28.000s	866.805us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	23.000s	1.780ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	23.000s	1.780ms	50	50	100.00
		aes_control_fi	47.000s	10.007ms	278	300	92.67
		aes_cipher_fi	49.000s	10.007ms	343	350	98.00
		aes_ctr_fi	19.000s	59.766us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	23.000s	1.780ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	23.000s	1.780ms	50	50	100.00
		aes_control_fi	47.000s	10.007ms	278	300	92.67
		aes_cipher_fi	49.000s	10.007ms	343	350	98.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.007ms	343	350	98.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	23.000s	1.780ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	23.000s	1.780ms	50	50	100.00
		aes_control_fi	47.000s	10.007ms	278	300	92.67
		aes_ctr_fi	19.000s	59.766us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	23.000s	1.780ms	50	50	100.00
		aes_control_fi	47.000s	10.007ms	278	300	92.67
		aes_cipher_fi	49.000s	10.007ms	343	350	98.00
		aes_ctr_fi	19.000s	59.766us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	26.000s	2.104ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	23.000s	1.780ms	50	50	100.00
		aes_control_fi	47.000s	10.007ms	278	300	92.67
		aes_cipher_fi	49.000s	10.007ms	343	350	98.00
		aes_ctr_fi	19.000s	59.766us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	23.000s	1.780ms	50	50	100.00
		aes_control_fi	47.000s	10.007ms	278	300	92.67
		aes_cipher_fi	49.000s	10.007ms	343	350	98.00
		aes_ctr_fi	19.000s	59.766us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	23.000s	1.780ms	50	50	100.00
		aes_control_fi	47.000s	10.007ms	278	300	92.67
		aes_ctr_fi	19.000s	59.766us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	23.000s	1.780ms	50	50	100.00
		aes_control_fi	47.000s	10.007ms	278	300	92.67
		aes_cipher_fi	49.000s	10.007ms	343	350	98.00
V2S		TOTAL			951	985	96.55
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.083m	10.992ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1558	1602	97.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.32	98.53	96.25	99.42	95.65	97.72	97.78	98.96	97.01

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test aes_cipher_fi has 1 failures.
  - 1.aes_cipher_fi.39664603207050056391834131234641612024829943556601544386177283472388005286870
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  Job ID: smart:aee77765-0c4c-4f37-b028-cb9a7162fa10
```
- Test aes_control_fi has 13 failures.
  - 36.aes_control_fi.82726057060002204211765825602952102799028637338165107055904916167571881977715
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  Job ID: smart:28a514cf-37aa-492a-949c-1adbce80abe5
```
  - 59.aes_control_fi.100812840588901835436282309243987410872081116200528505124366730242062116107380
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/59.aes_control_fi/latest/run.log
```
  Job ID: smart:9b827ba1-6ae9-4205-b209-5446ea7af4b8
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 19.aes_control_fi.72564247454896233590833415110603023685570086823982029644113234064114769022844
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014584821 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014584821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 188.aes_control_fi.78679266710236063300495696438975240108568319861826849936466108789262644507629
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/188.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010072576 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010072576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

1.aes_stress_all_with_rand_reset.11402850936821727291532938204650188316750503274707226244072672720292653938868
Line 1341, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10992101566 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 10992101566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.55269899974658881213870112722040611710107438692833402683315136386564662549822
Line 634, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 898012625 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 898012625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 13.aes_cipher_fi.86655199322302984252214527268743847926147459115584178589316286618561215606929
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015519900 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015519900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 83.aes_cipher_fi.84118594683587123763090099474546344583098536781949491839106178237505069899665
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/83.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006573562 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006573562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 30.aes_core_fi.83198095922707040646461114723162275109580622865185438491185300339654198749379
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/30.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003720976 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003720976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.aes_core_fi.38668207951644377357481825882874493545383153439310852836970062958269031715391
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019091586 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019091586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.15089240131192228909941929094804341177534180895577400008424534786815509326070
Line 833, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 674193282 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 674193282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.39385103448607173886814939553970755433854801116051338903657411130032314364377
Line 1467, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1591198580 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1591198580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 46.aes_reseed.10390541711124277259621367944256360028406174003210931185513119075405479143144
    Line 5800, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/46.aes_reseed/latest/run.log
```
  UVM_FATAL @ 589619188 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 589619188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```