AES/MASKED Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	53.982us	1	1	100.00
V1	smoke	aes_smoke	20.000s	108.915us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	7.000s	85.655us	5	5	100.00
V1	csr_rw	aes_csr_rw	23.000s	308.775us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	16.000s	2.803ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	1.633m	10.151ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	90.719us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	23.000s	308.775us	20	20	100.00
		aes_csr_aliasing	1.633m	10.151ms	4	5	80.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	20.000s	108.915us	50	50	100.00
		aes_config_error	27.000s	1.320ms	50	50	100.00
		aes_stress	2.333m	4.185ms	50	50	100.00
V2	key_length	aes_smoke	20.000s	108.915us	50	50	100.00
		aes_config_error	27.000s	1.320ms	50	50	100.00
		aes_stress	2.333m	4.185ms	50	50	100.00
V2	back2back	aes_stress	2.333m	4.185ms	50	50	100.00
		aes_b2b	30.000s	603.293us	50	50	100.00
V2	backpressure	aes_stress	2.333m	4.185ms	50	50	100.00
V2	multi_message	aes_smoke	20.000s	108.915us	50	50	100.00
		aes_config_error	27.000s	1.320ms	50	50	100.00
		aes_stress	2.333m	4.185ms	50	50	100.00
		aes_alert_reset	18.000s	622.667us	50	50	100.00
V2	failure_test	aes_man_cfg_err	18.000s	53.150us	50	50	100.00
		aes_config_error	27.000s	1.320ms	50	50	100.00
		aes_alert_reset	18.000s	622.667us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.333m	2.487ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	309.131us	1	1	100.00
V2	reset_recovery	aes_alert_reset	18.000s	622.667us	50	50	100.00
V2	stress	aes_stress	2.333m	4.185ms	50	50	100.00
V2	sideload	aes_stress	2.333m	4.185ms	50	50	100.00
		aes_sideload	22.000s	334.395us	50	50	100.00
V2	deinitialization	aes_deinit	15.000s	1.835ms	50	50	100.00
V2	stress_all	aes_stress_all	2.133m	4.737ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	52.351us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	111.667us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	111.667us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	7.000s	85.655us	5	5	100.00
		aes_csr_rw	23.000s	308.775us	20	20	100.00
		aes_csr_aliasing	1.633m	10.151ms	4	5	80.00
		aes_same_csr_outstanding	18.000s	99.638us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	7.000s	85.655us	5	5	100.00
		aes_csr_rw	23.000s	308.775us	20	20	100.00
		aes_csr_aliasing	1.633m	10.151ms	4	5	80.00
		aes_same_csr_outstanding	18.000s	99.638us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	3.933m	7.177ms	50	50	100.00
V2S	fault_inject	aes_fi	23.000s	762.171us	49	50	98.00
		aes_control_fi	48.000s	10.007ms	280	300	93.33
		aes_cipher_fi	29.000s	10.011ms	344	350	98.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	13.000s	157.652us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	13.000s	157.652us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	13.000s	157.652us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	13.000s	157.652us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	278.578us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	12.000s	1.423ms	5	5	100.00
		aes_tl_intg_err	15.000s	501.653us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	15.000s	501.653us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	18.000s	622.667us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	13.000s	157.652us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	20.000s	108.915us	50	50	100.00
		aes_stress	2.333m	4.185ms	50	50	100.00
		aes_alert_reset	18.000s	622.667us	50	50	100.00
		aes_core_fi	1.467m	10.005ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	13.000s	157.652us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	136.519us	50	50	100.00
		aes_stress	2.333m	4.185ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	2.333m	4.185ms	50	50	100.00
		aes_sideload	22.000s	334.395us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	136.519us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	136.519us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	136.519us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	136.519us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	136.519us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.333m	4.185ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	2.333m	4.185ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	23.000s	762.171us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	23.000s	762.171us	49	50	98.00
		aes_control_fi	48.000s	10.007ms	280	300	93.33
		aes_cipher_fi	29.000s	10.011ms	344	350	98.29
		aes_ctr_fi	14.000s	71.249us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	23.000s	762.171us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	23.000s	762.171us	49	50	98.00
		aes_control_fi	48.000s	10.007ms	280	300	93.33
		aes_cipher_fi	29.000s	10.011ms	344	350	98.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	29.000s	10.011ms	344	350	98.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	23.000s	762.171us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	23.000s	762.171us	49	50	98.00
		aes_control_fi	48.000s	10.007ms	280	300	93.33
		aes_ctr_fi	14.000s	71.249us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	23.000s	762.171us	49	50	98.00
		aes_control_fi	48.000s	10.007ms	280	300	93.33
		aes_cipher_fi	29.000s	10.011ms	344	350	98.29
		aes_ctr_fi	14.000s	71.249us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	18.000s	622.667us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	23.000s	762.171us	49	50	98.00
		aes_control_fi	48.000s	10.007ms	280	300	93.33
		aes_cipher_fi	29.000s	10.011ms	344	350	98.29
		aes_ctr_fi	14.000s	71.249us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	23.000s	762.171us	49	50	98.00
		aes_control_fi	48.000s	10.007ms	280	300	93.33
		aes_cipher_fi	29.000s	10.011ms	344	350	98.29
		aes_ctr_fi	14.000s	71.249us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	23.000s	762.171us	49	50	98.00
		aes_control_fi	48.000s	10.007ms	280	300	93.33
		aes_ctr_fi	14.000s	71.249us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	23.000s	762.171us	49	50	98.00
		aes_control_fi	48.000s	10.007ms	280	300	93.33
		aes_cipher_fi	29.000s	10.011ms	344	350	98.29
V2S		TOTAL			955	985	96.95
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	17.867m	34.227ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1561	1602	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.31	98.50	96.19	99.42	95.72	97.64	97.78	99.11	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test aes_control_fi has 14 failures.
  - 21.aes_control_fi.87328390895212001663430780176595595839798986911515970060743470545173450583221
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  Job ID: smart:af515746-75aa-4624-af83-4448e076fba0
```
  - 44.aes_control_fi.66632727917434387635480004920551447139372997342536261161683511920926118438208
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_control_fi/latest/run.log
```
  Job ID: smart:9c71eb3e-59d7-452a-aab6-850e0ff2b98a
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 3 failures.
  - 169.aes_cipher_fi.80928392595076675564154108152214136120770702305545298482275901942934991772502
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/169.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d44e1263-45de-4b46-bbd8-292929d001aa
```
  - 307.aes_cipher_fi.62300132354545479051489720327885012402193822369150857273997672661241063816284
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/307.aes_cipher_fi/latest/run.log
```
  Job ID: smart:429969b8-cdb4-41a3-a649-9c8af7b4aab7
```
  - ... and 1 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.74350004981673390814180672882203612701612027536984755012959793903685964406842
Line 894, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 34226949000 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 34226949000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.99315126085591719710474971239475159185995081748716112993435440116461341949501
Line 1002, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1162147099 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1162147099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 8.aes_control_fi.110354203728544475297200217398793689115558032858001704915544931834907817405783
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10022995567 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022995567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.aes_control_fi.104720386808405875475558881661723284254346938771915288444719652203041147310102
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/48.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004502369 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004502369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 7.aes_core_fi.46836582712317912005954322495484332821336104573036542189240587767422380578811
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004862207 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004862207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.aes_core_fi.22737252999784467753259302759987766663174592895408829511346024753706800452070
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016081624 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016081624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 12.aes_cipher_fi.67222284403479628975353532265351816380415897192158955288256524663396632616659
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10022074045 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022074045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 126.aes_cipher_fi.60036295799397154485968878985364469597969212696227491923799844903595055567361
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/126.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10037027262 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10037027262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_aliasing has 1 failures.
  - 2.aes_csr_aliasing.10232647951384075209153582958728975910849141964565949021784616771158920502389
    Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_csr_aliasing/latest/run.log
```
  UVM_FATAL @ 10150772724 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x1695dc84) == 0x0
  UVM_INFO @ 10150772724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.12058230504365400619850643173811186227737685404519860351376927694277789615447
    Line 901, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 823200674 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 823200674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.3829340326692689753288803201989158291649197391120203255593923823188231606427
    Line 566, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1560517027 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1560517027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 36.aes_fi.1510771071564411830797184196935801999799081871852733701826762039917015600892
    Line 6071, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_fi/latest/run.log
```
  UVM_FATAL @  49738310 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  49738310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```