AES/MASKED Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	73.159us	1	1	100.00
V1	smoke	aes_smoke	1.467m	2.676ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	58.910us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	79.931us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	2.612ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	712.635us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	166.198us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	79.931us	20	20	100.00
		aes_csr_aliasing	5.000s	712.635us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.467m	2.676ms	50	50	100.00
		aes_config_error	37.000s	1.440ms	50	50	100.00
		aes_stress	1.567m	4.695ms	50	50	100.00
V2	key_length	aes_smoke	1.467m	2.676ms	50	50	100.00
		aes_config_error	37.000s	1.440ms	50	50	100.00
		aes_stress	1.567m	4.695ms	50	50	100.00
V2	back2back	aes_stress	1.567m	4.695ms	50	50	100.00
		aes_b2b	51.000s	1.190ms	50	50	100.00
V2	backpressure	aes_stress	1.567m	4.695ms	50	50	100.00
V2	multi_message	aes_smoke	1.467m	2.676ms	50	50	100.00
		aes_config_error	37.000s	1.440ms	50	50	100.00
		aes_stress	1.567m	4.695ms	50	50	100.00
		aes_alert_reset	15.000s	909.799us	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	249.284us	50	50	100.00
		aes_config_error	37.000s	1.440ms	50	50	100.00
		aes_alert_reset	15.000s	909.799us	50	50	100.00
V2	trigger_clear_test	aes_clear	38.000s	1.164ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	367.817us	1	1	100.00
V2	reset_recovery	aes_alert_reset	15.000s	909.799us	50	50	100.00
V2	stress	aes_stress	1.567m	4.695ms	50	50	100.00
V2	sideload	aes_stress	1.567m	4.695ms	50	50	100.00
		aes_sideload	13.000s	724.205us	50	50	100.00
V2	deinitialization	aes_deinit	55.000s	1.891ms	50	50	100.00
V2	stress_all	aes_stress_all	1.417m	3.337ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	79.675us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	210.035us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	210.035us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	58.910us	5	5	100.00
		aes_csr_rw	3.000s	79.931us	20	20	100.00
		aes_csr_aliasing	5.000s	712.635us	5	5	100.00
		aes_same_csr_outstanding	4.000s	85.113us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	58.910us	5	5	100.00
		aes_csr_rw	3.000s	79.931us	20	20	100.00
		aes_csr_aliasing	5.000s	712.635us	5	5	100.00
		aes_same_csr_outstanding	4.000s	85.113us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	17.000s	471.115us	50	50	100.00
V2S	fault_inject	aes_fi	49.000s	1.892ms	49	50	98.00
		aes_control_fi	51.000s	10.006ms	277	300	92.33
		aes_cipher_fi	51.000s	10.005ms	339	350	96.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	450.925us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	450.925us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	450.925us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	450.925us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	492.746us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	822.758us	5	5	100.00
		aes_tl_intg_err	5.000s	651.993us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	651.993us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	15.000s	909.799us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	450.925us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.467m	2.676ms	50	50	100.00
		aes_stress	1.567m	4.695ms	50	50	100.00
		aes_alert_reset	15.000s	909.799us	50	50	100.00
		aes_core_fi	1.517m	10.003ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	450.925us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	436.670us	50	50	100.00
		aes_stress	1.567m	4.695ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.567m	4.695ms	50	50	100.00
		aes_sideload	13.000s	724.205us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	436.670us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	436.670us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	436.670us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	436.670us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	436.670us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.567m	4.695ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.567m	4.695ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	49.000s	1.892ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	49.000s	1.892ms	49	50	98.00
		aes_control_fi	51.000s	10.006ms	277	300	92.33
		aes_cipher_fi	51.000s	10.005ms	339	350	96.86
		aes_ctr_fi	8.000s	173.015us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	49.000s	1.892ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	49.000s	1.892ms	49	50	98.00
		aes_control_fi	51.000s	10.006ms	277	300	92.33
		aes_cipher_fi	51.000s	10.005ms	339	350	96.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.005ms	339	350	96.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	49.000s	1.892ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	49.000s	1.892ms	49	50	98.00
		aes_control_fi	51.000s	10.006ms	277	300	92.33
		aes_ctr_fi	8.000s	173.015us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	49.000s	1.892ms	49	50	98.00
		aes_control_fi	51.000s	10.006ms	277	300	92.33
		aes_cipher_fi	51.000s	10.005ms	339	350	96.86
		aes_ctr_fi	8.000s	173.015us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	15.000s	909.799us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	49.000s	1.892ms	49	50	98.00
		aes_control_fi	51.000s	10.006ms	277	300	92.33
		aes_cipher_fi	51.000s	10.005ms	339	350	96.86
		aes_ctr_fi	8.000s	173.015us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	49.000s	1.892ms	49	50	98.00
		aes_control_fi	51.000s	10.006ms	277	300	92.33
		aes_cipher_fi	51.000s	10.005ms	339	350	96.86
		aes_ctr_fi	8.000s	173.015us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	49.000s	1.892ms	49	50	98.00
		aes_control_fi	51.000s	10.006ms	277	300	92.33
		aes_ctr_fi	8.000s	173.015us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	49.000s	1.892ms	49	50	98.00
		aes_control_fi	51.000s	10.006ms	277	300	92.33
		aes_cipher_fi	51.000s	10.005ms	339	350	96.86
V2S		TOTAL			947	985	96.14
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.250m	7.458ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1554	1602	97.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	98.55	96.32	99.45	95.78	97.64	100.00	99.11	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test aes_control_fi has 15 failures.
  - 6.aes_control_fi.89052650082659353642248950251937968430714403001400275641664111529718079854472
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job ID: smart:cfe24def-a654-48d0-acd9-46ec41779e90
```
  - 52.aes_control_fi.75552945920866832318099337697914013314576078583255306735892436262889434139539
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  Job ID: smart:6cb515ae-a3fa-46a4-982a-de3cadee7c2b
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 2 failures.
  - 114.aes_cipher_fi.62566371567300882726829819709305966745968892146628804330105216070388191720184
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/114.aes_cipher_fi/latest/run.log
```
  Job ID: smart:958d3aca-2ce6-4b04-b29d-7e8b3ea633b6
```
  - 317.aes_cipher_fi.29852696565091211824930876614738956764989461547614935975052769188184375659319
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/317.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f6c976f2-2edf-4326-835e-e26ca833f78a
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 26.aes_cipher_fi.70216491504881934419261968623761250533946981227220274531653861818425582517376
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013760812 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013760812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 55.aes_cipher_fi.4383872123705339751247563487271690336372165556385754601093187143483399775767
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016459452 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016459452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 12.aes_control_fi.78072946941906864348084348304676046551805507236009322804189636671680395031797
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011368823 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011368823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.aes_control_fi.37886482756360949811855035248174556201211922405912496519810584674636795245119
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006298537 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006298537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.100141326029539804538983691884307181890703385855512271507529784871853125882007
Line 783, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7249417743 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 7249417743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.95773771090643492060785890376628768391373821263673858208367083200794335870609
Line 775, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 362473623 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 362473623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

2.aes_stress_all_with_rand_reset.53762459035793222776505045611481544767009705461411756836912308203268458106798
Line 951, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5216419690 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5216419690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.98417649820847189825018079234081453664873030835514030920662551469381905881794
Line 1716, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1827848931 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1827848931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 0.aes_core_fi.85432111742258113616631228738405395491903388804708111955109498724246690486056
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016354078 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016354078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.aes_core_fi.42021927046282218911839984673665902585939947341470586183111345419929846573790
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014140031 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014140031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 34.aes_fi.25381432189786155325944275767158673655524515865916711249923746729062995458081
    Line 2786, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 10721935 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 10709740 PS)
  UVM_ERROR @  10721935 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  10721935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```