AES/MASKED Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	95.883us	1	1	100.00
V1	smoke	aes_smoke	8.000s	240.257us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	119.904us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	216.856us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	599.879us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	1.766ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	206.345us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	216.856us	20	20	100.00
		aes_csr_aliasing	6.000s	1.766ms	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	8.000s	240.257us	50	50	100.00
		aes_config_error	23.000s	1.481ms	50	50	100.00
		aes_stress	48.000s	1.457ms	50	50	100.00
V2	key_length	aes_smoke	8.000s	240.257us	50	50	100.00
		aes_config_error	23.000s	1.481ms	50	50	100.00
		aes_stress	48.000s	1.457ms	50	50	100.00
V2	back2back	aes_stress	48.000s	1.457ms	50	50	100.00
		aes_b2b	36.000s	1.025ms	50	50	100.00
V2	backpressure	aes_stress	48.000s	1.457ms	50	50	100.00
V2	multi_message	aes_smoke	8.000s	240.257us	50	50	100.00
		aes_config_error	23.000s	1.481ms	50	50	100.00
		aes_stress	48.000s	1.457ms	50	50	100.00
		aes_alert_reset	55.000s	3.474ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	219.064us	50	50	100.00
		aes_config_error	23.000s	1.481ms	50	50	100.00
		aes_alert_reset	55.000s	3.474ms	50	50	100.00
V2	trigger_clear_test	aes_clear	35.000s	911.200us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	56.000s	13.632ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	55.000s	3.474ms	50	50	100.00
V2	stress	aes_stress	48.000s	1.457ms	50	50	100.00
V2	sideload	aes_stress	48.000s	1.457ms	50	50	100.00
		aes_sideload	16.000s	293.188us	50	50	100.00
V2	deinitialization	aes_deinit	23.000s	763.057us	50	50	100.00
V2	stress_all	aes_stress_all	40.267m	78.869ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	61.059us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	235.979us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	235.979us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	119.904us	5	5	100.00
		aes_csr_rw	3.000s	216.856us	20	20	100.00
		aes_csr_aliasing	6.000s	1.766ms	5	5	100.00
		aes_same_csr_outstanding	7.000s	280.416us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	119.904us	5	5	100.00
		aes_csr_rw	3.000s	216.856us	20	20	100.00
		aes_csr_aliasing	6.000s	1.766ms	5	5	100.00
		aes_same_csr_outstanding	7.000s	280.416us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	2.117m	4.956ms	50	50	100.00
V2S	fault_inject	aes_fi	59.000s	2.374ms	48	50	96.00
		aes_control_fi	50.000s	10.005ms	281	300	93.67
		aes_cipher_fi	48.000s	10.016ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	152.920us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	152.920us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	152.920us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	152.920us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.500m	10.081ms	19	20	95.00
V2S	tl_intg_err	aes_sec_cm	12.000s	1.182ms	5	5	100.00
		aes_tl_intg_err	6.000s	373.386us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	373.386us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	55.000s	3.474ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	152.920us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	240.257us	50	50	100.00
		aes_stress	48.000s	1.457ms	50	50	100.00
		aes_alert_reset	55.000s	3.474ms	50	50	100.00
		aes_core_fi	1.483m	10.005ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	152.920us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	62.445us	50	50	100.00
		aes_stress	48.000s	1.457ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	48.000s	1.457ms	50	50	100.00
		aes_sideload	16.000s	293.188us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	62.445us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	62.445us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	62.445us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	62.445us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	62.445us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	48.000s	1.457ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	48.000s	1.457ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	59.000s	2.374ms	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	59.000s	2.374ms	48	50	96.00
		aes_control_fi	50.000s	10.005ms	281	300	93.67
		aes_cipher_fi	48.000s	10.016ms	338	350	96.57
		aes_ctr_fi	6.000s	378.354us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	59.000s	2.374ms	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	59.000s	2.374ms	48	50	96.00
		aes_control_fi	50.000s	10.005ms	281	300	93.67
		aes_cipher_fi	48.000s	10.016ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.016ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	59.000s	2.374ms	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	59.000s	2.374ms	48	50	96.00
		aes_control_fi	50.000s	10.005ms	281	300	93.67
		aes_ctr_fi	6.000s	378.354us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	59.000s	2.374ms	48	50	96.00
		aes_control_fi	50.000s	10.005ms	281	300	93.67
		aes_cipher_fi	48.000s	10.016ms	338	350	96.57
		aes_ctr_fi	6.000s	378.354us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	55.000s	3.474ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	59.000s	2.374ms	48	50	96.00
		aes_control_fi	50.000s	10.005ms	281	300	93.67
		aes_cipher_fi	48.000s	10.016ms	338	350	96.57
		aes_ctr_fi	6.000s	378.354us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	59.000s	2.374ms	48	50	96.00
		aes_control_fi	50.000s	10.005ms	281	300	93.67
		aes_cipher_fi	48.000s	10.016ms	338	350	96.57
		aes_ctr_fi	6.000s	378.354us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	59.000s	2.374ms	48	50	96.00
		aes_control_fi	50.000s	10.005ms	281	300	93.67
		aes_ctr_fi	6.000s	378.354us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	59.000s	2.374ms	48	50	96.00
		aes_control_fi	50.000s	10.005ms	281	300	93.67
		aes_cipher_fi	48.000s	10.016ms	338	350	96.57
V2S		TOTAL			948	985	96.24
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	17.100m	61.331ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1554	1602	97.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	98.55	96.32	99.45	95.80	97.72	100.00	99.11	96.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
- Test aes_control_fi has 12 failures.
  - 9.aes_control_fi.32898717053796619877881013868621579113824556338869764946243591052191186128672
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  Job ID: smart:9ee861f5-32b1-4c14-b698-1f961d6e7165
```
  - 12.aes_control_fi.20463523662203367804614050188646027872706666810602945669351368274390776831262
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  Job ID: smart:1f7f1c92-da16-4c07-b8e9-c5626c94c630
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 6 failures.
  - 156.aes_cipher_fi.89373628616603076048487739004111219171493509537011331802683657282366631771252
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/156.aes_cipher_fi/latest/run.log
```
  Job ID: smart:026ba62d-1534-4e45-a809-82d70c51a57c
```
  - 211.aes_cipher_fi.102267403237769803835484719941426513211407352416998240247447832206724958552144
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/211.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4bbf8549-2268-4686-9adc-9bcdb8cdf7fb
```
  - ... and 4 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 8.aes_control_fi.2475608627312104393898578633916196238736759291486189619926938792838944347979
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005205705 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005205705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 120.aes_control_fi.102932683995817960118882845089597388744708123996116450744337854021434261786469
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/120.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10416705087 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10416705087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 73.aes_cipher_fi.38945211551040573348099096023788404174601941722995824097830124971215793131556
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/73.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007639919 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007639919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 112.aes_cipher_fi.97926999700317583664996070755877711318059797068935725778314374519765476742580
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/112.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10040594613 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10040594613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.86176971280054086893188720850880672514744385157847940161857097420725653707455
Line 676, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3595384550 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3595384550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.1039500546452389044183923277915775334031572571274239929129904590107530696653
Line 1733, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1600458488 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1600458488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.74547905150404521676598874018164357860533223946879031249112263509812648297749
Line 484, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 143848307 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 143848307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.81568562369412902362251171122113505884778208840517540885959048457792716102975
Line 1212, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1097864344 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1097864344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 41.aes_core_fi.720358021449659551254600406128781695259693751055970541610907926754137558007
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/41.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004544303 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004544303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 55.aes_core_fi.67715864404068230375429773559686116010559400389701014115485012046385766349499
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006324795 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006324795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:826) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.aes_csr_mem_rw_with_rand_reset.33817110540650245899636679312887124379151382374632342712034207526984628986093
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 206344993 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 206344993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_shadow_reg_errors_with_csr_rw has 1 failures.
  - 6.aes_shadow_reg_errors_with_csr_rw.105133401155991485554985978075447835141420442408697189367781658562669020804945
    Line 294, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_FATAL @ 10081299391 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xed3f4d84) == 0x0
  UVM_INFO @ 10081299391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 8.aes_fi.90544806988711704400903116760973876254268984869675428701828240677399195976640
    Line 20669, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_fi/latest/run.log
```
  UVM_FATAL @ 183733542 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 183733542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 26.aes_fi.12768802280846165556100837426407146820918796232885917970345952438892107993523
    Line 1600, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 62448051 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 62406384 PS)
  UVM_ERROR @  62448051 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  62448051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```