AES/MASKED Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: `e6706fcc7b`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	128.123us	1	1	100.00
V1	smoke	aes_smoke	19.000s	603.522us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	125.094us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	66.965us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	887.366us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	10.000s	670.852us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	88.906us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	66.965us	20	20	100.00
		aes_csr_aliasing	10.000s	670.852us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	19.000s	603.522us	50	50	100.00
		aes_config_error	15.000s	70.232us	50	50	100.00
		aes_stress	19.000s	1.222ms	50	50	100.00
V2	key_length	aes_smoke	19.000s	603.522us	50	50	100.00
		aes_config_error	15.000s	70.232us	50	50	100.00
		aes_stress	19.000s	1.222ms	50	50	100.00
V2	back2back	aes_stress	19.000s	1.222ms	50	50	100.00
		aes_b2b	58.000s	775.098us	50	50	100.00
V2	backpressure	aes_stress	19.000s	1.222ms	50	50	100.00
V2	multi_message	aes_smoke	19.000s	603.522us	50	50	100.00
		aes_config_error	15.000s	70.232us	50	50	100.00
		aes_stress	19.000s	1.222ms	50	50	100.00
		aes_alert_reset	16.000s	130.525us	50	50	100.00
V2	failure_test	aes_man_cfg_err	18.000s	114.721us	50	50	100.00
		aes_config_error	15.000s	70.232us	50	50	100.00
		aes_alert_reset	16.000s	130.525us	50	50	100.00
V2	trigger_clear_test	aes_clear	36.000s	1.127ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	1.364ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	16.000s	130.525us	50	50	100.00
V2	stress	aes_stress	19.000s	1.222ms	50	50	100.00
V2	sideload	aes_stress	19.000s	1.222ms	50	50	100.00
		aes_sideload	16.000s	130.516us	50	50	100.00
V2	deinitialization	aes_deinit	1.500m	3.532ms	50	50	100.00
V2	stress_all	aes_stress_all	3.067m	68.702ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	52.382us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	192.864us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	192.864us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	125.094us	5	5	100.00
		aes_csr_rw	7.000s	66.965us	20	20	100.00
		aes_csr_aliasing	10.000s	670.852us	5	5	100.00
		aes_same_csr_outstanding	4.000s	105.319us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	125.094us	5	5	100.00
		aes_csr_rw	7.000s	66.965us	20	20	100.00
		aes_csr_aliasing	10.000s	670.852us	5	5	100.00
		aes_same_csr_outstanding	4.000s	105.319us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	29.000s	1.758ms	50	50	100.00
V2S	fault_inject	aes_fi	16.000s	1.136ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	283	300	94.33
		aes_cipher_fi	49.000s	10.090ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	219.808us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	219.808us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	219.808us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	219.808us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	159.766us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	718.618us	5	5	100.00
		aes_tl_intg_err	5.000s	119.599us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	119.599us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	16.000s	130.525us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	219.808us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	19.000s	603.522us	50	50	100.00
		aes_stress	19.000s	1.222ms	50	50	100.00
		aes_alert_reset	16.000s	130.525us	50	50	100.00
		aes_core_fi	39.000s	1.691ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	219.808us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	61.725us	50	50	100.00
		aes_stress	19.000s	1.222ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	19.000s	1.222ms	50	50	100.00
		aes_sideload	16.000s	130.516us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	61.725us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	61.725us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	61.725us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	61.725us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	61.725us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	19.000s	1.222ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	19.000s	1.222ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	16.000s	1.136ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	16.000s	1.136ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	283	300	94.33
		aes_cipher_fi	49.000s	10.090ms	338	350	96.57
		aes_ctr_fi	19.000s	121.395us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	16.000s	1.136ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	16.000s	1.136ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	283	300	94.33
		aes_cipher_fi	49.000s	10.090ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.090ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	16.000s	1.136ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	16.000s	1.136ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	283	300	94.33
		aes_ctr_fi	19.000s	121.395us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	16.000s	1.136ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	283	300	94.33
		aes_cipher_fi	49.000s	10.090ms	338	350	96.57
		aes_ctr_fi	19.000s	121.395us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	16.000s	130.525us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	16.000s	1.136ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	283	300	94.33
		aes_cipher_fi	49.000s	10.090ms	338	350	96.57
		aes_ctr_fi	19.000s	121.395us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	16.000s	1.136ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	283	300	94.33
		aes_cipher_fi	49.000s	10.090ms	338	350	96.57
		aes_ctr_fi	19.000s	121.395us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	16.000s	1.136ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	283	300	94.33
		aes_ctr_fi	19.000s	121.395us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	16.000s	1.136ms	50	50	100.00
		aes_control_fi	49.000s	10.006ms	283	300	94.33
		aes_cipher_fi	49.000s	10.090ms	338	350	96.57
V2S		TOTAL			954	985	96.85
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.700m	12.481ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1561	1602	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.28	98.48	96.14	99.38	95.74	97.64	97.78	99.11	95.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
- Test aes_control_fi has 11 failures.
  - 16.aes_control_fi.8419801610877599945964296120499509883573653640267464471198227650808048248762
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job ID: smart:2f4f97c3-340c-47b1-a2d9-11f1572dd24d
```
  - 24.aes_control_fi.45510504803901478254241748518102065653145613578200115793595320933165946097555
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/24.aes_control_fi/latest/run.log
```
  Job ID: smart:42f844c6-2567-48fc-92bf-308ca39dc832
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 5 failures.
  - 93.aes_cipher_fi.79746017026714308874620188229347463759056780129994894452686709833239673970004
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/93.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d61ead7e-cbea-4e29-b430-2a5507fd812a
```
  - 153.aes_cipher_fi.78885721866405812893850517244442981185101742575643055544592547453680991726411
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/153.aes_cipher_fi/latest/run.log
```
  Job ID: smart:2381fc74-c6bb-4667-b7de-58b2dcf08763
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 91.aes_cipher_fi.51329714094045936854457135432786546181981966409000168198885795716652225435862
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/91.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015917756 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015917756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 113.aes_cipher_fi.26061303311266861499290131118541159426241311913698422868365167416719416654443
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/113.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10090154065 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10090154065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 11.aes_control_fi.46121777410212556807141210804305964856466028867339300035154490794664469895587
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005689604 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005689604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.aes_control_fi.44202694698594120435913942794502819551817953205071134503290621420902818484849
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014056860 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014056860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.32922879926073748116610534476643902977888358105748992026793224952495955910339
Line 1177, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2044088079 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2044088079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.56580340522911739841865536561488255885713461488005680969923360419516111539064
Line 793, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2378653231 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2378653231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.19391356632602303397835239244858185783132818299730089736875410947439714884951
Line 1652, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1053938548 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1053938548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.114669615223523468265593574915244209024241821895239225243245079914397408917285
Line 1778, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12775545351 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 12775545351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 44.aes_core_fi.39612521153512448632502251530901907006744503463809929440676007060601366002023
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10317574868 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10317574868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 66.aes_core_fi.21487565549705021399535974349987277228153040257448665231535714860958872757113
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/66.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10025741409 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025741409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```