AES/MASKED Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	61.001us	1	1	100.00
V1	smoke	aes_smoke	19.000s	58.304us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	124.255us	5	5	100.00
V1	csr_rw	aes_csr_rw	12.000s	102.364us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	366.266us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	43.000s	10.398ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	90.028us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	12.000s	102.364us	20	20	100.00
		aes_csr_aliasing	43.000s	10.398ms	4	5	80.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	19.000s	58.304us	50	50	100.00
		aes_config_error	11.000s	84.306us	50	50	100.00
		aes_stress	1.650m	6.217ms	50	50	100.00
V2	key_length	aes_smoke	19.000s	58.304us	50	50	100.00
		aes_config_error	11.000s	84.306us	50	50	100.00
		aes_stress	1.650m	6.217ms	50	50	100.00
V2	back2back	aes_stress	1.650m	6.217ms	50	50	100.00
		aes_b2b	44.000s	531.656us	50	50	100.00
V2	backpressure	aes_stress	1.650m	6.217ms	50	50	100.00
V2	multi_message	aes_smoke	19.000s	58.304us	50	50	100.00
		aes_config_error	11.000s	84.306us	50	50	100.00
		aes_stress	1.650m	6.217ms	50	50	100.00
		aes_alert_reset	20.000s	453.840us	50	50	100.00
V2	failure_test	aes_man_cfg_err	11.000s	73.847us	50	50	100.00
		aes_config_error	11.000s	84.306us	50	50	100.00
		aes_alert_reset	20.000s	453.840us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.717m	9.759ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	22.000s	2.050ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	20.000s	453.840us	50	50	100.00
V2	stress	aes_stress	1.650m	6.217ms	50	50	100.00
V2	sideload	aes_stress	1.650m	6.217ms	50	50	100.00
		aes_sideload	22.000s	137.631us	50	50	100.00
V2	deinitialization	aes_deinit	53.000s	1.828ms	50	50	100.00
V2	stress_all	aes_stress_all	1.767m	5.661ms	9	10	90.00
V2	alert_test	aes_alert_test	18.000s	52.352us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	168.466us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	168.466us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	124.255us	5	5	100.00
		aes_csr_rw	12.000s	102.364us	20	20	100.00
		aes_csr_aliasing	43.000s	10.398ms	4	5	80.00
		aes_same_csr_outstanding	11.000s	128.018us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	124.255us	5	5	100.00
		aes_csr_rw	12.000s	102.364us	20	20	100.00
		aes_csr_aliasing	43.000s	10.398ms	4	5	80.00
		aes_same_csr_outstanding	11.000s	128.018us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	2.850m	5.088ms	48	50	96.00
V2S	fault_inject	aes_fi	1.833m	10.253ms	49	50	98.00
		aes_control_fi	46.000s	10.008ms	283	300	94.33
		aes_cipher_fi	50.000s	10.054ms	343	350	98.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	57.175us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	57.175us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	57.175us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	57.175us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	73.731us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	12.000s	827.111us	5	5	100.00
		aes_tl_intg_err	10.000s	294.007us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	294.007us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	20.000s	453.840us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	57.175us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	19.000s	58.304us	50	50	100.00
		aes_stress	1.650m	6.217ms	50	50	100.00
		aes_alert_reset	20.000s	453.840us	50	50	100.00
		aes_core_fi	1.500m	10.005ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	57.175us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	54.437us	50	50	100.00
		aes_stress	1.650m	6.217ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.650m	6.217ms	50	50	100.00
		aes_sideload	22.000s	137.631us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	54.437us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	54.437us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	54.437us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	54.437us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	54.437us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.650m	6.217ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.650m	6.217ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.833m	10.253ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.833m	10.253ms	49	50	98.00
		aes_control_fi	46.000s	10.008ms	283	300	94.33
		aes_cipher_fi	50.000s	10.054ms	343	350	98.00
		aes_ctr_fi	13.000s	97.653us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.833m	10.253ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.833m	10.253ms	49	50	98.00
		aes_control_fi	46.000s	10.008ms	283	300	94.33
		aes_cipher_fi	50.000s	10.054ms	343	350	98.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.054ms	343	350	98.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.833m	10.253ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.833m	10.253ms	49	50	98.00
		aes_control_fi	46.000s	10.008ms	283	300	94.33
		aes_ctr_fi	13.000s	97.653us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.833m	10.253ms	49	50	98.00
		aes_control_fi	46.000s	10.008ms	283	300	94.33
		aes_cipher_fi	50.000s	10.054ms	343	350	98.00
		aes_ctr_fi	13.000s	97.653us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	20.000s	453.840us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.833m	10.253ms	49	50	98.00
		aes_control_fi	46.000s	10.008ms	283	300	94.33
		aes_cipher_fi	50.000s	10.054ms	343	350	98.00
		aes_ctr_fi	13.000s	97.653us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.833m	10.253ms	49	50	98.00
		aes_control_fi	46.000s	10.008ms	283	300	94.33
		aes_cipher_fi	50.000s	10.054ms	343	350	98.00
		aes_ctr_fi	13.000s	97.653us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.833m	10.253ms	49	50	98.00
		aes_control_fi	46.000s	10.008ms	283	300	94.33
		aes_ctr_fi	13.000s	97.653us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.833m	10.253ms	49	50	98.00
		aes_control_fi	46.000s	10.008ms	283	300	94.33
		aes_cipher_fi	50.000s	10.054ms	343	350	98.00
V2S		TOTAL			955	985	96.95
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.667m	8.409ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1560	1602	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.55	96.32	99.43	95.78	97.72	98.52	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
- Test aes_control_fi has 12 failures.
  - 22.aes_control_fi.29832771563503461062130182101822926276828724240331541260017818768130101901186
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job ID: smart:e6898d08-703b-4e33-bb7b-b1c23c791c9d
```
  - 50.aes_control_fi.2963565125113111969679802215095036591130441382090716798328608740166286266387
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/50.aes_control_fi/latest/run.log
```
  Job ID: smart:902f5feb-315b-4553-9093-10a0adc95373
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 4 failures.
  - 195.aes_cipher_fi.54601755045205697467983456479362581848691626565269903675408995722447631207772
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/195.aes_cipher_fi/latest/run.log
```
  Job ID: smart:12c43fe5-0278-46ab-9bfd-7a4e5f81f158
```
  - 234.aes_cipher_fi.5005274581736233879498434779746388704811239513593500002202448679918381963818
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/234.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7b72d96d-7055-48ab-9618-1231677f43a8
```
  - ... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.91974858807688741921467058204998156930777805919077677074560918973202225875925
Line 1097, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4455823689 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4455823689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.113148331032008175693713507854019612870868037926234158851123974239829466096502
Line 679, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5021354106 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5021354106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 200.aes_control_fi.88586918453305094947328203012051356187651197209639545584235390246686691101548
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/200.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007416872 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007416872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 213.aes_control_fi.102795041001150149669466472420658870775843823993462532856407581151707002201569
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/213.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10048969704 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10048969704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 4 failures:

Test aes_stress_all_with_rand_reset has 1 failures.
- 3.aes_stress_all_with_rand_reset.13924086730485883774568580112118399761779240857071075487523963879381012709738
  Line 436, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 581632887 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 581632887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test aes_stress_all has 1 failures.

5.aes_stress_all.50096771423099721764146758163609119485923964361813385021021763651040304864095
Line 62674, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all/latest/run.log

  UVM_FATAL @ 13004154211 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 13004154211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_reseed has 2 failures.

11.aes_reseed.65706990089022746396896238048951422858077672969127754173644551379922279257650
Line 1799, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_reseed/latest/run.log

  UVM_FATAL @ 169034860 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 169034860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.aes_reseed.36442090012133673014471929793905016065424599848320372789970177870786509617761
Line 6315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/30.aes_reseed/latest/run.log

  UVM_FATAL @ 225163264 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 225163264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 19.aes_core_fi.30184883795362096246853054739453923531784670050671073202093466759418243694175
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015881351 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015881351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.aes_core_fi.110605619561810488900764712986507709058254237942251170960176984564866987428007
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/27.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10053377754 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10053377754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 104.aes_cipher_fi.25560984359321491673919742596960670605336420275202194955296179698016802148193
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/104.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008525815 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008525815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 246.aes_cipher_fi.97655230483439197609514040245189023815528356404728792646056244115637842271181
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/246.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10054307611 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10054307611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.77161462382600442788912797903070974336507999456393007932219682357406335843200
    Line 661, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6157470537 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6157470537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_aliasing has 1 failures.
  - 1.aes_csr_aliasing.111196486523342828155563483254414080236522393270900535549493316557924184283321
    Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_csr_aliasing/latest/run.log
```
  UVM_FATAL @ 10398170195 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xa410be84) == 0x0
  UVM_INFO @ 10398170195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.54129236742722549394371893007249866363013220747400599298629788476248732041113
    Line 406, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1525640652 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1525640652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 21.aes_fi.105503625298227921299948489553653865952470717821936871172036468473826041860047
    Line 25289, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/21.aes_fi/latest/run.log
```
  UVM_FATAL @ 104175003 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 104175003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```