AES/UNMASKED Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	104.250us	1	1	100.00
V1	smoke	aes_smoke	6.000s	70.450us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	125.323us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	133.088us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	595.672us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	529.826us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	80.594us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	133.088us	20	20	100.00
		aes_csr_aliasing	5.000s	529.826us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	70.450us	50	50	100.00
		aes_config_error	6.000s	775.935us	50	50	100.00
		aes_stress	38.000s	1.341ms	50	50	100.00
V2	key_length	aes_smoke	6.000s	70.450us	50	50	100.00
		aes_config_error	6.000s	775.935us	50	50	100.00
		aes_stress	38.000s	1.341ms	50	50	100.00
V2	back2back	aes_stress	38.000s	1.341ms	50	50	100.00
		aes_b2b	11.000s	361.045us	50	50	100.00
V2	backpressure	aes_stress	38.000s	1.341ms	50	50	100.00
V2	multi_message	aes_smoke	6.000s	70.450us	50	50	100.00
		aes_config_error	6.000s	775.935us	50	50	100.00
		aes_stress	38.000s	1.341ms	50	50	100.00
		aes_alert_reset	6.000s	106.140us	49	50	98.00
V2	failure_test	aes_config_error	6.000s	775.935us	50	50	100.00
		aes_alert_reset	6.000s	106.140us	49	50	98.00
		aes_man_cfg_err	5.000s	58.653us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	142.219us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	112.319us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	106.140us	49	50	98.00
V2	stress	aes_stress	38.000s	1.341ms	50	50	100.00
V2	sideload	aes_stress	38.000s	1.341ms	50	50	100.00
		aes_sideload	5.000s	130.838us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	342.668us	50	50	100.00
V2	alert_test	aes_alert_test	5.000s	52.617us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	276.391us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	276.391us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	125.323us	5	5	100.00
		aes_csr_rw	3.000s	133.088us	20	20	100.00
		aes_csr_aliasing	5.000s	529.826us	5	5	100.00
		aes_same_csr_outstanding	5.000s	146.214us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	125.323us	5	5	100.00
		aes_csr_rw	3.000s	133.088us	20	20	100.00
		aes_csr_aliasing	5.000s	529.826us	5	5	100.00
		aes_same_csr_outstanding	5.000s	146.214us	20	20	100.00
V2		TOTAL			490	491	99.80
V2S	reseeding	aes_reseed	50.000s	706.116us	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	334.849us	49	50	98.00
		aes_control_fi	55.000s	56.279ms	265	300	88.33
		aes_cipher_fi	56.000s	33.540ms	331	350	94.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	196.551us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	196.551us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	196.551us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	196.551us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	978.251us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.945ms	5	5	100.00
		aes_tl_intg_err	6.000s	424.795us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	424.795us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	106.140us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	196.551us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	70.450us	50	50	100.00
		aes_stress	38.000s	1.341ms	50	50	100.00
		aes_alert_reset	6.000s	106.140us	49	50	98.00
		aes_core_fi	2.150m	10.023ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	196.551us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	38.000s	1.341ms	50	50	100.00
		aes_readability	4.000s	53.862us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	38.000s	1.341ms	50	50	100.00
		aes_sideload	5.000s	130.838us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	53.862us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	53.862us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	53.862us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	53.862us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	53.862us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	38.000s	1.341ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	38.000s	1.341ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	334.849us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	334.849us	49	50	98.00
		aes_control_fi	55.000s	56.279ms	265	300	88.33
		aes_cipher_fi	56.000s	33.540ms	331	350	94.57
		aes_ctr_fi	5.000s	106.133us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	334.849us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	334.849us	49	50	98.00
		aes_control_fi	55.000s	56.279ms	265	300	88.33
		aes_cipher_fi	56.000s	33.540ms	331	350	94.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	56.000s	33.540ms	331	350	94.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	334.849us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	334.849us	49	50	98.00
		aes_control_fi	55.000s	56.279ms	265	300	88.33
		aes_ctr_fi	5.000s	106.133us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	334.849us	49	50	98.00
		aes_control_fi	55.000s	56.279ms	265	300	88.33
		aes_cipher_fi	56.000s	33.540ms	331	350	94.57
		aes_ctr_fi	5.000s	106.133us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	106.140us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	334.849us	49	50	98.00
		aes_control_fi	55.000s	56.279ms	265	300	88.33
		aes_cipher_fi	56.000s	33.540ms	331	350	94.57
		aes_ctr_fi	5.000s	106.133us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	334.849us	49	50	98.00
		aes_control_fi	55.000s	56.279ms	265	300	88.33
		aes_cipher_fi	56.000s	33.540ms	331	350	94.57
		aes_ctr_fi	5.000s	106.133us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	334.849us	49	50	98.00
		aes_control_fi	55.000s	56.279ms	265	300	88.33
		aes_ctr_fi	5.000s	106.133us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	334.849us	49	50	98.00
		aes_control_fi	55.000s	56.279ms	265	300	88.33
		aes_cipher_fi	56.000s	33.540ms	331	350	94.57
V2S		TOTAL			926	985	94.01
V3		TOTAL			0	0	--
		TOTAL			1522	1582	96.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	11	91.67
V2S	11	11	7	63.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	97.63	94.65	98.81	93.80	97.64	91.11	98.07	92.09

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 37 failures:
- Test aes_cipher_fi has 14 failures.
  - 9.aes_cipher_fi.997789062
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  Job ID: smart:a744f9dd-e541-4ddb-8822-aa957a6c72ea
```
  - 10.aes_cipher_fi.2600562834
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b287b5f4-55c1-48ec-a2be-ad94e81ef306
```
  - ... and 12 more failures.
- Test aes_control_fi has 23 failures.
  - 35.aes_control_fi.2831058055
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  Job ID: smart:b65fb7af-0768-48aa-91bb-291243b0212b
```
  - 49.aes_control_fi.4220452124
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_control_fi/latest/run.log
```
  Job ID: smart:3d0baf93-5e78-4c4f-bd21-6b2e1fda28c3
```
  - ... and 21 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 12 failures:

Test aes_control_fi has 12 failures.

81.aes_control_fi.3217368823
Line 276, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/81.aes_control_fi/latest/run.log

  UVM_FATAL @ 10007539387 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007539387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

130.aes_control_fi.766849390
Line 273, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/130.aes_control_fi/latest/run.log

  UVM_FATAL @ 10004393523 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004393523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:

Test aes_cipher_fi has 5 failures.

20.aes_cipher_fi.2490061270
Line 270, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10019435179 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019435179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

190.aes_cipher_fi.1576149729
Line 270, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/190.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10013506798 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013506798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

10.aes_core_fi.552346437
Line 269, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_core_fi/latest/run.log

  UVM_FATAL @ 10008833608 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008833608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

65.aes_core_fi.4246209284
Line 277, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/65.aes_core_fi/latest/run.log

  UVM_FATAL @ 10015345303 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015345303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 1.aes_core_fi.3773421203
    Line 266, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10043893334 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10043893334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 6.aes_core_fi.1521157683
    Line 270, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022624678 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x63d22184) == 0x0
  UVM_INFO @ 10022624678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,984): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

11.aes_alert_reset.1302258204
Line 2075, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 17066576 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 17046576 PS)
  UVM_ERROR @  17066576 ps: (aes_core.sv:984) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  17066576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

33.aes_fi.2265553797
Line 504, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 21540174 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 21500174 PS)
  UVM_ERROR @  21540174 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  21540174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---