748235cbb6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 0 | 1 | 0.00 | ||
| V1 | smoke | aes_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | aes_csr_hw_reset | 8.000s | 64.591us | 5 | 5 | 100.00 |
| V1 | csr_rw | aes_csr_rw | 8.000s | 68.802us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aes_csr_bit_bash | 18.000s | 181.967us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aes_csr_aliasing | 40.000s | 10.227ms | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 12.000s | 56.402us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 8.000s | 68.802us | 20 | 20 | 100.00 |
| aes_csr_aliasing | 40.000s | 10.227ms | 4 | 5 | 80.00 | ||
| V1 | TOTAL | 54 | 106 | 50.94 | |||
| V2 | algorithm | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2 | key_length | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2 | back2back | aes_stress | 0 | 50 | 0.00 | ||
| aes_b2b | 0 | 50 | 0.00 | ||||
| V2 | backpressure | aes_stress | 0 | 50 | 0.00 | ||
| V2 | multi_message | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| V2 | failure_test | aes_man_cfg_err | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| V2 | trigger_clear_test | aes_clear | 0 | 50 | 0.00 | ||
| V2 | nist_test_vectors | aes_nist_vectors | 0 | 1 | 0.00 | ||
| V2 | reset_recovery | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2 | stress | aes_stress | 0 | 50 | 0.00 | ||
| V2 | sideload | aes_stress | 0 | 50 | 0.00 | ||
| aes_sideload | 0 | 50 | 0.00 | ||||
| V2 | deinitialization | aes_deinit | 0 | 50 | 0.00 | ||
| V2 | stress_all | aes_stress_all | 0 | 10 | 0.00 | ||
| V2 | alert_test | aes_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | aes_tl_errors | 10.000s | 319.757us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aes_tl_errors | 10.000s | 319.757us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 8.000s | 64.591us | 5 | 5 | 100.00 |
| aes_csr_rw | 8.000s | 68.802us | 20 | 20 | 100.00 | ||
| aes_csr_aliasing | 40.000s | 10.227ms | 4 | 5 | 80.00 | ||
| aes_same_csr_outstanding | 1.717m | 10.035ms | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 8.000s | 64.591us | 5 | 5 | 100.00 |
| aes_csr_rw | 8.000s | 68.802us | 20 | 20 | 100.00 | ||
| aes_csr_aliasing | 40.000s | 10.227ms | 4 | 5 | 80.00 | ||
| aes_same_csr_outstanding | 1.717m | 10.035ms | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 39 | 501 | 7.78 | |||
| V2S | reseeding | aes_reseed | 0 | 50 | 0.00 | ||
| V2S | fault_inject | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 9.000s | 62.498us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 9.000s | 62.498us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 9.000s | 62.498us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 9.000s | 62.498us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 8.000s | 173.467us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | aes_sec_cm | 0 | 5 | 0.00 | ||
| aes_tl_intg_err | 13.000s | 255.437us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 13.000s | 255.437us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 9.000s | 62.498us | 20 | 20 | 100.00 |
| V2S | sec_cm_main_config_sparse | aes_smoke | 0 | 50 | 0.00 | ||
| aes_stress | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| aes_core_fi | 0 | 70 | 0.00 | ||||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 9.000s | 62.498us | 20 | 20 | 100.00 |
| V2S | sec_cm_aux_config_regwen | aes_readability | 0 | 50 | 0.00 | ||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_key_sideload | aes_stress | 0 | 50 | 0.00 | ||
| aes_sideload | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_key_sca | aes_stress | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_masking | aes_stress | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 0 | 350 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_ctrl_sparse | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | TOTAL | 60 | 985 | 6.09 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 0 | 10 | 0.00 | ||
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 153 | 1602 | 9.55 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 4 | 57.14 |
| V2 | 13 | 13 | 1 | 7.69 |
| V2S | 11 | 11 | 3 | 27.27 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 84.30 | 99.88 | 99.63 | 100.00 | 99.74 | 44.47 | -- | 98.03 | 44.56 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 724 failures:
Test aes_wake_up has 1 failures.
Test aes_deinit has 28 failures.
0.aes_deinit.63726264563163061947573125991626970949322156848242532887480995174186210528348
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_deinit/latest/run.log
1.aes_deinit.76918190542616444157667313953718402487664934774800279696293581996360101299523
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_deinit/latest/run.log
... and 26 more failures.
Test aes_readability has 28 failures.
0.aes_readability.76001666208412695848279084478487093389422037696972541086801725989362478936244
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_readability/latest/run.log
1.aes_readability.93628835822420387555823733292101824331194802512475156999577995179574092551799
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_readability/latest/run.log
... and 26 more failures.
Test aes_config_error has 28 failures.
0.aes_config_error.113742051570137831543560904986094866843575405319306278117353464968625178418731
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_config_error/latest/run.log
1.aes_config_error.53200677682925667145113233124705834753140080914366416767503104592424653275213
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_config_error/latest/run.log
... and 26 more failures.
Test aes_b2b has 28 failures.
0.aes_b2b.86732285564406697445545888392297122971417559248503773565179819178300063986424
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_b2b/latest/run.log
1.aes_b2b.95855512242297866554290324262121071082922966404026428214291446070625421107631
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_b2b/latest/run.log
... and 26 more failures.
... and 16 more tests.
Job killed most likely because its dependent job failed. has 723 failures:
Test aes_nist_vectors has 1 failures.
Test aes_man_cfg_err has 28 failures.
0.aes_man_cfg_err.20598271127640970723942141187272942723265075687847003255041245905256988741167
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
1.aes_man_cfg_err.87576687178345065615068162888527997881378965898448733686317344272118363673862
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
... and 26 more failures.
Test aes_smoke has 28 failures.
0.aes_smoke.42084823399084592930429421418258227713848763047332105694928483995580199155459
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_smoke/latest/run.log
1.aes_smoke.112946893996849300131755655763617205588120723895544317682478329174296785964072
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_smoke/latest/run.log
... and 26 more failures.
Test aes_stress has 28 failures.
0.aes_stress.88488400515566864287170944885420900306447921140305252265933740332292672657277
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress/latest/run.log
1.aes_stress.106050698005866085519773101697221909527179334695863749834027173325739728405425
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress/latest/run.log
... and 26 more failures.
Test aes_clear has 28 failures.
0.aes_clear.19227100727958819180843514657688596918857936517966140454671105538823904279703
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_clear/latest/run.log
1.aes_clear.42884596834207444127109242171417735973152270575509269362247452455063096625461
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_clear/latest/run.log
... and 26 more failures.
... and 15 more tests.
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 2 failures:
Test aes_csr_aliasing has 1 failures.
0.aes_csr_aliasing.63061076391815269902548511988312892956132970619022748673607685894813826154332
Line 283, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_csr_aliasing/latest/run.log
UVM_FATAL @ 10226825441 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x6e631a84) == 0x0
UVM_INFO @ 10226825441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test aes_same_csr_outstanding has 1 failures.
15.aes_same_csr_outstanding.12313627501391467409740293772307834736638410540833600115049295348176975595161
Line 283, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_same_csr_outstanding/latest/run.log
UVM_FATAL @ 10035007425 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x41449384) == 0x0
UVM_INFO @ 10035007425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---