93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 0 | 1 | 0.00 | ||
| V1 | smoke | aes_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | aes_csr_hw_reset | 3.000s | 51.852us | 5 | 5 | 100.00 |
| V1 | csr_rw | aes_csr_rw | 14.000s | 10.080ms | 19 | 20 | 95.00 |
| V1 | csr_bit_bash | aes_csr_bit_bash | 11.000s | 4.787ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aes_csr_aliasing | 5.000s | 793.181us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 5.000s | 90.140us | 6 | 20 | 30.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 14.000s | 10.080ms | 19 | 20 | 95.00 |
| aes_csr_aliasing | 5.000s | 793.181us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 40 | 106 | 37.74 | |||
| V2 | algorithm | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2 | key_length | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2 | back2back | aes_stress | 0 | 50 | 0.00 | ||
| aes_b2b | 0 | 50 | 0.00 | ||||
| V2 | backpressure | aes_stress | 0 | 50 | 0.00 | ||
| V2 | multi_message | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| V2 | failure_test | aes_man_cfg_err | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| V2 | trigger_clear_test | aes_clear | 0 | 50 | 0.00 | ||
| V2 | nist_test_vectors | aes_nist_vectors | 0 | 1 | 0.00 | ||
| V2 | reset_recovery | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2 | stress | aes_stress | 0 | 50 | 0.00 | ||
| V2 | sideload | aes_stress | 0 | 50 | 0.00 | ||
| aes_sideload | 0 | 50 | 0.00 | ||||
| V2 | deinitialization | aes_deinit | 0 | 50 | 0.00 | ||
| V2 | stress_all | aes_stress_all | 0 | 10 | 0.00 | ||
| V2 | alert_test | aes_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | aes_tl_errors | 7.000s | 262.152us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aes_tl_errors | 7.000s | 262.152us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 3.000s | 51.852us | 5 | 5 | 100.00 |
| aes_csr_rw | 14.000s | 10.080ms | 19 | 20 | 95.00 | ||
| aes_csr_aliasing | 5.000s | 793.181us | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 5.000s | 137.623us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 3.000s | 51.852us | 5 | 5 | 100.00 |
| aes_csr_rw | 14.000s | 10.080ms | 19 | 20 | 95.00 | ||
| aes_csr_aliasing | 5.000s | 793.181us | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 5.000s | 137.623us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 40 | 501 | 7.98 | |||
| V2S | reseeding | aes_reseed | 0 | 50 | 0.00 | ||
| V2S | fault_inject | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 4.000s | 268.026us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 4.000s | 268.026us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 4.000s | 268.026us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 4.000s | 268.026us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 5.000s | 526.859us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | aes_sec_cm | 0 | 5 | 0.00 | ||
| aes_tl_intg_err | 6.000s | 910.465us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 6.000s | 910.465us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 4.000s | 268.026us | 20 | 20 | 100.00 |
| V2S | sec_cm_main_config_sparse | aes_smoke | 0 | 50 | 0.00 | ||
| aes_stress | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| aes_core_fi | 0 | 70 | 0.00 | ||||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 4.000s | 268.026us | 20 | 20 | 100.00 |
| V2S | sec_cm_aux_config_regwen | aes_readability | 0 | 50 | 0.00 | ||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_key_sideload | aes_stress | 0 | 50 | 0.00 | ||
| aes_sideload | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_key_sca | aes_stress | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_masking | aes_stress | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 0 | 350 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_ctrl_sparse | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | TOTAL | 60 | 985 | 6.09 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 0 | 10 | 0.00 | ||
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 140 | 1602 | 8.74 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 3 | 42.86 |
| V2 | 13 | 13 | 2 | 15.38 |
| V2S | 11 | 11 | 3 | 27.27 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 84.10 | 99.63 | 98.89 | 100.00 | 99.74 | 44.47 | -- | 98.03 | 43.64 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 724 failures:
Test aes_wake_up has 1 failures.
Test aes_deinit has 28 failures.
0.aes_deinit.13841574810636366637299030816479752144502528219933324812478246075286881190419
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_deinit/latest/run.log
1.aes_deinit.114494632757133035893935064477078655299845448236528464510304888272304872518200
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_deinit/latest/run.log
... and 26 more failures.
Test aes_readability has 28 failures.
0.aes_readability.17093287914188920412436588453504397394316367803145631589089284218146957691587
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_readability/latest/run.log
1.aes_readability.22106304185948286851511143081898447534745430628215478346393596376419481071302
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_readability/latest/run.log
... and 26 more failures.
Test aes_config_error has 28 failures.
0.aes_config_error.4717278108122136799432353668879824361155372359474874629053046680166033461337
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_config_error/latest/run.log
1.aes_config_error.80232901780836760898904584569359502796857308701352802711521588786703971680636
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_config_error/latest/run.log
... and 26 more failures.
Test aes_b2b has 28 failures.
0.aes_b2b.2028464913569294052500315309009146807905042852517469218077795782657735699659
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_b2b/latest/run.log
1.aes_b2b.75089372224176344717262347297677474526583294323907183000316219249009130927307
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_b2b/latest/run.log
... and 26 more failures.
... and 16 more tests.
Job killed most likely because its dependent job failed. has 723 failures:
Test aes_nist_vectors has 1 failures.
Test aes_man_cfg_err has 28 failures.
0.aes_man_cfg_err.54742214136095333002298143091746310316814168518493805699389917025138210535218
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
1.aes_man_cfg_err.101938065057386621205804805501741961286863482252547681236345981324431281614463
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
... and 26 more failures.
Test aes_smoke has 28 failures.
0.aes_smoke.17739499335325259748310975256927050635160995817072503504746255821906516327238
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_smoke/latest/run.log
1.aes_smoke.113129796070101497786794087944427413907592429403861314032073313687145187433750
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_smoke/latest/run.log
... and 26 more failures.
Test aes_stress has 28 failures.
0.aes_stress.59907571555552282627684601328121164904949140964707744619742380557384642387010
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress/latest/run.log
1.aes_stress.28931668612906858962209382810118411900376340858387481411849694220535378490172
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress/latest/run.log
... and 26 more failures.
Test aes_clear has 28 failures.
0.aes_clear.30133750240871592906092896819456269679175088324804902655297392839205495099321
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_clear/latest/run.log
1.aes_clear.63774589955835242401880476301806969579557607471227878304367198945897773487392
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_clear/latest/run.log
... and 26 more failures.
... and 15 more tests.
UVM_ERROR (cip_base_vseq.sv:757) [aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 8 failures:
1.aes_csr_mem_rw_with_rand_reset.40768255489132174459006046806553155900040374656196795067674170174372570735245
Line 284, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 31152641 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 31152641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.aes_csr_mem_rw_with_rand_reset.26256823546539267222106459351908672523021798757054955794795664215877552154294
Line 284, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 75365532 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 75365532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:757) [aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 6 failures:
4.aes_csr_mem_rw_with_rand_reset.37051603828834047779665307681479122112976608893189056073510420713439432061185
Line 284, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 13714647 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 13714647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.aes_csr_mem_rw_with_rand_reset.29528376894112107934027072975006027518144137505381247766013820890670968152280
Line 284, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 308765668 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
UVM_INFO @ 308765668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
5.aes_csr_rw.101979236906453237731581885033397099434793841463449602838238819840088685903343
Line 284, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_csr_rw/latest/run.log
UVM_FATAL @ 10080386727 ps: (csr_utils_pkg.sv:572) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x88d0f084) == 0x0
UVM_INFO @ 10080386727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---