AON_TIMER Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.500s 554.977us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 1.900s 1.084ms 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.510s 511.580us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 9.980s 6.030ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.810s 576.214us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.420s 556.064us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.510s 511.580us 20 20 100.00
aon_timer_csr_aliasing 1.810s 576.214us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 1.080s 506.882us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 1.250s 483.666us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.450m 60.782ms 50 50 100.00
V2 jump aon_timer_jump 1.610s 632.128us 50 50 100.00
V2 stress_all aon_timer_stress_all 7.653m 312.083ms 50 50 100.00
V2 intr_test aon_timer_intr_test 1.390s 515.880us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 2.970s 555.909us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 2.970s 555.909us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 1.900s 1.084ms 5 5 100.00
aon_timer_csr_rw 1.510s 511.580us 20 20 100.00
aon_timer_csr_aliasing 1.810s 576.214us 5 5 100.00
aon_timer_same_csr_outstanding 4.420s 2.201ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 1.900s 1.084ms 5 5 100.00
aon_timer_csr_rw 1.510s 511.580us 20 20 100.00
aon_timer_csr_aliasing 1.810s 576.214us 5 5 100.00
aon_timer_same_csr_outstanding 4.420s 2.201ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S tl_intg_err aon_timer_sec_cm 10.680s 8.067ms 5 5 100.00
aon_timer_tl_intg_err 15.060s 8.484ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 15.060s 8.484ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 15.767m 104.932ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 430 430 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.50 99.82 94.68 100.00 -- 99.35 100.00 97.16

Past Results