AON_TIMER Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: a9c19f09f3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.500s 588.151us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 2.510s 1.260ms 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.310s 413.099us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 13.980s 5.884ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.640s 502.555us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.600s 605.692us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.310s 413.099us 20 20 100.00
aon_timer_csr_aliasing 1.640s 502.555us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 1.240s 465.188us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 1.000s 302.247us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.576m 61.578ms 50 50 100.00
V2 jump aon_timer_jump 1.510s 552.210us 50 50 100.00
V2 stress_all aon_timer_stress_all 14.063m 484.555ms 50 50 100.00
V2 intr_test aon_timer_intr_test 1.250s 492.833us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 2.790s 539.642us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 2.790s 539.642us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 2.510s 1.260ms 5 5 100.00
aon_timer_csr_rw 1.310s 413.099us 20 20 100.00
aon_timer_csr_aliasing 1.640s 502.555us 5 5 100.00
aon_timer_same_csr_outstanding 4.730s 1.919ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 2.510s 1.260ms 5 5 100.00
aon_timer_csr_rw 1.310s 413.099us 20 20 100.00
aon_timer_csr_aliasing 1.640s 502.555us 5 5 100.00
aon_timer_same_csr_outstanding 4.730s 1.919ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S tl_intg_err aon_timer_sec_cm 5.510s 4.600ms 5 5 100.00
aon_timer_tl_intg_err 14.280s 7.865ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 14.280s 7.865ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 18.043m 243.800ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 430 430 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.56 99.82 95.32 100.00 -- 99.35 100.00 96.90

Past Results