AON_TIMER Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: 8faf04697a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.410s 556.303us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 1.490s 1.261ms 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.420s 530.458us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 13.800s 11.615ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.480s 443.613us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 3.220s 718.522us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.420s 530.458us 20 20 100.00
aon_timer_csr_aliasing 1.480s 443.613us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 1.340s 508.642us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 1.190s 454.968us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.506m 61.422ms 50 50 100.00
V2 jump aon_timer_jump 1.480s 596.861us 50 50 100.00
V2 stress_all aon_timer_stress_all 8.081m 358.636ms 50 50 100.00
V2 intr_test aon_timer_intr_test 1.300s 477.965us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 3.010s 410.424us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 3.010s 410.424us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 1.490s 1.261ms 5 5 100.00
aon_timer_csr_rw 1.420s 530.458us 20 20 100.00
aon_timer_csr_aliasing 1.480s 443.613us 5 5 100.00
aon_timer_same_csr_outstanding 3.860s 2.168ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 1.490s 1.261ms 5 5 100.00
aon_timer_csr_rw 1.420s 530.458us 20 20 100.00
aon_timer_csr_aliasing 1.480s 443.613us 5 5 100.00
aon_timer_same_csr_outstanding 3.860s 2.168ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S tl_intg_err aon_timer_sec_cm 13.970s 8.518ms 5 5 100.00
aon_timer_tl_intg_err 13.600s 8.854ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 13.600s 8.854ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 19.014m 174.112ms 42 50 84.00
V3 TOTAL 42 50 84.00
TOTAL 422 430 98.14

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.82 95.31 100.00 -- 99.35 100.00 96.64

Failure Buckets

Past Results