AON_TIMER Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: 0dd29ab736

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.480s 551.709us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 2.160s 928.729us 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.420s 454.887us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 19.190s 11.774ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.670s 580.603us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.520s 596.535us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.420s 454.887us 20 20 100.00
aon_timer_csr_aliasing 1.670s 580.603us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 1.090s 404.756us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 0.840s 263.889us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.290m 47.039ms 50 50 100.00
V2 jump aon_timer_jump 1.520s 572.008us 50 50 100.00
V2 stress_all aon_timer_stress_all 12.289m 485.330ms 50 50 100.00
V2 intr_test aon_timer_intr_test 1.290s 474.170us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 3.010s 591.179us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 3.010s 591.179us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 2.160s 928.729us 5 5 100.00
aon_timer_csr_rw 1.420s 454.887us 20 20 100.00
aon_timer_csr_aliasing 1.670s 580.603us 5 5 100.00
aon_timer_same_csr_outstanding 5.030s 1.775ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 2.160s 928.729us 5 5 100.00
aon_timer_csr_rw 1.420s 454.887us 20 20 100.00
aon_timer_csr_aliasing 1.670s 580.603us 5 5 100.00
aon_timer_same_csr_outstanding 5.030s 1.775ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S tl_intg_err aon_timer_sec_cm 12.970s 7.629ms 5 5 100.00
aon_timer_tl_intg_err 13.450s 8.147ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 13.450s 8.147ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 21.376m 509.337ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 430 430 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.56 99.82 95.31 100.00 -- 99.35 100.00 96.90

Past Results