AON_TIMER Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: 5c87d18988

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.460s	575.740us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.940s	1.397ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.290s	485.486us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	8.710s	6.059ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.260s	401.328us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.550s	573.303us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.290s	485.486us	20	20	100.00
		aon_timer_csr_aliasing	1.260s	401.328us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.160s	420.480us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.060s	401.722us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.470m	61.478ms	50	50	100.00
V2	jump	aon_timer_jump	1.510s	590.836us	50	50	100.00
V2	stress_all	aon_timer_stress_all	16.480m	622.859ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.350s	434.100us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.920s	1.031ms	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.920s	1.031ms	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.940s	1.397ms	5	5	100.00
		aon_timer_csr_rw	1.290s	485.486us	20	20	100.00
		aon_timer_csr_aliasing	1.260s	401.328us	5	5	100.00
		aon_timer_same_csr_outstanding	6.690s	2.613ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.940s	1.397ms	5	5	100.00
		aon_timer_csr_rw	1.290s	485.486us	20	20	100.00
		aon_timer_csr_aliasing	1.260s	401.328us	5	5	100.00
		aon_timer_same_csr_outstanding	6.690s	2.613ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	6.670s	3.950ms	5	5	100.00
		aon_timer_tl_intg_err	14.540s	8.533ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.540s	8.533ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	26.579m	275.040ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			429	430	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.56	99.82	95.31	100.00	--	99.35	100.00	96.90

Failure Buckets

• UVM_ERROR (aon_timer_scoreboard.sv:360) [scoreboard] Check failed wdog_rst_req_exp === cfg.aon_intr_vif.sample_pin(.idx(0)) (* [*] vs * [*]) has 1 failures:
  • Test aon_timer_stress_all has 1 failures.

    • 42.aon_timer_stress_all.39975056322883397987069300723335719462540534298943430350640484723885250292202
      Line 301, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/42.aon_timer_stress_all/latest/run.log

        UVM_ERROR @ 140355794805 ps: (aon_timer_scoreboard.sv:360) [uvm_test_top.env.scoreboard] Check failed wdog_rst_req_exp === cfg.aon_intr_vif.sample_pin(.idx(0)) (0x1 [1] vs 0x0 [0])
        UVM_INFO @ 140355794805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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