AON_TIMER Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: 796f9fb805

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.420s 568.479us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 1.660s 694.708us 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.400s 503.950us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 17.970s 7.891ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.370s 504.453us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.610s 619.813us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.400s 503.950us 20 20 100.00
aon_timer_csr_aliasing 1.370s 504.453us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 0.980s 309.422us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 1.240s 485.874us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.477m 59.439ms 50 50 100.00
V2 jump aon_timer_jump 1.570s 622.881us 50 50 100.00
V2 stress_all aon_timer_stress_all 8.097m 318.386ms 49 50 98.00
V2 intr_test aon_timer_intr_test 1.400s 509.945us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 2.780s 546.944us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 2.780s 546.944us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 1.660s 694.708us 5 5 100.00
aon_timer_csr_rw 1.400s 503.950us 20 20 100.00
aon_timer_csr_aliasing 1.370s 504.453us 5 5 100.00
aon_timer_same_csr_outstanding 5.850s 2.546ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 1.660s 694.708us 5 5 100.00
aon_timer_csr_rw 1.400s 503.950us 20 20 100.00
aon_timer_csr_aliasing 1.370s 504.453us 5 5 100.00
aon_timer_same_csr_outstanding 5.850s 2.546ms 20 20 100.00
V2 TOTAL 239 240 99.58
V2S tl_intg_err aon_timer_sec_cm 12.430s 7.547ms 5 5 100.00
aon_timer_tl_intg_err 13.170s 8.121ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 13.170s 8.121ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 17.951m 430.589ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 429 430 99.77

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 5 83.33
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.56 99.82 95.31 100.00 -- 99.35 100.00 96.90

Failure Buckets

Past Results