AON_TIMER Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.530s	599.207us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.670s	766.526us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.410s	520.771us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	18.890s	11.294ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.460s	628.002us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.540s	557.089us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.410s	520.771us	20	20	100.00
		aon_timer_csr_aliasing	1.460s	628.002us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.290s	461.130us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.300s	480.635us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.443m	56.670ms	50	50	100.00
V2	jump	aon_timer_jump	1.580s	530.018us	50	50	100.00
V2	stress_all	aon_timer_stress_all	9.421m	322.544ms	50	50	100.00
V2	intr_test	aon_timer_intr_test	1.380s	501.091us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.910s	608.740us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.910s	608.740us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.670s	766.526us	5	5	100.00
		aon_timer_csr_rw	1.410s	520.771us	20	20	100.00
		aon_timer_csr_aliasing	1.460s	628.002us	5	5	100.00
		aon_timer_same_csr_outstanding	4.320s	2.371ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.670s	766.526us	5	5	100.00
		aon_timer_csr_rw	1.410s	520.771us	20	20	100.00
		aon_timer_csr_aliasing	1.460s	628.002us	5	5	100.00
		aon_timer_same_csr_outstanding	4.320s	2.371ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	tl_intg_err	aon_timer_sec_cm	7.570s	4.488ms	5	5	100.00
		aon_timer_tl_intg_err	14.680s	8.421ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.680s	8.421ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.404m	1.127s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			430	430	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test aon_timer has 1 failures.

cov_merge
Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/cov_merge/merged.vdb/cov_merge.log

              Inclusivity and Diversity" (Refer to article 000036315 at
                          https://solvnetplus.synopsys.com)
  
  Error-[URG-NLCW] No license key
    URG failed to get a license key. Number of attempts to get a license key
    exceeded the limit (500).
    Please check for 'VCSTools_Net' or 'VT_CoverageURG' key in your license
    file.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:220: cov_merge] Error 1

Job killed most likely because its dependent job failed. has 1 failures:
- Test aon_timer has 1 failures.
  - cov_report
    Log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/cov_report/cov_report.log