AON_TIMER Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: df66f8a42e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.540s	605.009us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.660s	763.111us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.230s	407.868us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	22.870s	11.703ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.540s	608.407us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.600s	570.990us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.230s	407.868us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	608.407us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.990s	328.545us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.220s	437.170us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.335m	52.818ms	50	50	100.00
V2	jump	aon_timer_jump	1.480s	634.845us	50	50	100.00
V2	stress_all	aon_timer_stress_all	14.270m	519.332ms	50	50	100.00
V2	intr_test	aon_timer_intr_test	1.360s	506.705us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.870s	515.603us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.870s	515.603us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.660s	763.111us	5	5	100.00
		aon_timer_csr_rw	1.230s	407.868us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	608.407us	5	5	100.00
		aon_timer_same_csr_outstanding	6.260s	2.307ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.660s	763.111us	5	5	100.00
		aon_timer_csr_rw	1.230s	407.868us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	608.407us	5	5	100.00
		aon_timer_same_csr_outstanding	6.260s	2.307ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	tl_intg_err	aon_timer_sec_cm	7.050s	4.352ms	5	5	100.00
		aon_timer_tl_intg_err	13.630s	8.169ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.630s	8.169ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	19.734m	312.530ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			428	430	99.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.82	95.31	100.00	--	99.35	100.00	96.64

Failure Buckets

• UVM_ERROR (aon_timer_scoreboard.sv:274) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*]) has 2 failures:
  • Test aon_timer_stress_all_with_rand_reset has 2 failures.

    • 11.aon_timer_stress_all_with_rand_reset.67422955719832492601052822655220716220378498966993581635229881431987936168857
      Line 410, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 51374318140 ps: (aon_timer_scoreboard.sv:274) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
        UVM_INFO @ 51374318140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 24.aon_timer_stress_all_with_rand_reset.111644658391462948068093287991585988186217989189929523870429680588853088428900
      Line 1128, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 297002747347 ps: (aon_timer_scoreboard.sv:274) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
        UVM_INFO @ 297002747347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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