AON_TIMER Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: 49a27e136c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.500s 570.892us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 2.230s 1.114ms 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.310s 521.516us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 23.670s 11.315ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 0.970s 612.465us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.660s 622.611us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.310s 521.516us 20 20 100.00
aon_timer_csr_aliasing 0.970s 612.465us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 1.210s 478.413us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 0.880s 497.609us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.295m 59.323ms 50 50 100.00
V2 jump aon_timer_jump 1.500s 584.612us 50 50 100.00
V2 stress_all aon_timer_stress_all 11.259m 394.378ms 50 50 100.00
V2 intr_test aon_timer_intr_test 1.350s 490.175us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 2.800s 395.032us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 2.800s 395.032us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 2.230s 1.114ms 5 5 100.00
aon_timer_csr_rw 1.310s 521.516us 20 20 100.00
aon_timer_csr_aliasing 0.970s 612.465us 5 5 100.00
aon_timer_same_csr_outstanding 6.540s 2.023ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 2.230s 1.114ms 5 5 100.00
aon_timer_csr_rw 1.310s 521.516us 20 20 100.00
aon_timer_csr_aliasing 0.970s 612.465us 5 5 100.00
aon_timer_same_csr_outstanding 6.540s 2.023ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S tl_intg_err aon_timer_sec_cm 3.510s 4.501ms 5 5 100.00
aon_timer_tl_intg_err 13.470s 7.646ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 13.470s 7.646ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 16.184m 436.536ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 430 430 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.82 95.31 100.00 -- 99.35 100.00 96.64

Past Results